Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) IRDA
8.4-13
6.3 IRDA INTERRUPT / DMA CONFIGURATION REGISTER (IRDA_CNF, R/W, ADDRESS = 0XEC60_0008)
IrDA _CNF Bit Description Initial State
Reserved [7:4] - 0
DMA Enable [3] 1 : DMA Enable 0
DMA Mode [2] 0 : Tx DMA 1 : Rx DMA 0
Reserved [1] - 0
Interrupt Enable [0] The bit 0 enables Interrupt output signal. 0
6.4 IRDA INTERUPT ENALBLE REGISTER(IRDA_IER, R/W, ADDRESS = 0XEC60_000C)
IrDA_IER Bit Description Initial State
Last Byte to Rx
FIFO [7] Enables state indication interrupt. If Last byte write to RX FIFO. 0
Error Indication [6] Enables error status indication interrupt in data receiving mode. 0
Tx Underrun [5] Enables transmitter under-run interrupt. 0
Last Byte Detect [4] Detect stop-flag interrupt enable. If this bit is set to "1", an
interrupt signal is activated if the last byte of the received data
frame comes into the demodulation block and CRC decoding is
finished. 0
Rx Overrun [3] Enables receiver over-run interrupt. 0
Last Byte Read
from Rx FIFO [2] Bit 2 enables last byte from RX FIFO interrupt which is generated
if the microcontroller reads the last byte of the frame from the RX
FIFO. 0
Tx FIFO Below
Threshold [1] Bit 1 enables a TX FIFO below threshold level interrupt if the
available empty space in TX FIFO is over the threshold level. 0
Rx FIFO Over
Threshold [0] Bit 0 enables received data in RX FIFO over threshold level
interrupt if the RX FIFO is equal to or above the threshold level. 0