Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) CLOCK CONTROLLER
2.3-11
6 CLOCK CONFIGURATION PROCEDURE
Some basic SFR configuration flows are listed below.
1. Turn on a PLL
(A,M,E,H)PLL_CON[31] = 1; // Power on a PLL (Refer (A, M, E, H)PLL_CON SFR)
wait_lock_time; // If you want to wait until PLL clock is out (locking time passed),
// check assertion of (A. M, E, H)PLL_CON[30].
(A, M, E, H)PLL_SEL = 1; // Select the PLL output clock.
(Refer 0, 4, 8, 12th bit of CLK_SRC0 SFR)
2. Turn off a PLL
(A,M,E,H)PLL_SEL = 0; // De-select the output of a PLL
(A,M,E,H)PLL_CON[31] = 0; // Power off the PLL
Must follow above procedure 1, 2
3. Change PLL’s PMS values
Set PMS values; // Set PDIV, MDIV, and SDIV values
(Refer (A,M,E,H)PLL_CON SFR)
4. Change the system clock divider values
CLK_DIV0 [31:0] = target value0;
5. Change the divider values for special clocks
CLK_DIV1 [31:0] = target value1;
CLK_DIV2 [31:0] = target value2;
Can change PMS value (procedure 3), dividing value (procedure 4, 5) freely without stopping clock.
6.1 CLOCK GATING
S5PC100 can disable the clock operation of each IP if it is not required. This reduces dynamic power.