Samsung S5PC100, Руководство пользователя

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USB2.0 HS OTG S5PC100 USER’S MANUAL (REV1.0)
8.10 -48
HPRT Bit Description R/W Reset
Value
PrtRst [8] Port Reset
If the application sets this bit, a reset sequence is started on this
port. The application must time the reset period and clear this
bit after the reset sequence is complete.
•
1'b0 : Port not in reset
•
1'b1 : Port in reset
The application must leave this bit set for at least a minimum
duration mentioned below to start a reset on the port. The
application can leave it set for another 10ms in addition to the
required minimum duration, before clearing the bit, even though
there is no maximum limit set by the USB standard.
•
High speed : 50 ms
•
Full speed/Low speed : 10ms
R/W 1'b0
prtSusp [7] Port Suspend
The application sets this bit to put this port in Suspend mode.
The core stops sending SOFs if this is set. To stop the PHY
clock, the application must set the Port Clock Stop bit, which
asserts the suspend input pin of the PHY.
The read value of this bit reflects the current suspend status of
the port. This bit is cleared by the core after a remote wakeup
signal is detected or the application sets the Port Reset bit or
Port Resume bit in this register or the Resume/Remote Wakeup
Detected Interrupt bit or Disconnect Detected Interrupt bit in the
Core Interrupt register.
•
1'b0 : Port not in Suspend mode
•
1'b1 : Port in Suspend mode
R_WS
_SC
1'b0
PrtRes [6] Port Resume
The application sets this bit to drive resume signaling on the
port. The core continues to drive the resume signal until the
application clears this bit. If the core detects a USB remote
wakeup sequence, as indicated by the Port Resume/ Remote
Wakeup Detected Interrupt bit of the Core Interrupt register, the
core starts driving resume signaling without application
intervention and clears this bit if it detects a disconnect
condition. The read value of this bit indicates whether the core
is currently driving resume signaling.
•
1'b0 : No resume driven
•
1'b1 : Resume driven
R_W_
SS_S
C
1'b0
PrtOvr
CurrChng [5] Port Overcurrent Change
The core sets this bit if the status of the Port Overcurrent Active
bit (bit 4) in this register changes. R_SS_
WC
1'b0
PrtOvr
CurrAct [4] Port Overcurrent Active
Indicates the overcurrent condition of the port.
•
1'b0 : No overcurrent condition
•
1'b1 : Overcurrent condition
R 1'b0