Samsung S5PC100, Руководство пользователя

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S5PC100 USER’S MANUAL (REV1.0) MODEM INTERFACE
8.11-3
3 INTERRUPT PORTS
Interrupts are requested or cleared if the Modem chip or the AP accesses the interrupt-port (predefined special
addresses). That special address is configured by the AP and the default address-map is shown in the Table 8.11-
1.
Table 8.11-1 Interrupt Request and Clear Conditions
Interrupt An Interrupt is requested, when The Interrupt is cleared, when
To AP Modem chip writes at least 1 to
0x1FFF through ADR. AP writes at least 1 to MSMINTCLR register in
MODEM IF (
NOTE 2 ).
To Modem AP writes 1 to 0xED50_3FFC
through internal-chip AHB bus. Modem chip writes 1 to the bits at 0x1FFE
through ADR.
NOTE:
1. There are two address views for MODEMIF, one is MSM address (ADR) for MODEM chip, and the other one is AHB
address for S5PC100. AHB address is twice of ADR. For example, 0x3FFC at AHB bus is 0x1FFE at ADR.
Figure 8.11-2 helps you to understand it.
This is default value. It can be set to other value by the SFR. (INT2AP and INT2MSM)
2. Modem interface block has one Interrupt Clear Registers; MSMINTCLR. Level type interrupt request is generated by
modem interface block and is sustained until the AP clears the interrupt clear registers by writing any value to the
registers.
Modem chip or AP (S5PC100) reads the data that indicates what event happens
−
data transfer requested, data
transfer done, special command issued, etc.
−
from interrupt port address. That data format should be defined for
communication between the modem chip and AP.
3.1 WAKEUP
* Standard mode
To assert wakeup at IDLE/ STOP mode, write 0x1100~0x117F to ADR[12:0]
To clear wakeup signal, write 0x1180~0x11FF to ADR[12:0]
* Address Muxed mode
To assert wakeup at IDLE/STOP mode, assert chip select (XmsmCsn) and address valid (XmsmADDR[4])
To clear wakeup signal, assert chip select (XmsmCsn) and address valid (XmsmADDR[4]) again