Samsung S5PC100, Руководство пользователя

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DRAM CONTROLLER S5PC100 USER’S MANUAL (REV1.0)
5.1-8
2.3 LOW POWER OPERATION
The controller executes a low power memory operation in five ways as described below. Each feature is
independent of each other and executed at the same time.
2.3.1 AXI low Power Channel
The controller has an AXI low power channel interface to communicate with low power management units such as
the system controller, which makes the memory device go into self-refresh mode. To request through the AXI low
power channel, refer the
chip1_empty and chip0_empty bit-fields of ConControl register to check if the
command queue is currently empty.
2.3.2 Dynamic Power Down
The SDRAM device has an active/ precharge power down mode. This mode is entered if CKE becomes LOW. To
enter active power down mode minimum one row of a bank must be open. To enter precharge power down mode
CKE must be low.
If no AXI transaction enters the controller and the command queue becomes empty for a specific number of cycles
(
PwrdnConfig.dpwrdn_cyc bit-field), the controller changes the memory device’s state to active/ precharge
power down automatically. Then, there are two ways to enter the active/ precharge power down state and It is
selected by
MEMCONTROL.dpwrdn_type bit.
1. Active/ precharge power down mode: Enter power down without considering whether there is a row open or
not,
2. Force precharge power down mode: Enter power down after closing all banks.
If a new AXI transaction enters the controller, the controller automatically wakes up the memory device from
power down state and executes in a normal operation state.
2.3.3 Dynamic Self Refresh
Similar to the dynamic power down feature (Refer to Section 2.3.2 Dynamic Power Down), if the command queue
is empty for a specific amount of cycles (
PwrdnConfig.dsref_cyc bit-field ) , the memory device enters self-refresh
mode. Since exiting power down mode requires many cycles, we recommend to choose a greater cycle size for
dynamic self-refresh entry than dynamic power down.
2.3.4 Clock Stop
To reduce the I/O power of the memory device and the controller, it is possible to stop the clock if the LPDDR /
LPDDR2 is in idle mode, or self refresh mode and DDR2 is in self refresh mode. If this feature is enabled, the
controller automatically executes the clock stop feature.
2.3.5 Direct Command
Use the direct command feature to send a command to the memory device through the APB3 port. This way, you
force the memory device to enter active/ precharge power down, self-refresh or deep power down mode