Network Operation and Remote Control
R&S
®
FPL1000
562
User Manual 1178.3370.02 ─ 11
A separate LMARgin register exists for each active channel and for each window.
It can be read using the commands
STATus:QUEStionable:LMARgin:CONDition?
and
STATus:QUEStionable:LMARgin[:EVENt]?
.
Table 9-11: Meaning of the bits used in the STATus:QUEStionable:LMARgin register
Bit No.
Meaning
0
LMARgin 1 FAIL
This bit is set if limit margin 1 is violated.
1
LMARgin 2 FAIL
This bit is set if limit margin 2 is violated.
2
LMARgin 3 FAIL
This bit is set if limit margin 3 is violated.
3
LMARgin 4 FAIL
This bit is set if limit margin 4 is violated.
4
LMARgin 5 FAIL
This bit is set if limit margin 5 is violated.
5
LMARgin 6 FAIL
This bit is set if limit margin 6 is violated.
6
LMARgin 7 FAIL
This bit is set if limit margin 7 is violated.
7
LMARgin 8 FAIL
This bit is set if limit margin 8 is violated.
8 to 14
Not used
15
This bit is always 0.
9.2.2.12
STATus:QUEStionable:POWer Register
The
STATus:QUEStionable:POWer
register contains information about possible
overload situations that may occur during operation of the R&S
FPL1000. A separate
power register exists for each active channel.
You can read out the register with
STATus:QUEStionable:POWer:CONDition?
or
STATus:QUEStionable:POWer[:EVENt]?
Table 9-12: Meaning of the bits used in the STATus:QUEStionable:POWer register
Bit No.
Meaning
0
OVERload
This bit is set if an overload occurs at the RF input, causing signal distortion but not yet causing
damage to the device.
The R&S
FPL1000 displays the keyword "RF OVLD".
1
Unused
2
Unused
Status Reporting System
