Omron CP1L - 12-2007, Operation Manual

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44
Specifications
Section 2-2
Note Can be used as Modbus-RTU easy master function.
2-2-2 I/O Memory Details
Clock function Supported.
Accuracy (monthly deviation): 4.5 min to
−
0.5 min (ambient temperature: 55
°
C),
−
2.0 min to +2.0 min (ambient temperature: 25
°
C),
−
2.5 min to +1.5 min (ambient temperature: 0
°
C)
Memory
Backup Built-in flash
memory User programs and parameters (such as the PLC Setup) are automatically saved to the
flash memory. It is also possible to save and read data memory initial data.
The data is automatically transferred to RAM when the power supply is turned ON.
(Data memory initial data, however, may or may not be transferred, depending on the
selection in the PLC Setup.
Battery backup The HR Area, DM Area, and counter values (flags, PV) are backed up by a battery.
Battery model: CJ1W-BAT01 (Built into the CP1L CPU Unit.)
Maximum battery service life: 5 years
Guaranteed (ambient temperature: 55°C): 13,000 hours (approx. 1.5 years)
Effective value (ambient temperature: 25°C): 43,000 hours (approx. 5 years)
Memory Cassette function A CP1W-ME05M Memory Cassette (512K words, optional)
can be mounted. It can be used to back up the following
data on the CPU Unit's RAM and to transfer the data at
startup.
• Data saved on Memory Cassette: User programs,parame-
ters (such as the PLC Setup), DM Area, data memory ini-
tial data, comment memory (CX-Programmer conversion
tables, comments, program indices), and FB program
memory.
• Writing to Memory Cassette: By operations from the CX-
Programmer.
• Reading from Memory Cassette: At startup or by opera-
tions from the CX-Programmer.
Unusable
Type M CPU Units L CPU Units J CPU Units
Model CP1L-M40DR-A
CP1L-M40DR-D
CP1L-M40DT-D
CP1L-M40DT1-D
CP1L-M30DR-A
CP1L-M30DR-D
CP1L-M30DT-D
CP1L-M30DT1-D
CP1L-L20DR-A
CP1L-L20DR-D
CP1L-L20DT-D
CP1L-L20DT1-D
CP1L-L14DR-A
CP1L-L14DR-D
CP1L-L14DT-D
CP1L-L14DT1-D
CP1L-J20DR-A
CP1L-J20DR-D
CP1L-J20DT1-D
CP1L-J14DR-A
CP1L-J14DR-D
CP1L-J14DT1-D
I/O
Areas Input bits 24 bits
CIO 0.00 to
CIO 0.11
CIO 1.00 to
CIO 1.11
18 bits
CIO 0.00 to
CIO 0.11
CIO 1.00 to
CIO 1.05
12 bits
CIO 0.00 to
CIO 0.11
8 bits
CIO 0.00 to
CIO 0.07
12 bits
CIO 0.00 to
CIO 0.11
8 bits
CIO 0.00 to
CIO 0.07
Output bits 16 bits
CIO 100.00 to
CIO 100.07
CIO 101.00 to
CIO 101.11
12 bits
CIO 100.00 to
CIO 100.07
CIO 101.00 to
CIO 100.03
8 bits
CIO 100.00 to
CIO 100.07
6 bits
CIO 100.00 to
CIO 100.05
8 bits
CIO 100.00 to
CIO 100.07
6 bits
CIO 100.00 to
CIO 100.05
1:1 Link Bit
Area 1024 bits (64 words): CIO 3000.00 to CIO 3063.15 (words CIO 3000 to CIO 3063)
Serial PLC
Link Area 1,440 bits (90 words): CIO 3100.00 to CIO 3189.15 (words CIO 3100 to CIO 3189)
Work bits 4,800 bits (300 words): CIO 1200.00 to CIO 1499.15 (words CIO 1200 to CIO 1499)
6,400 bits (400 words): CIO 1500.00 to CIO 1899.15 (words CIO 1500 to CIO 1899)
15,360 bits (960 words): CIO 2000.00 to CIO 2959.15 (words CIO 2000 to CIO 2959)
9,600 bits (600 words): CIO 3200.00 to CIO 3799.15 (words CIO 3200 to CIO 3799)
37,504 bits (2,344 words): CIO 3800.00 to CIO 6143.15 (words CIO 3800 to CIO 6143)
Work bits 8,192 bits (1,536 words): W000.00 to W511.15 (words W0 to W511)
TR Area 16 bits: TR0 to TR15
Type M CPU Units L CPU Units J CPU Units
Model CP1L-M40DR-A
CP1L-M40DR-D
CP1L-M40DT-D
CP1L-M40DT1-D
CP1L-M30DR-A
CP1L-M30DR-D
CP1L-M30DT-D
CP1L-M30DT1-D
CP1L-L20DR-A
CP1L-L20DR-D
CP1L-L20DT-D
CP1L-L20DT1-D
CP1L-L14DR-A
CP1L-L14DR-D
CP1L-L14DT-D
CP1L-L14DT1-D
CP1L-J20DR-A
CP1L-J20DR-D
CP1L-J20DT1-D
CP1L-J14DR-A
CP1L-J14DR-D
CP1L-J14DT1-D