617
PLC Setup
Appendix G
2
2-6
PC Link (Slave)
2-6-1
Baud
9,600 bps
(disabled)
38,400 (standard)
Every cycle
161
(CP1L M-
type CPU
Unit)
00 to
07
00 hex
115,200 (high speed)
0A hex
2-6-2
PC Link
Unit No.
0
0
Every cycle
167
(CP1L M-
type CPU
Unit)
00 to
03
0 hex
:
:
7
7 hex
2-7
PC Link (Master)
2-7-1
Baud
9,600 bps
(disabled)
38,400 (standard)
Every cycle
161
(CP1L M-
type CPU
Unit)
00 to
07
00 hex
115,200 (high speed)
0A hex
2-7-2
Link
Words
10 (default)
1
:
10 (default)
Every cycle
166
(CP1L M-
type CPU
Unit)
04 to
07
1 hex
:
0 or A hex
2-7-3
PC Link
Mode
ALL
ALL
Every cycle
166
(CP1L M-
type CPU
Unit)
15
0
Masters
1
Name
Default
Settings
When setting is read
by CPU Unit
Internal
address
Bits
Settings
Summary of Contents for CP1L - 12-2007
Page 3: ...iv...
Page 9: ...x...
Page 13: ...xiv TABLE OF CONTENTS...
Page 21: ...xxii...
Page 33: ...xxxiv Conformance to EC Directives 6...
Page 65: ...32 Function Blocks Section 1 5...
Page 428: ...395 Clock Section 6 9...
Page 429: ...396 Clock Section 6 9...
Page 523: ...488 Troubleshooting Unit Errors Section 9 4...
Page 531: ...496 Replacing User serviceable Parts Section 10 2...
Page 563: ...528 Auxiliary Area Allocations by Function Appendix C...
Page 611: ...576 Auxiliary Area Allocations by Address Appendix D...
Page 638: ...603 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 639: ...604 Connections to Serial Communications Option Boards Appendix F...
Page 669: ...634 Index...
Page 671: ...636 Revision History...