608
PLC Setup
Appendix G
Input Constant Settings
Name
Default
Settings
When setting is read
by CPU Unit
Internal
address
Bits
Settings
1
0CH: CIO 0
8 ms
Default (8ms)
No filter (0 ms)
When power is turned
ON
10
00 to 07
10 hex
0.5 ms
11 hex
1 ms
12 hex
2 ms
13 hex
4 ms
14 hex
8 ms
15 hex
16 ms
16 hex
32 ms
17 hex
2
1 CH: CIO 1
Same as
above.
Same as above.
Same as above.
10
08 to 15
Same as
above.
3
2 CH: CIO 2
11
00 to 07
4
3 CH: CIO 3
11
08 to 15
5
4 CH: CIO 4
12
00 to 07
6
5 CH: CIO 5
12
08 to 15
7
6 CH: CIO 6
13
00 to 07
8
7 CH: CIO 7
13
08 to 15
9
8 CH: CIO 8
14
00 to 07
10
9 CH: CIO 9
14
08 to 15
11
10 CH: CIO 10
15
00 to 07
12
11 CH: CIO 11
15
08 to 15
13
12 CH: CIO 12
16
00 to 07
14
13 CH: CIO 13
16
08 to 15
15
14 CH: CIO 14
17
00 to 07
16
15 CH: CIO 15
17
08 to 15
17
16 CH: CIO 16
18
00 to 07
18
17 CH: CIO 17
18
08 to 15
Summary of Contents for CP1L - 12-2007
Page 3: ...iv...
Page 9: ...x...
Page 13: ...xiv TABLE OF CONTENTS...
Page 21: ...xxii...
Page 33: ...xxxiv Conformance to EC Directives 6...
Page 65: ...32 Function Blocks Section 1 5...
Page 428: ...395 Clock Section 6 9...
Page 429: ...396 Clock Section 6 9...
Page 523: ...488 Troubleshooting Unit Errors Section 9 4...
Page 531: ...496 Replacing User serviceable Parts Section 10 2...
Page 563: ...528 Auxiliary Area Allocations by Function Appendix C...
Page 611: ...576 Auxiliary Area Allocations by Address Appendix D...
Page 638: ...603 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 639: ...604 Connections to Serial Communications Option Boards Appendix F...
Page 669: ...634 Index...
Page 671: ...636 Revision History...