Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 May 29, 2006 page 274 of 698
REJ09B0146-0500
(1st cycle)
(2nd cycle)
Data read cycle
Data write cycle
Transfer source
address
Transfer destination
address
CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
DACKn
Note: Transfer between external memories, DACK output in a read cycle DACK output timing
is the same as that of
CSn
.
Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode
in the Dual Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Summary of Contents for SH7706 Series
Page 8: ...Rev 5 00 May 29 2006 page viii of xlviii ...
Page 160: ...Section 5 Cache Rev 5 00 May 29 2006 page 112 of 698 REJ09B0146 0500 ...
Page 370: ...Section 11 Watchdog Timer WDT Rev 5 00 May 29 2006 page 322 of 698 REJ09B0146 0500 ...
Page 554: ...Section 17 Pin Function Controller PFC Rev 5 00 May 29 2006 page 506 of 698 REJ09B0146 0500 ...
Page 576: ...Section 18 I O Ports Rev 5 00 May 29 2006 page 528 of 698 REJ09B0146 0500 ...
Page 746: ...Index Rev 5 00 May 29 2006 page 698 of 698 REJ09B0146 0500 ...
Page 749: ...SH7706 Group Hardware Manual ...