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Section 8 Bus State Controller (BSC)

Rev. 5.00 May 29, 2006 page 166 of 698
REJ09B0146-0500

Pin Name

Signal

I/O

Description

Data enable 2

WE2

/

DQMUL

/

ICIORD

O

When memory other than synchronous DRAM is
used, selects D23 to D16 write strobe signal.
When synchronous DRAM is used, selects D23 to
D16. When PCMCIA is used, strobe signal
indicating I/O read.

Data enable 3

WE3

/

DQMUU

/

ICIOWR

O

When memory other than synchronous DRAM is
used, selects D31 to D24 write strobe signal.
When synchronous DRAM is used, selects D31 to
D24. When PCMCIA is used, strobe signal
indicating I/O write.

Read

RD

O

Strobe signal indicating read cycle

Wait

WAIT

I

Wait state request signal

Clock enable

CKE

O

Clock enable control signal of synchronous DRAM

IOIS16

IOIS16

I

Signal indicating PCMCIA 16-bit I/O. Valid only in
little-endian mode.

Bus release request

BREQ

I

Bus release request signal

Bus release
acknowledgment

BACK

O

Bus release acknowledge signal

8.3

Area Overview

Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32-
bit address spaces. The logical space is divided into five areas by the value of the upper bits of the
address. The physical space is divided into eight areas.

Logical space can be allocated at physical spaces using a memory management unit (MMU). For
details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for
physical spaces.

As listed in table 8.2, this LSI can be connected directly to six areas of memory/PCMCIA
interface, and it outputs chip select signals (

CS0

,

CS2

to

CS6

,

CE2A

,

CE2B

) for each of them.

CS0

is asserted during area 0 access;

CS6

is asserted during area 6 access. When PCMCIA

interface is selected in area 5 or 6, in addition to

CS5

/

CS6

,

CE2A

/

CE2B

are asserted for the

corresponding bytes accessed.

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Summary of Contents for SH7706 Series

Page 1: ...erH RISC engine Family SH7700 Series SH7706 HD6417706F HD6417706BP Rev 5 00 REJ09B0146 0500 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ...as a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein 5 Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is p...

Page 3: ...re Initialization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction beca...

Page 4: ...ntents 6 Overview 7 Description of Functional Modules CPU and System Control Modules On Chip Peripheral Modules The configuration of the functional description of each module differs according to the module However the generic style includes the following items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this L...

Page 5: ... this manual Product Classifications and Abbreviations Basic Classification Product Code SH7706 176 pin plastic LQFP HD6417706F133 SH7706 208 pin plastic TFBGA HD6417706BP133V In order to understand the overall functions of the chip Read the manual according to the contents This manual can be roughly categorized into parts on the CPU system control functions peripheral functions and electrical cha...

Page 6: ...manual SH 3 SH 3E SH3 DSP Programming Manual ADE 602 096 Users manuals for development tools Document Title Document No SH Series C C Compiler Assembler Optimizing Linkage Editor User s Manual ADE 702 246 SH Series Simulator Debugger for Windows User s Manual ADE 702 186 SH Series Simulator Debugger for UNIX User s Manual ADE 702 203 High performance Embedded Workshop User s Manual ADE 702 201 SH ...

Page 7: ...nterrupt Controller JEIDA Japan Electronic Industry Development Association JTAG Joint Test Action Group LRU Least Recently Used LSB Least Significant Bit MMU Memory Management Unit MSB Most Significant Bit PCMCIA Personal Computer Memory Card International Association PFC Pin Function Controller PLL Phase Locked Loop RISC Reduced Instruction Set Computer ROM Read Only Memory RTC Realtime Clock SC...

Page 8: ...Rev 5 00 May 29 2006 page viii of xlviii ...

Page 9: ...BP 208A Pin Name I O Description 109 K15 AUDATA 0 PTF 0 I O AUD data input output port F 110 K16 AUDATA 1 PTF 1 I O AUD data input port F 111 K17 AUDATA 2 PTF 2 I O AUD data input output port F 3 4 4 Avoiding Synonym Problems Figure 3 9 Synonym Problem 69 Figure amended When using a 4 kbyte page Virtual address 31 VPN 0 12 11 Offset Physical address 31 PPN 0 Offset Virtual address 11 to 4 Physical...

Page 10: ... pin When edge detection mode is set for IRQ5 an interrupt request is cleared by clearing the IRQ5R bit It is not necessary to clear the flag when using level sensing because this bit merely shows the status of the IRQ5 pin 0 An interrupt request is not input to IRQ5 pin 1 An interrupt request is input to IRQ5 pin 4 IRQ4R 0 R W IRQ4 Interrupt Request Indicates whether an interrupt request is input...

Page 11: ...IRQ0 Interrupt Request IRQ0R Indicates whether an interrupt request is input to the IRQ0 pin When edge detection mode is set for IRQ0 an interrupt request is cleared by clearing the IRQ0R bit It is not necessary to clear the flag when using level sensing because this bit merely shows the status of the IRQ0 pin 0 An interrupt request is not input to IRQ0 pin 1 An interrupt request is input to IRQ0 ...

Page 12: ...RAM all bank precharge may not be executed properly in the first cycle of the refresh or bus release cycle In this case precharging of the selected bank is executed instead of all bank precharge 1 The RASD bit in the individual memory control register MCR is set to 1 and 2 long word access is performed to any 16 bit bus width area areas 0 to 6 or word long word access is performed to any 8 bit bus...

Page 13: ...Note Items in parentheses apply to 16 bit bus width connections TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High A15 to A13 or A14 to A12 9 3 2 DMA Destination Address Registers 0 to 3 DAR_0 to DAR_3 255 Description amended To transfer data in 16 bits or in 32 bits specify the address with 16 bit or 32 bit address boundary When transferring data in 16 byte units a 16 byte boundary address 16n must be ...

Page 14: ...ained by dividing the peripheral clock Pφ When the STR0 bit of the CMSTR is set to 1 the CMCNT begins incrementing with the clock selected by CKS1 and CKS0 00 P φ 4 01 P φ 8 10 P φ 16 11 P φ 64 9 5 3 Operation Period Count Operation 295 Description amended When a clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR0 bit of the CMSTR is set to 1 the CMCNT begins increment...

Page 15: ...ock frequency division ratio bits IFC 2 0 in the frequency control register FRQCR are modified Note that no problem occurs if the clock ratio for Iφ Bφ is 1 1 after modification of the bits Furthermore no problem occurs if the frequency multiplication ratio bits STC 2 0 are modified at the same time as IFC 2 0 These problems may be avoided by either of the following measures Do not use the DMAC wh...

Page 16: ...egister 1 RCR1 352 Description and table amended RTC control register 1 RCR1 affects carry flags and alarm flags It also selects whether to generate interrupts for each flag Because flags are sometimes set after an operand read do not use this register in read modify write processing RCR1 is an 8 bit read write register Bits CIE AIE and AF are initialized by a power on reset or manual reset After ...

Page 17: ... SCFCR2 SCPCR SCPDR Parity generation Parity check Ex Transmit receive control 16 stages 16 stages 16 3 6 Serial Control Register 2 SCSCR2 451 Bit table amended Bit Bit Name Initial Value R W Description 1 0 CKE1 CKE0 0 0 R W R W 00 Internal clock SCK pin used for I O pin input signal is ignored 01 Internal clock SCK2 pin used for clock output 1 10 External clock SCK2 pin used for clock input 2 11...

Page 18: ...Register SCPCR 503 Description amended When the TE bit in SCSCR is set to 1 the SCPCR setting is ignored and the TxD function is selected When the RE bit in SCSCR is set to 1 the SCPCR setting is ignored and the RxD function is selected When the TE bit in SCSCR2 is set to 1 the SCPCR setting is ignored and the TxD2 function is selected When the RE bit in SCSCR2 is set to 1 the SCPCR setting is ign...

Page 19: ...l communication interface SCI or timer unit TMU may not be read properly To avoid this problem access read or write any register in the RTC SCI or TMU once or more before setting the RTC to module standby mode 22 3 3 Module Standby Function Transition to Module Standby Function 576 Description added If the realtime clock RTC is set to module standby mode bit 1 in standby control register STBCR set...

Page 20: ...D tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 Note Items in parentheses apply to 16 bit bus width connections 24 3 7 PCMCIA Timing Figure 24 45 PCMCIA I O Bus Cycle TED 2 TEH 1 One Wait External Wait 652 Figure amended D15 to D0 read ICIOWR write D15 to D0 write tICWSD tWDD1 tICWSD tWDH1 tWDH4 tRDS1 24 3 12 Delay Time Variation Due to Load Capacitance Figure 24 63 Load Capacitance vs Delay Time 663 Figure...

Page 21: ...XTAL2 O O O O O Clock CAP1 CAP2 671 Reset Power Down Category Pin Power On Reset Manual Reset Standby Sleep Bus Released Port CE2B PTD 7 H OP 3 ZH 11 K 3 OP 3 ZP 3 CE2A PTD 6 H OP 3 ZH 11 K 3 OP 3 ZP 3 IOIS16 PTD 5 I I Z I I ADTRG PTG 5 V 8 I IZ I I H UDI TCK PTG 1 IV I IZ I I TDI PTG 0 IV I IZ I I TMS PTG 2 IV I IZ I I TRST PTG 3 IV I IZ I I AUDSYNC PTF 4 OV OP 3 OK 3 OP 3 OP 3 TDO PTF 5 OV OP 3 ...

Page 22: ...Table amended Model Marking Package HD6417706F133 176 pin plastic LQFP FP 176C PLQP0176KD A HD6417706BP133 208 pin TFBGA TBP 208A TTBG0208JA A D Package Dimensions Figure D 1 Package Dimensions FP 176C PLQP0176KD A 693 Figure replaced Figure D 2 Package Dimensions TBP 208A TTBG0208JA A 694 Figure replaced ...

Page 23: ...2 Addressing Modes 23 2 3 3 Instruction Formats 27 2 4 Instruction Set 30 2 4 1 Instruction Set Classified by Function 30 2 4 2 Instruction Code Map 46 2 5 Processor States and Processor Modes 49 2 5 1 Processor States 49 2 5 2 Processor Modes 50 Section 3 Memory Management Unit MMU 51 3 1 Role of MMU 51 3 1 1 This LSI s MMU 53 3 2 Register Description 56 3 2 1 Page Table Entry Register High PTEH ...

Page 24: ...ss Array 77 3 6 2 Data Array 77 3 6 3 Usage Examples 79 3 7 Usage Note 79 3 7 1 Use of Instructions Manipulating MD and BL Bits in SR 79 3 7 2 Use of TLB 80 Section 4 Exception Processing 81 4 1 Exception Processing Function 81 4 1 1 Exception Processing Flow 81 4 1 2 Exception Processing Vector Addresses 82 4 1 3 Acceptance of Exceptions 83 4 1 4 Exception Codes 85 4 1 5 Exception Request and BL ...

Page 25: ...y 108 5 4 2 Data Array 109 5 4 3 Usage Examples 111 Section 6 Interrupt Controller INTC 113 6 1 Feature 113 6 2 Input Output Pin 115 6 3 Interrupt Sources 115 6 3 1 NMI Interrupts 115 6 3 2 IRQ Interrupt 116 6 3 3 IRL Interrupts 117 6 3 4 On Chip Peripheral Module Interrupts 118 6 3 5 Interrupt Exception Processing and Priority 119 6 4 Register Description 123 6 4 1 Interrupt Priority Registers A ...

Page 26: ...SR 151 7 2 12 Branch Destination Register BRDR 152 7 2 13 Break ASID Register A BASRA 152 7 2 14 Break ASID Register B BASRB 153 7 3 Operation 153 7 3 1 Flow of the User Break Operation 153 7 3 2 Break on Instruction Fetch Cycle 154 7 3 3 Break by Data Access Cycle 154 7 3 4 Sequential Break 155 7 3 5 Value of Saved Program Counter 155 7 3 6 PC Trace 156 7 3 7 Usage Examples 158 7 4 Usage Note 162...

Page 27: ...put Output Pin 254 9 3 Register Description 254 9 3 1 DMA Source Address Registers 0 to 3 SAR_0 to SAR_3 255 9 3 2 DMA Destination Address Registers 0 to 3 DAR_0 to DAR_3 255 9 3 3 DMA Transfer Count Registers 0 to 3 DMATCR_0 to DMATCR_3 256 9 3 4 DMA Channel Control Registers 0 to 3 CHCR_0 to CHCR_3 256 9 3 5 DMA Operation Register DMAOR 263 9 4 Operation 265 9 4 1 DMA Transfer Flow 265 9 4 2 DMA...

Page 28: ... Counter WTCNT 316 11 2 2 Watchdog Timer Control Status Register WTCSR 316 11 2 3 Notes on Register Access 318 11 3 Operation 319 11 3 1 Canceling Software Standbys 319 11 3 2 Changing the Frequency 320 11 3 3 Using Watchdog Timer Mode 320 11 3 4 Using Interval Timer Mode 321 Section 12 Timer Unit TMU 323 12 1 Feature 323 12 2 Input Output Pin 325 12 3 Register Description 325 12 3 1 Timer Output ...

Page 29: ...er RYRCNT 346 13 3 9 Second Alarm Register RSECAR 347 13 3 10 Minute Alarm Register RMINAR 347 13 3 11 Hour Alarm Register RHRAR 348 13 3 12 Day of the Week Alarm Register RWKAR 349 13 3 13 Date Alarm Register RDAYAR 350 13 3 14 Month Alarm Register RMONAR 351 13 3 15 RTC Control Register 1 RCR1 352 13 3 16 RTC Control Register 2 RCR2 354 13 4 RTC Operation 356 13 4 1 Initial Settings of Registers...

Page 30: ...ynchronous Operation 410 14 5 SCI Interrupt Sources 417 14 6 Usage Note 418 Section 15 Smart Card Interface 421 15 1 Feature 421 15 2 Input Output Pin 423 15 3 Register Description 423 15 3 1 Smart Card Mode Register SCSCMR 424 15 3 2 Serial Status Register SCSSR 425 15 4 Operation 427 15 4 1 Overview 427 15 4 2 Pin Connections 427 15 4 3 Data Format 428 15 4 4 Register Settings 429 15 4 5 Clock 4...

Page 31: ...ACR 489 17 1 2 Port B Control Register PBCR 490 17 1 3 Port C Control Register PCCR 492 17 1 4 Port D Control Register PDCR 493 17 1 5 Port E Control Register PECR 495 17 1 6 Port F Control Register PFCR 497 17 1 7 Port G Control Register PGCR 499 17 1 8 Port H Control Register PHCR 500 17 1 9 Port J Control Register PJCR 502 17 1 10 SC Port Control Register SCPCR 503 Section 18 I O Ports 507 18 1...

Page 32: ...eatures 529 19 2 Input Output Pin 531 19 3 Register Description 531 19 3 1 A D Data Registers A to D ADDRA to ADDRD 532 19 3 2 A D Control Status Register ADCSR 533 19 3 3 A D Control Register ADCR 536 19 4 Bus Master Interface 536 19 5 Access Size of A D Data Register 538 19 5 1 Word Access 538 19 5 2 Longword Access 538 19 6 Operation 539 19 6 1 Single Mode MULTI 0 539 19 6 2 Multi Mode MULTI 1 ...

Page 33: ... Operations 561 21 4 1 TAP Controller 561 21 4 2 Reset Configuration 562 21 4 3 H UDI Reset 563 21 4 4 H UDI Interrupt 563 21 4 5 Bypass 563 21 4 6 Using H UDI to Recover from Sleep Mode 563 21 5 Boundary Scan 564 21 5 1 Supported Instructions 564 21 5 2 Notes for Boundary Scan 565 21 6 Usage Note 565 21 7 Advanced User Debugger AUD 565 Section 22 Power Down Modes 567 22 1 Input Output Pin 569 22 ...

Page 34: ...24 3 6 Synchronous DRAM Timing 630 24 3 7 PCMCIA Timing 647 24 3 8 Peripheral Module Signal Timing 654 24 3 9 H UDI AUD Related Pin Timing 658 24 3 10 A D Converter Timing 660 24 3 11 AC Characteristics Measurement Conditions 662 24 3 12 Delay Time Variation Due to Load Capacitance 663 24 4 A D Converter Characteristics 664 24 5 D A Converter Characteristics 664 Appendix 665 A Equivalent Circuits ...

Page 35: ...ess and TLB Structure 61 Figure 3 5 TLB Indexing IX 1 62 Figure 3 6 TLB Indexing IX 0 63 Figure 3 7 Objects of Address Comparison 64 Figure 3 8 Operation of LDTLB Instruction 67 Figure 3 9 Synonym Problem 69 Figure 3 10 MMU Exception Generation Flowchart 74 Figure 3 11 MMU Exception Signals in Instruction Fetch 75 Figure 3 12 MMU Exception Signals in Data Access 76 Figure 3 13 Specifying Address a...

Page 36: ...ng Wait State Insertion by WAIT Signal WAITSEL 1 210 Figure 8 11 Example of 64 Mbit Synchronous DRAM Connection 32 Bit Bus Width 212 Figure 8 12 Example of 64 Mbit Synchronous DRAM 16 Bit Bus Width 213 Figure 8 13 Basic Timing for Synchronous DRAM Burst Read 216 Figure 8 14 Synchronous DRAM Burst Read Wait Specification Timing 217 Figure 8 15 Basic Timing for Synchronous DRAM Single Read 218 Figur...

Page 37: ...e 9 6 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode Transfer Source Ordinary Memory Transfer Destination Ordinary Memory 274 Figure 9 7 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode 16 Byte Transfer Transfer Source Ordinary Memory Transfer Destination Ordinary Memory 275 Figure 9 8 Example of DMA Transfer Timing in the Direc...

Page 38: ...0 Clock Pulse Generator CPG Figure 10 1 Block Diagram of Clock Pulse Generator 304 Figure 10 2 Points for Attention when Using Crystal Oscillator 313 Figure 10 3 Points for Attention when Using PLL Oscillator Circuit 314 Section 11 Watchdog Timer WDT Figure 11 1 Block Diagram of the WDT 315 Figure 11 2 Writing to WTCNT and WTCSR 319 Section 12 Timer Unit TMU Figure 12 1 TMU Block Diagram 324 Figur...

Page 39: ...ta 404 Figure 14 14 SCI Multiprocessor Transmit Operation 406 Figure 14 15 Sample Flowchart for Receiving Multiprocessor Serial Data 407 Figure 14 16 Example of SCI Receive Operation 409 Figure 14 17 Data Format in Clock Synchronous Communication 410 Figure 14 18 Sample Flowchart for SCI Initialization 411 Figure 14 19 Sample Flowchart for Serial Transmitting 412 Figure 14 20 Example of SCI Transm...

Page 40: ...with 8 Bit Data Parity One Stop Bit 479 Figure 16 12 Example of Operation Using Modem Control RTS2 479 Figure 16 13 Receive Data Sampling Timing in Asynchronous Mode 482 Section 18 I O Ports Figure 18 1 Port A 507 Figure 18 2 Port B 509 Figure 18 3 Port C 511 Figure 18 4 Port D 513 Figure 18 5 Port E 515 Figure 18 6 Port F 517 Figure 18 7 Port G 519 Figure 18 8 Port H 521 Figure 18 9 Port J 523 Fi...

Page 41: ...andby to Power On Reset STATUS Output 579 Figure 22 6 Software Standby to Manual Reset STATUS Output 580 Figure 22 7 Sleep to Interrupt STATUS Output 580 Figure 22 8 Sleep to Power On Reset STATUS Output 581 Figure 22 9 Sleep to Manual Reset STATUS Output 581 Figure 22 10 Hardware Standby Mode When CA Goes Low in Normal Operation 583 Figure 22 11 Hardware Standby Mode Timing When CA Goes Low durin...

Page 42: ...CAS Latency 1 TPC 1 632 Figure 24 25 Synchronous DRAM Read Bus Cycle Burst Read Single Read 4 RCD 1 CAS Latency 3 TPC 0 633 Figure 24 26 Synchronous DRAM Write Bus Cycle RCD 0 TPC 0 TRWL 0 634 Figure 24 27 Synchronous DRAM Write Bus Cycle RCD 2 TPC 1 TRWL 1 635 Figure 24 28 Synchronous DRAM Write Bus Cycle Burst Mode Single Write 4 RCD 0 TPC 1 TRWL 0 636 Figure 24 29 Synchronous DRAM Write Bus Cyc...

Page 43: ...6 PCMCIA I O Bus Cycle TED 1 TEH 1 One Wait Bus Sizing 653 Figure 24 47 TCLK Input Timing 655 Figure 24 48 TCLK Clock Input Timing 655 Figure 24 49 Oscillation Settling Time at RTC Crystal Oscillator Power on 655 Figure 24 50 SCK Input Clock Timing 655 Figure 24 51 SCI I O Timing in Clock Synchronous Mode 656 Figure 24 52 I O Port Timing 656 Figure 24 53 DREQ Input Timing 657 Figure 24 54 DRAK Out...

Page 44: ...Table 4 2 Exception Codes 85 Table 4 3 Types of Reset 92 Section 5 Cache Table 5 1 LRU and Way Replacement 100 Table 5 2 Way to be Replaced when Cache Miss Occurs during PREF Instruction Execution 103 Table 5 3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction Other than PREF Instruction 104 Table 5 4 LRU and Way Replacement When W2LOCK 1 104 Table 5 5 LRU and Way Replaceme...

Page 45: ...cess and Data Alignment 200 Table 8 15 16 Bit External Device Little Endian Access and Data Alignment 200 Table 8 16 8 Bit External Device Little Endian Access and Data Alignment 201 Table 8 17 Relationship between Bus Width AMX and Address Multiplex Output 214 Table 8 18 Example of Correspondence between this LSI and Synchronous DRAM Address Pins AMX 3 to 0 0100 32 Bit Bus Width 215 Section 9 Dir...

Page 46: ...ode 389 Table 14 8 Serial Mode Register Settings and SCI Communication Formats 391 Table 14 9 SCSMR and SCSCR Settings and SCI Clock Source Selection 391 Table 14 10 Serial Communication Formats Asynchronous Mode 393 Table 14 11 Receive Error Conditions and SCI Operation 401 Table 14 12 SCI Interrupt Sources 417 Table 14 13 SCSSR Status Flags and Transfer of Receive Data 418 Section 15 Smart Card ...

Page 47: ...Table 18 5 Read Write Operation of the Port E Data Register PEDR 516 Table 18 6 Read Write Operation of the Port F Data Register PFDR 518 Table 18 7 Read Write Operation of the Port G Data Register PGDR 520 Table 18 8 Read Write Operation of the Port H Data Register PHDR 522 Table 18 9 Read Write Operation of the Port J Data Register PJDR 524 Table 18 10 Read Write Operation of the SC Port Data Re...

Page 48: ... AUD Related Pin Timing 658 Table 24 10 A D Converter Timing 660 Table 24 11 A D Converter Characteristics 664 Table 24 12 D A Converter Characteristics 664 Appendix Table B 1 Pin States during Resets Power Down States and Bus Released State 669 Table B 2 Pin Specifications 673 Table B 3 Pin States Normal Memory Little Endian 678 Table B 4 Pin States Normal Memory Big Endian 680 Table B 5 Pin Stat...

Page 49: ...ime clock that enable system configuration at low cost A built in power management function enables dynamic control of power consumption Thus this LSI is optimum for portable electronic devices such as PDAs that require both high performance and low power The SH7706 incorporates a user debugging interface H UDI and an advanced user debugger AUD to support emulator functions such as E10A This LSI a...

Page 50: ...tions Memory Management Unit MMU User Break Controller UBC Bus state Controller BSC Direct Memory Access Controller DMAC Clock Pulse Generator CPG Watchdog Timer WDT Timer Unit TMU Realtime Clock RTC Serial Communication Interface SCI Smartcard Interface Serial Communication Interface with FIFO SCIF 10 bit A D converter ADC 8 bit D A converter DAC User Debugging Interface H UDI Advanced User Debug...

Page 51: ...anced user debugger Bus state controller Cache memory Cache memory controller Compare match timer Clock pulse generator watchdog timer Central processing unit D A converter DMAC H UDI INTC MMU RTC SCI SCIF TLB TMU UBC Direct memory access controller User debugging interface Interrupt controller Memory management unit Realtime clock Serial communication interface with smart card interface Serial co...

Page 52: ...U PTD 3 CASL PTD 2 RASU PTD 1 RASL PTD 0 V CC Q CE2B PTD 7 V SS Q CE2A PTD 6 CS6 CE1B PTC 7 CS5 CE1A PTC 6 CS4 PTC 5 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53...

Page 53: ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U A B C D E F G H J K L M N P R T U SH7706 TBP 208A Top view INDEX MARK Note Section in the dotted lines are perspective view Figure 1 3 Pin Assignment TBP 208A ...

Page 54: ... 11 G2 VSS Q Input output power supply 0 V 12 G1 D25 PTB 1 I O Data bus input output port B 13 H4 VCC Q Input output power supply 3 3 V 14 H3 D24 PTB 0 I O Data bus input output port B 15 H2 D23 PTA 7 I O Data bus input output port A 16 H1 D22 PTA 6 I O Data bus input output port A 17 J4 D21 PTA 5 I O Data bus input output port A 18 J2 D20 PTA 4 I O Data bus input output port A 19 J1 VSS Internal ...

Page 55: ...bus 39 P3 VCC Q Input output power supply 3 3 V 40 R1 D4 I O Data bus 41 R2 D3 I O Data bus 42 P4 D2 I O Data bus 43 T1 D1 I O Data bus 44 T2 D0 I O Data bus 45 U1 A0 O Address bus 46 U2 A1 O Address bus 47 R3 A2 O Address bus 48 T3 A3 O Address bus 49 U3 VSS Q Input output power supply 0 V 50 R4 A4 O Address bus 51 T4 VCC Q Input output power supply 3 3 V 52 U4 A5 O Address bus 53 P5 A6 O Address...

Page 56: ...ernal power supply 0 V 72 R9 A22 O Address bus 73 U10 VCC Internal power supply 1 9 V 74 T10 A23 O Address bus 75 P10 A24 O Address bus 76 T11 A25 O Address bus 77 R11 BS PTC 0 O I O Bus cycle start signal input output port C 78 P11 RD O Read strobe 79 U12 WE0 DQMLL O D7 to D0 select signal DQM SDRAM 80 T12 WE1 DQMLU WE O D15 to D8 select signal DQM SDRAM write strobe PCMCIA 81 R12 WE2 DQMUL ICIOR...

Page 57: ... input output port D 93 R17 VSS Q Input output power supply 0 V 94 P15 CE2B PTD 7 O I O Area 6 PCMCIA CE2 input output port D 95 P16 VCC Q Input output power supply 3 3 V 96 P17 RASL PTD 0 O I O Lower 32 Mbytes address RAS SDRAM input output port D 97 N14 RASU PTD 1 O I O Upper 32 Mbytes address RAS SDRAM input output port D 98 N15 CASL PTD 2 O I O Lower 32 Mbytes address CAS SDRAM input output po...

Page 58: ... J15 VSS Internal power supply 0 V 116 H17 TCK PTG 1 I Clock H UDI input port G 117 H16 VCC Internal power supply 1 9 V 118 G16 TMS PTG 2 I Mode select H UDI input port G 119 G15 TRST PTG 3 I Reset H UDI input port G 120 G14 TDO PTF 5 O I O Data output H UDI input output port F 121 F16 ASEBRKAK PTF 6 O I O ASE break acknowledge H UDI input output port F 122 F15 ASEMD0 3 I ASE mode H UDI 123 E17 VC...

Page 59: ...CIF transmit data 2 SC port 143 B13 SCK2 SCPT 3 I O SCIF clock 2 SC port 144 A13 RTS2 SCPT 4 O I O SCIF transmit request 2 SC port 145 D12 RxD0 SCPT 0 I SCI receive data 0 SC port 146 C12 RxD2 SCPT 2 I SCIF receive data 2 SC port 147 B12 CTS2 IRQ5 SCPT 5 I SCIF transmit clear external interruption request SC port 148 D11 VSS Internal power supply 0 V 149 C11 RESETM I Manual reset request 150 B11 V...

Page 60: ...nput D A converter output input port J 174 B4 AN 3 DA 0 PTJ 3 I O I A D converter input D A converter output input port J 175 B3 AVCC Analog power supply 3 3 V 176 B2 AVSS Analog power supply 0 V Notes Except in hardware standby mode all VCC VSS pins must be connected to the system power supply Supply power constantly In hardware standby mode power must be supplied at least to VCC RTC and VSS RTC ...

Page 61: ...s the general register set with BANK0 general registers R0_BANK0 to R7_BANK0 accessed only by the LDC STC instructions When the RB bit is 0 BANK0 general registers R0_BANK0 to R7_BANK0 and nonbanked general registers R8 to R15 function as the general register set with BANK1 general registers R0_BANK1 to R7_BANK1 accessed only by the LDC STC instructions In user mode the 16 registers comprising ban...

Page 62: ...NK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 GBR MACH MACL VBR PR SR SSR PC SPC a User mode register configuration Notes 1 2 3 4 b Privileged mode register configuration RB 1 c Privileged mode register configuration RB 0 R0 functions as an index register in the indexed register indirect addressin...

Page 63: ...nked registers with a different R0 to R7 register bank R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1 being accessed according to the processor mode For details see figure 2 1 The general register configuration is shown in figure 2 2 31 0 R0 1 2 General Registers R1 2 R2 2 R3 2 R4 2 R5 2 R6 2 R7 2 R8 R9 R10 R11 R12 R13 R14 R15 Notes 1 R0 functions as an index register in the indexed register indirec...

Page 64: ...tem register configuration is shown in figure 2 3 31 0 31 0 31 0 Multiply and Accumulate Register MAC Procedure Register PR Program Counter PC PR PC MACH MACL Figure 2 3 System Registers 1 Multiply and Accumulate Register MAC Multiply and Accumulate register is consist of Higher part register MACH and Lower part register MACL Store the results of multiply and accumulate operations Initialized to u...

Page 65: ...r mode There are five control registers as follows Status register SR Saved status register SSR Saved program counter SPC Global base register GBR Vector base register VBR The control register configuration is shown in figure 2 4 SSR Saved Status Register SSR Saved Program Counter SPC Global Base Register GBR Vector Base Register VBR 31 0 SPC 31 0 GBR 31 0 VBR 31 0 Status Register SR SR 31 0 Figur...

Page 66: ...n privileged mode 1 R0_BANK1 to R7_BANK1 and R8 to R15 are general registers and R0_BANK0 to R7_BANK0 can be accessed by LDC STC instructions 0 R0_BANK0 to R7_BANK0 and R8 to R15 are general registers and R0_BANK1 to R7_BANK1 can be accessed by LDC STC instructions RB is set to 1 when an exception or interruption is occurred 28 BL 1 R W Block bit 0 Exceptions and interrupts are accepted 1 Exceptio...

Page 67: ...ction 0 T R W T bit Used by the MOVT CMP cond TAS TST BT BF SETT CLRT and DT instructions to indicate true 1 or false 0 Used by the ADDV C SUBV C DIV0U S DIV1 NEGC SHAR L SHLR L ROTR L and ROTCR L instructions to indicate a carry borrow overflow or underflow Note The M Q S and T bits can be set or cleared by special instructions in user mode Their values are undefined after a reset All other bits ...

Page 68: ...and longwords Memory can be accessed in 8 bit byte 16 bit word or 32 bit longword form A memory operand less than 32 bits in length is sign extended before being stored in a register A word operand must be accessed starting from a word boundary even address of a 2 byte unit address 2n and a longword operand starting from a longword boundary even address of a 4 byte unit address 4n An address error...

Page 69: ...an be accessed in 8 bit byte 16 bit word or 32 bit longword units with byte or word units sign extended into 32 bit longwords Literals are sign extended in arithmetic operations MOV ADD and CMP EQ instructions and zero extended in logical operations TST AND OR and XOR instructions Load Store Architecture The load store architecture is used so basic operations are executed by the registers Operatio...

Page 70: ...in a table in main memory rather than inserted directly into the instruction code The memory table is accessed by the MOV instruction using PC relative addressing with displacement as follows MOV W disp PC R0 Absolute Addresses As with word and longword literals absolute addresses must also be stored in a table in main memory The value of the absolute address is transferred to a register and the o...

Page 71: ...s is register Rn contents Rn Rn Rn Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand Rn Rn 1 2 4 Rn 1 2 4 Rn After instruction execution Byte Rn 1 Rn Word Rn 2 Rn Longword Rn 4 Rn Register indirect with pre decrement Rn Effective address is regis...

Page 72: ...ro extended Rn disp 1 2 4 Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 GBR indirect with displacement disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the operand ...

Page 73: ...perand size With a longword operand the lower 2 bits of PC are masked PC H FFFFFFFC 2 4 x for longword disp zero extended PC disp 2 or PC H FFFFFFFC disp 4 Word PC disp 2 Longword PC H FFFF FFFC disp 4 disp 8 Effective address is register PC contents with 8 bit displacement disp added after being sign extended and multiplied by 2 PC 2 disp sign extended PC disp 2 PC disp 2 PC relative disp 12 Effe...

Page 74: ... is sign extended Immediate imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operand size This is done to clarify the operation of the LSI Refer to the relevant assembler notation rule...

Page 75: ... Formats Instruction Format Source Operand Destination Operand Instruction Example 0 format xxxx xxxx xxxx xxxx 15 0 NOP nnnn register direct MOVT Rn Control register or system register nnnn register direct STS MACH Rn n format xxxx xxxx xxxx nnnn 15 0 Control register or system register nnnn register indirect with pre decrement STC L SR Rn m format xxxx mmmm xxxx xxxx 15 0 mmmm register direct Co...

Page 76: ...post increment multiply and accumulate operation MACH MACL MAC W Rm Rn mmmm register indirect with post increment nnnn register direct MOV L Rm Rn mmmm register direct nnnn register indirect with pre decrement MOV L Rm Rn nm format nnnn xxxx xxxx 15 0 mmmm mmmm register direct nnnn indexed register indirect MOV L Rm R0 Rn md format xxxx dddd 15 0 mmmm xxxx mmmmdddd register indirect with displacem...

Page 77: ...0 disp GBR dddddddd PC relative with displacement R0 register direct MOVA disp PC R0 d format dddd xxxx 15 0 xxxx dddd dddddddd PC relative BF label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd PC relative BRA label label disp PC nd8 format dddd nnnn xxxx 15 0 dddd dddddddd PC relative with displacement nnnn register direct MOV L disp PC Rn iiiiiiii immediate Indexed GBR indirect AND B imm R0 ...

Page 78: ...ansfer SWAP Swap of upper and lower bytes Data transfer 5 XTRCT Extraction of middle of linked registers 39 21 ADD Binary addition Arithmetic operations ADDC Binary addition with carry ADDV Binary addition with overflow check CMP cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double precision multiplication DMULU Unsigne...

Page 79: ...nary subtraction with underflow check 33 AND Logical AND NOT Bit inversion OR Logical OR TAS Memory test and bit set TST Logical AND and T bit set Logic operations 6 XOR Exclusive OR 14 Shift 12 ROTL One bit left rotation ROTR One bit right rotation ROTCL One bit left rotation with T bit ROTCR One bit right rotation with T bit SHAL One bit arithmetic left shift SHAR One bit arithmetic right shift ...

Page 80: ...to subroutine procedure Branch 9 RTS Return from subroutine procedure 11 CLRMAC MAC register clear CLRT Clear T bit CLRS Clear S bit LDC Load to control register LDS Load to system register LDTLB Load PTE to TLB NOP No operation PREF Prefetch data to cache RTE Return from exception handling SETS Set S bit SETT Set T bit SLEEP Shift to power down mode STC Store from control register STS Store from ...

Page 81: ...ical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n bit shift Privileged mode Indicates whether privileged mode applies Execution cycles Value when no wait states are inserted The execution cycles listed in the table are minimums The actual number of cycles may be increased in cases such as the followings 1 When contention occurs between instruction fetch...

Page 82: ...mmm0000 1 MOV W Rm Rn Rm Sign extension Rn 0110nnnnmmmm0001 1 MOV L Rm Rn Rm Rn 0110nnnnmmmm0010 1 MOV B Rm Rn Rn 1 Rn Rm Rn 0010nnnnmmmm0100 1 MOV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 1 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 1 MOV B Rm Rn Rm Sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 1 MOV W Rm Rn Rm Sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 1 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 1 M...

Page 83: ...BR R0 disp GBR 11000000dddddddd 1 MOV W R0 disp GBR R0 disp 2 GBR 11000001dddddddd 1 MOV L R0 disp GBR R0 disp 4 GBR 11000010dddddddd 1 MOV B disp GBR R0 disp GBR Sign extension R0 11000100dddddddd 1 MOV W disp GBR R0 disp 2 GBR Sign extension R0 11000101dddddddd 1 MOV L disp GBR R0 disp 4 GBR R0 11000110dddddddd 1 MOVA disp PC R0 disp 4 PC R0 11000111dddddddd 1 MOVT Rn T Rn 0000nnnn00101001 1 SWA...

Page 84: ...MP HS Rm Rn If Rn Rm with unsigned data 1 T 0011nnnnmmmm0010 1 Comparison result CMP GE Rm Rn If Rn Rm with signed data 1 T 0011nnnnmmmm0011 1 Comparison result CMP HI Rm Rn If Rn Rm with unsigned data 1 T 0011nnnnmmmm0110 1 Comparison result CMP GT Rm Rn If Rn Rm with signed data 1 T 0011nnnnmmmm0111 1 Comparison result CMP PZ Rn If Rn 0 1 T 0100nnnn00010001 1 Comparison result CMP PL Rn If Rn 0 ...

Page 85: ...d Rn 0110nnnnmmmm1111 1 EXTU B Rm Rn A byte in Rm is zero extended Rn 0110nnnnmmmm1100 1 EXTU W Rm Rn A word in Rm is zero extended Rn 0110nnnnmmmm1101 1 MAC L Rm Rn Signed operation of Rn Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 2 to 5 MAC W Rm Rn Signed operation of Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 2 to 5 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 000...

Page 86: ...Rm Rn Rn Rm Rn 0011nnnnmmmm1000 1 SUBC Rm Rn Rn Rm T Rn Borrow T 0011nnnnmmmm1010 1 Borrow SUBV Rm Rn Rn Rm Rn Underflow T 0011nnnnmmmm1011 1 Underflow Note The normal number of execution cycles is shown The value in parentheses is the number of cycles required in case of contention with the preceding or following instruction ...

Page 87: ...11iiiiiiii 1 OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii 3 TAS B Rn If Rn is 0 1 T 1 MSB of Rn 0100nnnn00011011 4 Test result TST Rm Rn Rn Rm if the result is 0 1 T 0010nnnnmmmm1000 1 Test result TST imm R0 R0 imm if the result is 0 1 T 11001000iiiiiiii 1 Test result TST B imm R0 GBR R0 GBR imm if the result is 0 1 T 11001100iiiiiiii 3 Test result XOR Rm Rn Rn Rm Rn 0010nnnnmmmm1010 1 XOR i...

Page 88: ...n T 0100nnnn00100101 1 LSB SHAD Rm Rn Rn 0 Rn Rm Rn Rn 0 Rn Rm MSB Rn 0100nnnnmmmm1100 1 SHAL Rn T Rn 0 0100nnnn00100000 1 MSB SHAR Rn MSB Rn T 0100nnnn00100001 1 LSB SHLD Rm Rn Rn 0 Rn Rm Rn Rn 0 Rn Rm 0 Rn 0100nnnnmmmm1101 1 SHLL Rn T Rn 0 0100nnnn00000000 1 MSB SHLR Rn 0 Rn T 0100nnnn00000001 1 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 1 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 1 SHLL8 Rn Rn 8 Rn 0100nnnn...

Page 89: ... 1 BT label Delayed branch if T 1 disp 2 PC PC if T 0 nop 10001001dddddddd 3 1 BT S label If T 1 disp 2 PC PC if T 0 nop 10001101dddddddd 2 1 BRA label Delayed branch disp 2 PC PC 1010dddddddddddd 2 BRAF Rm Delayed branch Rm PC PC 0000mmmm00100011 2 BSR label Delayed branch PC PR disp 2 PC PC 1011dddddddddddd 2 BSRF Rm Delayed branch PC PR Rm PC PC 0000mmmm00000011 2 JMP Rm Delayed branch Rm PC 01...

Page 90: ...m R1_BANK 0100mmmm10011110 3 LDC Rm R2_BANK Rm R2_BANK 0100mmmm10101110 3 LDC Rm R3_BANK Rm R3_BANK 0100mmmm10111110 3 LDC Rm R4_BANK Rm R4_BANK 0100mmmm11001110 3 LDC Rm R5_BANK Rm R5_BANK 0100mmmm11011110 3 LDC Rm R6_BANK Rm R6_BANK 0100mmmm11101110 3 LDC Rm R7_BANK Rm R7_BANK 0100mmmm11111110 3 LDC L Rm SR Rm SR Rm 4 Rm 0100mmmm00000111 7 LSB LDC L Rm GBR Rm GBR Rm 4 Rm 0100mmmm00010111 5 LDC L...

Page 91: ...DS L Rm MACL Rm MACL Rm 4 Rm 0100mmmm00010110 1 LDS L Rm PR Rm PR Rm 4 Rm 0100mmmm00100110 1 LDTLB PTEH PTEL TLB 0000000000111000 1 NOP No operation 0000000000001001 1 PREF Rm Rm cache 0000mmmm10000011 2 RTE Delayed branch SSR SPC SR PC 0000000000101011 4 SETS 1 S 0000000001011000 1 SETT 1 T 0000000000011000 1 1 SLEEP Sleep 0000000000011011 4 STC SR Rn SR Rn 0000nnnn00000010 1 STC GBR Rn GBR Rn 00...

Page 92: ... R0_BANK Rn Rn 4 Rn R0_BANK Rn 0100nnnn10000011 2 STC L R1_BANK Rn Rn 4 Rn R1_BANK Rn 0100nnnn10010011 2 STC L R2_BANK Rn Rn 4 Rn R2_BANK Rn 0100nnnn10100011 2 STC L R3_BANK Rn Rn 4 Rn R3_BANK Rn 0100nnnn10110011 2 STC L R4_BANK Rn Rn 4 Rn R4_BANK Rn 0100nnnn11000011 2 STC L R5_BANK Rn Rn 4 Rn R5_BANK Rn 0100nnnn11010011 2 STC L R6_BANK Rn Rn 4 Rn R6_BANK Rn 0100nnnn11100011 2 STC L R7_BANK Rn Rn ...

Page 93: ...ter instruction is also used by the next instruction With the addressing modes using displacement disp listed below the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed This is done to clarify the operation of the chip For the actual assembler descriptions refer to the individual assembler notation rules disp 4 Rn Register indirect with displacement disp 8 ...

Page 94: ...0 Rn MUL L Rm Rn 0000 0000 00MD 1000 CLRT SETT CLRMAC LDTLB 0000 0000 01MD 1000 CLRS SETS 0000 0000 Fx 1001 NOP DIV0U 0000 0000 Fx 1010 0000 0000 Fx 1011 RTS SLEEP RTE 0000 Rn Fx 1000 0000 Rn Fx 1001 MOVT Rn 0000 Rn Fx 1010 STS MACH Rn STS MACL Rn STS PR Rn 0000 Rn Fx 1011 0000 Rn Rm 11MD MOV B R0 Rm Rn MOV W R0 Rm Rn MOV L R0 Rm Rn MAC L Rm Rn 0001 Rn Rm disp MOV L Rm disp 4 Rn 0010 Rn Rm 00MD MO...

Page 95: ...L Rm SR LDC L Rm GBR LDC L Rm VBR LDC L Rm SSR 0100 Rm 01MD 0111 LDC L Rm SPC 0100 Rm 10MD 0111 LDC L Rm R0_BANK LDC L Rm R1_BANK LDC L Rm R2_BANK LDC L Rm R3_B ANK 0100 Rm 11MD 0111 LDC L Rm R4_BANK LDC L Rm R5_BANK LDC L Rm R6_BANK LDC L Rm R7_B ANK 0100 Rn Fx 1000 SHLL2 Rn SHLL8 Rn SHLL16 Rn 0100 Rn Fx 1001 SHLR2 Rn SHLR8 Rn SHLR16 Rn 0100 Rm Fx 1010 LDS Rm MACH LDS Rm MACL LDS Rm PR 0100 Rm Rn...

Page 96: ... imm disp CMP EQ imm 8 R0 BT label 8 BF label 8 1000 11MD imm disp BT S label 8 BF S label 8 1001 Rn disp MOV W DISP 8 PC RN 1010 disp BRA label 12 1011 disp BSR label 12 1100 00MD imm disp MOV B R0 disp 8 GBR MOV W R0 disp 8 GBR MOV L R0 disp 8 GBR TRAPA imm 8 1100 01MD disp MOV B disp 8 GBR R0 MOV W disp 8 GBR R0 MOV L disp 8 GBR R0 MOVA disp 8 PC R0 1100 10MD imm TST imm 8 R0 AND imm 8 R0 XOR i...

Page 97: ...ception handling In the case of a reset the CPU branches to address H A0000000 and starts executing the user coded exception handling program In the case of a general exception or interrupt the program counter PC contents are saved in the saved program counter SPC and the status register SR contents are saved in the saved status register SSR The CPU branches to the start address of the user coded ...

Page 98: ...ption transition processing Bus request Bus request clearance SLEEP instruction with STBY bit set Interrupt Reset state Power down state SLEEP instruction with STBY bit cleared Bus request Bus request clearance Figure 2 6 Processor State Transitions 2 5 2 Processor Modes There are two processor modes privileged mode and user mode The processor mode is determined by the processor mode bit MD in the...

Page 99: ...al memory is provided and the process is mapped onto this virtual memory Thus a process only has to consider operation in virtual memory Mapping from virtual memory to physical memory is handled by the MMU The MMU is normally controlled by the operating system switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion Switching...

Page 100: ...translation information is normally performed by software This makes it possible for memory management to be performed flexibly by software The MMU has two methods of mapping from virtual memory to physical memory a paging method using fixed length address translation and a segment method using variable length address translation With the paging method the unit of translation is a fixed size addre...

Page 101: ...e so the TLB is not used and no exceptions like TLB misses occur Initialization of MMU related registers exception processing and the like are located in the P1 and P2 areas Because the P1 area is cached handlers that require high speed processing are placed there A part of the control register in the peripheral module is allocated in P2 area The P4 area is used for mapping on chip control registe...

Page 102: ...ce cacheable write back write through CPU Address error H 00000000 H 00000000 H 80000000 H FFFFFFFF Area P0 Area P1 Area P2 Area P3 Area P4 Area U0 Privileged mode User mode 0 5 Gbyte fixed physical space cacheable write back write through 0 5 Gbyte fixed physical space non cacheable 0 5 Gbyte virtual space cacheable write back write through 0 5 Gbyte control space non cacheable Figure 3 2 Virtual...

Page 103: ... executed When the MMU is enabled address translation information that results in a physical address space of H 80000000 to H FFFFFFFF should not be registered in the TLB When the MMU is disabled the virtual address is used directly as the physical address As this LSI supports a 29 bit address space as the physical address space the top 3 bits of the physical address are ignored and constitute a s...

Page 104: ... the TLB does not have to be purged In single virtual memory mode the ASID is used to provide memory protection for processes running simulataneously and using the virtual address space exclusively 3 2 Register Description There are five registers for MMU processing These are located in address space area P4 and can only be accessed from privileged mode by specifying the address These registers fo...

Page 105: ...rently executing process The VPN and ASID are recorded in the TLB by the LDTLB instruction Bit Bit Name Initial Value R W Description 31 to 10 VPN R W Virtual page number 9 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 to 0 ASID R W Address space identifier 3 2 2 Page Table Entry Register Low PTEL The page table entry register low register PTEL is used to ...

Page 106: ...tware command TTB is available to use by software for general purposes 3 2 4 The TLB Exception Address Register TEA The TLB exception address register TEA is a 32 bit register TEA is used to store the virtual address corresponding to a MMU or CPU address error exception after these exceptions has occurred This value remains valid until the next exception or interrupt occurs 3 2 5 MMU Control Regis...

Page 107: ...ding to the virtual address at which the exception occurred are checked and if all ways are valid 1 is added to RO if there is one or more invalid ways they are set by priority from way 0 in the order way 0 way 1 way 2 way 3 In the event of an MMU exception other than a TLB miss exception the way which caused the exception is set in RC 3 0 R Reserved This bit is always read as 0 The write value sh...

Page 108: ...virtual page number and the control information for the page which is the unit of address translation Figure 3 3 shows the overall TLB configuration The TLB is 4 way set associative with 128 entries There are 32 entries for each way Figure 3 4 shows the configuration of virtual addresses and TLB entries Entry 1 Address array Data array Entry 0 Entry 1 Entry 31 Ways 0 to 3 Ways 0 to 3 VPN 11 10 VPN...

Page 109: ... processes 1 Page shared between processes SZ Page size bit 0 1 kbyte page 1 4 kbyte page V Valid bit Indicates whether entry is valid 0 Invalid 1 Valid Cleared to 0 by a power on reset Not affected by a manual reset PPN Physical page number Top 22 bits of physical address PPN bits 11 10 are not used in case of a 4 kbyte page Attention must be paid to the synonym problem in case of a 1 kbyte page ...

Page 110: ... are used as the index number 2 When IX 1 VPN bits 16 to 12 are EX ORed with ASID bits 4 to 0 to generate a 5 bit index number The second method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space multiple virtual memory and a specific entry is selected by indexing of each process Figures 3 5 and 3 6 show the indexing ...

Page 111: ...an one way as hardware operation is not guaranteed if this occurs For example if there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID H FF when one is in the shared state SH 1 and the other in the non shared state SH 0 then if the ASID in PTEH is set to H FF there is a possibility of simultaneous TLB hits in both these ...

Page 112: ...Ds are not compared when single virtual memory is supported and privileged mode is engaged The objects of address comparison are shown in figure 3 7 Bits compared VPN 31 to 17 VPN 11 10 SZ 0 Yes No Yes 1 kbyte No 4 kbytes Bits compared VPN 31 to 17 Bits compared VPN 31 to 17 VPN 11 10 ASID 7 to 0 SZ 0 Yes 1 kbyte No 4 kbytes Bits compared VPN 31 to 17 ASID 7 to 0 SH 1 or SR MD 1 and MMUCR SV 1 Fig...

Page 113: ...area of memory The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory Attempts at nonpermitted accesses result in TLB protection violation exceptions Access states designated by the D C and PR bits are shown in table 3 1 Table 3 1 Access States Designated by D C and PR Bits Privileged Mode User Mode Reading Writing Reading Writing 0 Permitt...

Page 114: ...ince MMU exceptions are not generated in the MMU disabled state with the AT bit cleared to 0 use in the disabled state must be avoided with software that does not use the MMU 2 TLB entry recording deletion and reading TLB entry recording can be done in two ways by using the LDTLB instruction or by writing directly to the memory mapped TLB For TLB entry deletion and reading the memory allocation TL...

Page 115: ...bed in section 3 2 5 MMU Control Register MMUCR Consequently if the LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine TLB entry recording is possible Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR As the LDTLB instruction changes address translation information there is a risk of destroying address translation informati...

Page 116: ...te page is used also a cache index number is created using virtual address bits 11 to 4 However in case of a 1 kbyte page virtual address bits 11 10 are subject to address translation and therefore may not be the same as physical address bits 11 and 10 Consequently the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache add...

Page 117: ...s 31 VPN 0 12 11 Offset Physical address 31 PPN 0 Offset Virtual address 11 to 4 Physical address 31 to 10 Cache address array When using a 1 kbyte page Virtual address 31 VPN 0 10 Offset Physical address 31 PPN 0 10 Offset Virtual address 11 to 4 Physical address 31 to 10 Cache address array 9 9 12 11 Figure 3 9 Synonym Problem ...

Page 118: ... H 060 for a store access is written to the EXPEVT register 4 The PC value indicating the address of the instruction in which the exception occurred is written to the save program counter SPC If the exception occurred in a delay slot the PC value indicating the address of the related delayed branch instruction is written to the SPC 5 The contents of the status register SR at the time of the except...

Page 119: ...o match but the type of access is not permitted by the access rights specified in the PR field TLB protection violation exception processing includes both hardware and software operations Hardware Operations In a TLB protection violation exception this LSI s hardware executes a set of prescribed operations as follows 1 The VPN field of the virtual address causing the exception is written to the PT...

Page 120: ...for a load access or H 060 for a store access is written to the EXPEVT register 5 The PC value indicating the address of the instruction in which the exception occurred is written to the SPC If the exception occurred in a delay slot the PC value indicating the address of the delayed branch instruction is written to the SPC 6 The contents of SR at the time of the exception are written into SSR 7 Th...

Page 121: ... the exception occurred in a delay slot the PC value indicating the address of the related delayed branch instruction is written to the SPC 5 The contents of SR at the time of the exception are written to SSR 6 The MD bit in SR is set to 1 and switched to the privileged mode 7 The BL bit in SR is set to 1 to mask any further exception requests 8 The RB bit in SR is set to 1 9 The way that caused t...

Page 122: ...PR check Yes SH 0 and MMUCR SV 0 or SR MD 0 VPNs and ASIDs match VPNs match No Yes Yes Yes Yes User or privileged D 1 C 1 V 1 No No User mode Privileged mode No No TLB protection violation exception TLB protection violation Cache access W 00 01 10 01 11 00 10 11 W W W R R R R R W R W R W R W TLB invalid exception Memory access No noncacheable Yes cacheable Figure 3 10 MMU Exception Generation Flow...

Page 123: ...ure 3 11 shows the MMU exception signals in the instruction fetch mode ID EX MA WB ID EX MA WB ID EX MA WB NOP NOP IF ID EX MA WB Exception source stage IF ID EX MA WB NOP MMU exception handler Handler transition processing Instruction fetch Instruction decode Instruction execution Memory access Write back No operation IF Legend Figure 3 11 MMU Exception Signals in Instruction Fetch ...

Page 124: ... EX MA WB ID EX MA WB ID EX MA WB NOP NOP IF ID EX MA WB Exception source stage Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP Instruction fetch Instruction decode Instruction execution Memory access Write back No operation MMU exception handler Handler transition processing MA WB MA WB EX MA WB Legend Figure 3 12 MMU Exception Signals in Data Access ...

Page 125: ...cting the way bits 9 8 00 is way 0 01 is way 1 10 is way 2 11 is way 3 and H F2 to indicate address array access bits 31 to 24 The IX bit in MMUCR indicates whether an EX OR is taken of the entry address and ASID When writing the write is performed to the entry selected with the index address and way When reading the VPN V bit and ASID of the entry selected with the index address and way in the fo...

Page 126: ... 3 2 1 0 X V X X VPN 31 16 Data field 2 TLB Data Array Access 12 10 11 8 9 7 12 10 11 8 9 7 12 10 11 8 9 7 12 10 11 8 9 7 6 0 0 ASID 0 V VPN 0 0 17 VPN 16 12 10 11 VPN 31 ASID 8 9 7 0 V D C SH PR SZ VPN V W Virtual page number Valid bit Way 00 Way 0 01 Way 1 10 Way 2 11 Way 3 ASID Address space identifier Don t care PPN PR C SH VPN X W Legend Legend Physical page number Protection key field Cachea...

Page 127: ...is cleared to 0 achieving invalidation MOV L R0 R1 Reading the Data of a Specific Entry This example reads the data section of a specific TLB entry The bit order indicated in the data field in figure 3 14 2 is read R0 specifies the address and the data section of a selected entry is read to R1 R0 H F300 4300 VPN 16 12 B 0 0100 Way 3 MOV L R0 R1 3 7 Usage Note 3 7 1 Use of Instructions Manipulating...

Page 128: ... 0 12345 0 3 12345 0 3 12345 1 A condition may also be satisfied when the TLB is handled by software For example if an entry in the TLB address array is registered to way 3 after way 0 is disabled V bit is changed from 1 to 0 the state of that entry becomes as shown below Similar to the above case the same VPN exists in both way 0 and way 3 and condition 2 above is satisfied After way 0 is disable...

Page 129: ...are saved in the saved program counter SPC and saved status register SSR respectively and execution of the exception handler is invoked from a vector address The return from exception handler RTE instruction is issued by the exception handler routine at the completion of the routine restoring the contents of the PC and SR to return to the processor state at the point of interruption and the addres...

Page 130: ...gure 4 1 shows the relationship between the vector base address the vector offset and the vector table VBR Vector base address Vector offset H A000 0000 Vector address Figure 4 1 Vector Addresses In table 4 1 exceptions and their vector addresses are listed by exception type instruction completion state relative acceptance priority relative order of occurrence within an instruction execution seque...

Page 131: ...dress error 2 12 H 00000100 Nonmaskable interrupt 3 H 00000600 External hardware interrupt 4 3 H 00000600 General interrupt requests Completed H UDI interrupt 4 3 H 00000600 Notes 1 Priorities are indicated from high to low 1 being highest and 4 being lowest 2 The user defines the break point traps 1 is a break point before instruction execution and 11 is a break point after instruction execution ...

Page 132: ...ions and are mutually exclusive events in the instruction pipeline They have the same execution priority Figure 4 2 shows the order of general exception acceptance IF Instruction n ID EX MA TLB miss data access WB IF Instruction n 1 Instruction n 2 ID EX MA TLB miss instruction access WB IF ID EX MA RIE reserved instruction exception WB Pipeline Sequence TLB miss instruction n Re execution of inst...

Page 133: ...es Table 4 2 lists the exception codes written to bits 11 to 0 of the EXPEVT register for reset or general exceptions or the INTEVT and INTEVT2 registers for general interrupt requests to identify each specific exception event An additional exception register the TRAPA TRA register is used to hold the 8 bit immediate data in an unconditional trap TRAPA instruction Table 4 2 Exception Codes Excepti...

Page 134: ...4 1 5 Exception Request and BL Bit If a general exception event occurs when the BL bit in SR is 1 the CPU s internal registers are set to their post reset state other module registers retain their contents prior to the general exception and a branch is made to the same address H A0000000 as for a reset If a general interrupt occurs when BL 1 the request is masked held pending and not accepted unti...

Page 135: ...terrupt event register 2 should be initialized by software Refer to section 23 List of Registers for more details of the addresses and access sizes Exception event register EXPEVT Interrupt event register INTEVT Interrupt event register 2 INTEVT2 TRAPA exception register TRA 4 2 1 Exception Event Register EXPEVT The exception event register EXPEVT contains a 12 bit exception code The exception cod...

Page 136: ...so be modified by software Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 0 R W 12 bit interrupt exception code or a code indicating the interrupt priority 4 2 3 Interrupt Event Register 2 INTEVT2 The interrupt event register 2 INTEVT2 contains a 12 bit exception code The exception code set in INTEVT2 is...

Page 137: ...e SH7706 from the initialization state The RESETP signal and RESETM signal are sampled every clock cycle and in the case of a power on reset all processing being executed excluding the RTC is suspended all unfinished events are canceled and reset processing is executed immediately In the case of a manual reset however reset processing is executed after memory access in progress is completed The re...

Page 138: ... the value of the contents of the VBR and H 00000600 to invoke the exception handler 4 3 3 General Exceptions When the SH7706 encounters any exception condition other than a reset or interrupt request it executes the following operations 1 The contents of the PC and SR are saved in the SPC and SSR respectively 2 The BL bit in SR is set to 1 masking any subsequent exceptions 3 The MD bit in SR is s...

Page 139: ...t from the STATUS0 and STATUS1 pins Manual Reset Conditions RESETM low Operations EXPEVT set to H 020 VBR and SR initialized branch to PC H A0000000 Initialization sets the VBR register to H 0000000 In SR the MD RB and BL bits are set to 1 and the interrupt mask bits I3 to I0 are set to B 1111 The CPU and on chip supporting modules are initialized For details refer to section 23 List of Registers ...

Page 140: ... the instruction that generated the exception are saved to the SPC and SSR respectively If the exception occurred during a read H 040 is set in EXPEVT if the exception occurred during a write H 060 is set in EXPEVT The BL MD and RB bits in SR are set to 1 and a branch occurs to PC VBR H 0400 To speed up TLB miss processing the offset differs from other exceptions TLB invalid exception Conditions C...

Page 141: ...0 Only read enabled No access 01 Read write enabled No access 10 Only read enabled Only read enabled 11 Read write enabled Read write enabled Operations The virtual address 32 bits that caused the exception is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 to 10 The ASID of PTEH indicates the ASID at the time the exception occurred The way that generated the excepti...

Page 142: ...n exception Conditions When corresponded to the following items A When undefined code not in a delay slot is decoded Delay branch instructions JMP JSR BRA BRAF BSR BSRF RTS RTE BT S BF S Undefined instruction H Fxxx In the case of SR CL 1 the value should be B 111111xxxxxxxxxx B When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions LDC STC RTE LDTLB SLEE...

Page 143: ...in EXPEVT The BL MD and RB bits in SR are set to 1 and a branch occurs to PC VBR H 0100 See section 7 User Break Controller for more information DMA Address error Conditions When corresponded to the following items A Word data accessed from addresses other than word boundaries 4n 1 4n 3 B Longword accessed from addresses other than longword boundaries 4n 1 4n 2 4n 3 Operations The PC of the instru...

Page 144: ...TEVT and INTEVT2 The BL MD and RB bits of the SR are set to 1 and a branch occurs to VBR H 0600 The received level is not set to the interrupt mask bit of SR See section 6 Interrupt Controller INTC for more information On Chip Peripheral Module Interrupts Conditions The interrupt mask bit of SR is lower than the on chip peripheral module TMU RTC SCI0 SCI2 A D LCDC PCC DMAC WDT REF interrupt level ...

Page 145: ...s made to the fixed address of the reset H A0000000 In this case the values of the EXPEVT SPC and SSR registers are undefined Differently from general reset processing no signal is output from STATUS0 and STATUS1 SPC when an Exception Occurs The PC saved to the SPC when an exception occurs is as shown below Re executing type exceptions The PC of the instruction that caused the exception is set in ...

Page 146: ... exception is not generated at an RTE instruction delay slot as operation is not guaranteed in this case When the BL bit in the SR register is set to 1 ensure that a TLB related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction This occurrence will be identified as multiple exceptions and may initiate reset processing ...

Page 147: ...anks each of which is divided into an address section and a data section Each of the address and data sections is divided into 256 entries The data section of the entry is called a line Each line consists of 16 bytes 4 bytes 4 The data capacity per way is 4 kbytes 16 bytes 256 entries with a total of 16 kbytes in the cache as a whole 4 ways Figure 5 1 shows the cache structure 24 1 1 22 bits 128 3...

Page 148: ...et associative system up to four instructions or data with the same entry address address bits 11 to 4 can be registered in the cache When an entry is registered the LRU bits show which of the four ways it is recorded in There are six LRU bits controlled by hardware A least recently used LRU algorithm which selects the way that has been used least recently is used to select the way The LRU bits al...

Page 149: ...the contents of the CCR register should be placed in address space that is not cached Bit Bit Name Initial Value R W Description 31 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 CF 0 R Cache Flash When 1 is set the V U and LRU bits of all cache entries are cleared to 0 flush This bit is always read as 0 Write back to external memory is not performed whe...

Page 150: ...at have been valid in the cache are maintained For instance if one line size of data pointed by Rn exists at way 0 and if the prefetch instruction is executed while the cache lock W3LOAD and W3LOCK are set to 1s a cache hit occurs and data is not brought to way 3 When a cache is accessed by other than the prefetch instruction in cache locking mode the ways to be replaced are controlled by the W3LO...

Page 151: ...vel the cache is locked The locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF condition during cache locking mode watches During cache locking mode the LRU in table 5 1 will be replaced by tables 5 4 to 5 6 Table 5 2 Way to be Replaced when Cache Miss Occurs during PREF Instruction Execution CL bit W3LOAD W3LOCK W2LOAD W2LOCK Way to be Replaced 0 According ...

Page 152: ...1 LRU 5 to 0 Way to be Replaced 000000 000001 000100 010100 100000 100001 110000 110100 3 000011 000110 000111 001011 001111 010110 011110 011111 1 101001 101011 111000 111001 111011 111100 111110 111111 0 Table 5 5 LRU and Way Replacement When W3LOCK 1 LRU 5 to 0 Way to be Replaced 000000 000001 000011 001011 100000 100001 101001 101011 2 000100 000110 000111 001111 010100 010110 011110 011111 1 ...

Page 153: ...n its address section Entries are selected using bits 11 to 4 of the address virtual of the access to memory and the address tag of that entry is read In parallel to reading of the address tag the virtual address is translated to a physical address in the MMU The physical address after translation and the physical address read from the address section are compared The address comparison uses all f...

Page 154: ...5 2 Cache Search Scheme Normal Mode 5 3 2 Read Access Read Hit In a read access instructions and data are transferred from the cache to the CPU The LRU is updated Read Miss An external bus cycle starts and the entry is updated The way replaced is shown in table 5 3 Entries are updated in 16 byte units When the desired instruction or data that caused the miss is loaded from external memory to the c...

Page 155: ...to the write back buffer The write back unit is 16 bytes Data is written to the cache and the U bit and V bit are set to 1 After the cache completes its fill cycle the write back buffer writes back the entry to the memory In the write through mode no write to cache occurs in a write miss the write is only to the external memory 5 3 5 Write Back Buffer When the U bit of the entry to be replaced in ...

Page 156: ... for write accesses must be specified The address field specifies information for selecting the entry to be accessed the data field specifies the tag address V bit U bit and LRU bits to be written to the address array figure 5 4 1 In the address field specify the entry address for selecting the entry bits 11 to 4 W for selecting the way bits 13 and 12 00 is way 0 01 is way 1 10 is way 2 and 11 is ...

Page 157: ...ess field for read write accesses and 32 bit data field for write accesses must be specified The address field specifies information for selecting the entry to be accessed the data field specifies the longword data to be written to the data array In the address field specify the entry address for selecting the entry bits 11 to 4 L indicating the longword position within the 16 byte line bits 3 and...

Page 158: ...accesses Address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 0 0 0 0 W Entry address 31 24 23 14 13 12 11 4 3 0 1111 0000 W Entry address 2 A 313029 10 4 3 0 LRU 2 X 0 0 0 X 9 Address tag 28 10 U V 1 31 24 23 14 13 12 11 4 3 0 1111 0001 W Entry address 0 0 1 2 L Data specification 31 0 Longword Legend X 0 for read don t care for write Don t care 0 2 Figure 5 4 Specifying Address and Data fo...

Page 159: ... written when a match is found If no match is found there is no operation When the V bit of the entry is 1 a write back occurs R0 H 0110 0010 VPN B 00 0000 0100 0100 0000 0000 U 0 V 0 R1 H F000 0088 address array access entry B 0000 1000 A 1 MOV L R0 R1 2 Reading the Data of a Specific Entry This example reads the data section of a specific cache entry The longword indicated in the data field of t...

Page 160: ...Section 5 Cache Rev 5 00 May 29 2006 page 112 of 698 REJ09B0146 0500 ...

Page 161: ...y setting the five interrupt priority registers the priorities of on chip peripheral module IRQ interrupts can be selected from 16 levels for individual request sources NMI noise canceler function NMI input level bit indicates NMI pin states By reading this bit in the interrupt exception service routine the pin state can be checked enabling it to be used as a noise canceler External devices can be...

Page 162: ...face with FIFO Watchdog timer Refresh requests in the bus state controller Interrupt control register Registers A E for setting the interrupt proprity levels Status register Direct memory access controller Analog to digital converter User debugging interface TMU RTC SCI SCIF WDT REF ICR IPRA IPRE SR DMAC ADC H UDI CPU Internal bus Bus interface 2 1 0 H UDI Interrupt request Legend INTC IPR Interru...

Page 163: ... has the highest priority level of 16 When the BLMSK bit of the interrupt control register ICR1 is 1 or the BL bit of the status register SR is 0 NMI interrupts are accepted when the MAI bit of the ICR1 register is 0 NMI interrupts are edge detected In sleep or software standby mode the interrupt is accepted regardless of the BL The NMI edge select bit NMIE in the interrupt control register 0 ICR0...

Page 164: ... 0 to interrupt request register 0 IRR0 It is necessary for an edge input interrupt detection to input a pulse width more than two cycle width by peripheral clock Pφ basis In level detection keep the level until the CPU accepts an interrupt and starts the interrupt processing The interrupt mask bits I3 to I0 of the status register SR are not affected by IRQ interrupt processing Interrupts IRQ4 to ...

Page 165: ...ple of IRL Interrupt Connection Table 6 2 IRL3 IRL3 IRL3 IRL3 to IRL0 IRL0 IRL0 IRL0 Pins and Interrupt Levels IRL3 IRL3 IRL3 IRL3 IRL2 IRL2 IRL2 IRL2 IRL1 IRL1 IRL1 IRL1 IRL0 IRL0 IRL0 IRL0 Interrupt Priority Level Interrupt Request 0 0 0 0 15 Level 15 interrupt request 0 0 0 1 14 Level 14 interrupt request 0 0 1 0 13 Level 13 interrupt request 0 0 1 1 12 Level 12 interrupt request 0 1 0 0 11 Lev...

Page 166: ...by IRL interrupt processing 6 3 4 On Chip Peripheral Module Interrupts On chip peripheral module interrupts are generated by the following eight modules Timer unit TMU Realtime clock RTC Serial communication interface SCI SCIF Bus state controller BSC Watchdog timer WDT Direct memory access controller DMAC A D converter ADC User debugging interface H UDI Not every interrupt source is assigned a di...

Page 167: ...et to zero by RESET When the order of priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time they are processed according to the default order listed in tables 6 3 and 6 4 Table 6 3 Interrupt Exception Handling Sources and Priority IRQ Mode Interrupt Source INTEVT Code INTEVT2 Code Interrupt Priority Initial Value IPR Bit Numbers Prio...

Page 168: ... IPRA 15 to 12 TMU1 TUNI1 H 420 H 420 0 to 15 0 IPRA 11 to 8 TUNI2 H 440 H 440 High TMU2 TICPI2 H 460 H 460 0 to 15 0 IPRA 7 to 4 Low ATI H 480 H 480 High PRI H 4A0 H 4A0 RTC CUI H 4C0 H 4C0 0 to 15 0 IPRA 3 to 0 Low ERI H 4E0 H 4E0 High RXI H 500 H 500 TXI H 520 H 520 SCI SCI0 TEI H 540 H 540 0 to 15 0 IPRB 7 to 4 Low WDT ITI H 560 H 560 0 to 15 0 IPRB 15 to 12 RCMI H 580 H 580 High BSC REF ROVI ...

Page 169: ...3 0 0101 H 2A0 H 2A0 10 IRL 3 0 0110 H 2C0 H 2C0 9 IRL 3 0 0111 H 2E0 H 2E0 8 IRL 3 0 1000 H 300 H 300 7 IRL 3 0 1001 H 320 H 320 6 IRL 3 0 1010 H 340 H 340 5 IRL 3 0 1011 H 360 H 360 4 IRL 3 0 1100 H 380 H 380 3 IRL 3 0 1101 H 3A0 H 3A0 2 IRL IRL 3 0 1110 H 3C0 H 3C0 1 IRQ4 H 200 to 3C0 H 680 0 to 15 0 IPRD 3 to 0 IRQ IRQ5 H 200 to 3C0 H 6A0 0 to 15 0 IPRD 7 to 4 DEI0 H 200 to 3C0 H 800 High DEI1...

Page 170: ... H 420 H 420 0 to 15 0 IPRA 11 to 8 TUNI2 H 440 H 440 High TMU2 TICPI2 H 460 H 460 0 to 15 0 IPRA 7 to 4 Low ATI H 480 H 480 High PRI H 4A0 H 4A0 RTC CUI H 4C0 H 4C0 0 to 15 0 IPRA 3 to 0 Low ERI H 4E0 H 4E0 High RXI H 500 H 500 TXI H 520 H 520 SCI SCI0 TEI H 540 H 540 0 to 15 0 IPRB 7 to 4 Low WDT ITI H 560 H 560 0 to 15 0 IPRB 15 to 12 RCMI H 580 H 580 High BSC REF ROVI H 5A0 H 5A0 0 to 15 0 IPR...

Page 171: ...he following registers Refer to section 23 List of Registers for more details of the addresses and access sizes Interrupt control register 0 ICR0 Interrupt control register 1 ICR1 Interrupt priority level setting register A IPRA Interrupt priority level setting register B IPRB Interrupt priority level setting register C IPRC Interrupt priority level setting register D IPRD Interrupt priority level...

Page 172: ... bits Table 6 6 Interrupt Request Sources and IPRA to IPRE Register Bits 15 to 12 Bits 11 to 8 Bits 7 to 4 Bits 3 to 0 IPRA TMU0 TMU1 TMU2 RTC IPRB WDT REF SCI0 Reserved IPRC IRQ3 IRQ2 IRQ1 IRQ0 IPRD Reserved Reserved IRQ5 IRQ4 IPRE DMAC Reserved SCIF ADC Note These bits are always read as 0 The write value should be 0 As shown in table 6 6 four sets of on chip peripheral module IRQ interrupts are...

Page 173: ...I Input Level Sets the level of the signal input at the NMI pin This bit can be read to determine the NMI pin level This bit cannot be modified 0 NMI input level is low 1 NMI input level is high 14 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 NMIE 0 R W NMI Edge Select Selects whether the interrupt request signal is detected on the falling or rising ed...

Page 174: ...re not masked when a low level is being input to the NMI pin 1 All interrupt requests are masked when a low level is being input to the NMI pin 14 IRQLVL 1 R W Interrupt Request Level Detect Selects whether the IRQ3 to IRQ0 pins are used as four independent interrupt pins or as 15 level interrupt pins encoded as IRL3 to IRL0 0 Used as four independent interrupt request pins IRQ3 to IRQ0 1 Used as ...

Page 175: ...R W R W IRQ4 Sense Select Select whether the interrupt signal to the IRQ4 pin is detected at the rising edge at the falling edge or at low level 00 An interrupt request is detected at IRQ4 input falling edge 01 An interrupt request is detected at IRQ4 input rising edge 10 An interrupt request is detected at IRQ4 input low level 11 Reserved Setting prohibited 7 6 IRQ31S IRQ30S 0 0 R W R W IRQ3 Sens...

Page 176: ...W R W IRQ1 Sense Select Select whether the interrupt signal to the IRQ1 pin is detected at the rising edge at the falling edge or at low level 00 An interrupt request is detected at IRQ1 input falling edge 01 An interrupt request is detected at IRQ1 input rising edge 10 An interrupt request is detected at IRQ1 input low level 11 Reserved Setting prohibited 1 0 IRQ01S IRQ00S 0 0 R W R W IRQ0 Sense ...

Page 177: ...sary to clear the flag when using level sensing because this bit merely shows the status of the IRQ5 pin 0 An interrupt request is not input to IRQ5 pin 1 An interrupt request is input to IRQ5 pin 4 IRQ4R 0 R W IRQ4 Interrupt Request Indicates whether an interrupt request is input to the IRQ4 pin When edge detection mode is set for IRQ4 an interrupt request is cleared by clearing the IRQ4R bit It ...

Page 178: ...ates whether an interrupt request is input to the IRQ1 pin When edge detection mode is set for IRQ1 an interrupt request is cleared by clearing the IRQ1R bit It is not necessary to clear the flag when using level sensing because this bit merely shows the status of the IRQ1 pin 0 An interrupt request is not input to IRQ1 pin 1 An interrupt request is input to IRQ1 pin 0 IRQ0R 0 R W IRQ0 Interrupt R...

Page 179: ...3 DMAC interrupt request is generated 0 A DEI3 interrupt request is not generated 1 A DEI3 interrupt request is generated 2 DEI2R 0 R DEI2 Interrupt Request Indicates whether a DEI2 DMAC interrupt request is generated 0 A DEI2 interrupt request is not generated 1 A DEI2 interrupt request is generated 1 DEI1R 0 R DEI1 Interrupt Request Indicates whether a DEI1 DMAC interrupt request is generated 0 ...

Page 180: ...I interrupt request is generated 3 TXI2R 0 R TXI2 Interrupt Request Indicates whether a TXI2 SCIF interrupt request is generated 0 TXI2 interrupt request is not generated 1 A TXI2 interrupt request is generated 2 BRI2R 0 R BRI2 Interrupt Request Indicates whether a BRI2 SCIF interrupt request is generated 0 A BRI2 interrupt request is not generated 1 A BRI2 interrupt request is generated 1 RXI2R 0...

Page 181: ...an interrupt a low level is output from the IRQOUT pin 4 Detection timing The INTC operates in synchronization with the peripheral clock Pφ and reports the interrupt request to the CPU The CPU receives an interrupt at a break in instruction 5 The interrupt source code is set in the interrupt event registers INTEVT and INTEVT2 6 The SR and PC are saved to SSR and SPC respectively 7 The BL MD and RB...

Page 182: ...es Yes Yes Yes Yes Yes No No No No No No No No No No No No No Program execution state Save SR to SSR save PC to SPC Set interrupt cause in INTEVT INTEVT2 Set BL MD RB bits in SR to 1 Branch to exception handler Interrupt generated ICR1 MAI 1 ICR1 BLMSK 1 IRQOUT 1 NMI low NMI NMI SR BL 0 or sleepmode Level 14 interrupt Level 1 interrupt I3 to I0 level 13 or lower I3 to I0 level 0 Level 15 interrupt...

Page 183: ... Execute the RTE instruction When these procedures are followed in order an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4 6 6 Interrupt Response Time The time from generation of an interrupt request until interrupt exception processing is performed and fetching of the first instruction of the exception handler is started the interrupt response ...

Page 184: ...X 0 Icyc X 0 Icyc Interrupt exception processing is kept waiting until the executing instruction ends If the number of instruction execution states is S 1 the maximum wait time is X S 1 However if BL is set to 1 by instruc tion execution or by an exception interrupt exception processing is deferred until completion of an instruction that clears BL to 0 If the following instruction masks interrupt ...

Page 185: ...f Iφ Bcyc Duration of one cycle of Bφ Pcyc Duration of one cycle of Pφ Notes 1 S also includes the memory access wait time The processing requiring the maximum execution time is LDC L Rm SR When the memory access is a cache hit this requires seven instruction execution cycles When the external access is performed the corresponding number of cycles must be added There are also instructions that per...

Page 186: ...IF ID EX 5 Icyc Start of interrupt processing Legend IF Instruction fetch Instruction is fetched from memory in which program is stored ID Instruction decode Fetched instruction is decoded EX Instruction execution Data operation and address calculation are performed in accordance with result of decoding Overrun fetch First instruction of interrupt handler Figure 6 4 Example of Pipeline Operations ...

Page 187: ...of break channels channels A and B Address comparison bits are masked in units of 32 bits One of the two address buses the virtual address bus LAB and the internal address bus IAB can be selected Data only on channel B 32 bit maskable One of two data buses the virtual data bus LDB or the internal data bus IDB can be selected Bus master CPU cycle or DMAC cycle Bus cycle instruction fetch or data ac...

Page 188: ...break request UBC Location CCN Location LDB IDB Access Control Legend BBRA Break bus cycle register A BARA Break address register A BAMRA Break address mask register A BASRA Break ASID register A BBRB Break bus cycle register B BARB Break address register B BAMRB Break address mask register B BASRB Break ASID register B BDRB Break data register B BDMRB Break data mask register B BETR Break executi...

Page 189: ... B BAMRB Break bus cycle register B BBRB Break data register B BDRB Break data mask register B BDMRB Break control register BRCR Execution count break register BETR Branch source register BRSR Branch destination register BRDR Break ASID register A BASRA Break ASID register B BASRB 7 2 1 Break Address Register A BARA BARA is a 32 bit read write register BARA specifies the address used as a break co...

Page 190: ...sk Bit Specifies bits masked in the channel A break address bits specified by BARA BAA31 to BAA0 0 Break address bit BAAn of channel A is included in the break condition 1 Break address bit BAAn of channel A is masked and is not included in the break condition Note n 31 to 0 7 2 3 Break Bus Cycle Register A BBRA Break bus cycle register A BBRA is a 16 bit read write register which specifies 1 CPU ...

Page 191: ...ition 00 Condition comparison is not performed 01 The break condition is the instruction fetch cycle 10 The break condition is the data access cycle 11 The break condition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R W R W Read Write Select A Selects the read cycle or write cycle as the bus cycle of the channel A break condition 00 Condition comparison is not performed 0...

Page 192: ... B BAMRB BAMRB is a 32 bit read write register BAMRB specifies bits masked in the break address specified by BARB Bit Bit Name Initial Value R W Description 31 to 0 BAMB31 to BAMB0 All 0 R W Break Address Mask Specifies bits masked in the channel B break address bits specified by BARB BAB31 to BAB0 0 Break address BABn of channel B is included in the break condition 1 Break address BABn of channel...

Page 193: ...s selected as a break condition the break data must be set in bits 15 to 8 in BDRB for an even break address and bits 7 to 0 for an odd break address 7 2 8 Break Bus Cycle Register B BBRB Break bus cycle register B BBRB is a 16 bit read write register which specifies 1 CPU cycle or DMAC cycle 2 instruction fetch or data access 3 read write and 4 operand size in the break conditions of channel B Bi...

Page 194: ... instruction fetch cycle or data access cycle 3 2 RWB1 RWB0 0 0 R W R W Read Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition 00 Condition comparison is not performed 01 The break condition is the read cycle 10 The break condition is the write cycle 11 The break condition is the read cycle or write cycle 1 0 SZB1 SZB0 0 0 R W R W Operand Size Se...

Page 195: ...variety of break conditions Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 BASMA 0 R W Break ASID Mask A Specifies whether the bits of the channel A break ASID7 to ASID0 BASA7 to BASA0 set in BASRA are masked or not 0 All BASRA bits are included in break condition ASID is checked 1 No BASRA bits are include...

Page 196: ...In order to clear this flag write 0 into this bit 0 The CPU cycle condition for channel B does not match 1 The CPU cycle condition for channel B matches 13 SCMFDA 0 R W DMAC Condition Match Flag A When the on chip DMAC bus cycle condition in the break conditions set for channel A is satisfied this flag is set to 1 not cleared to 0 In order to clear this flag write 0 into this bit 0 The DMAC cycle ...

Page 197: ... 0 R Reserved These bits are always read as 0 The write value should always be 0 7 DBEB 0 R W Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B 0 No data bus condition is included in the condition of channel B 1 The data bus condition is included in the condition of channel B 6 PCBB 0 R W PC Break Select B Selects the break timing of ...

Page 198: ...r break is issued when the number of break conditions matches with the number of execution times that is specified by the BETR register 0 The execution times break condition is masked on channel B 1 The execution times break condition is enabled on channel B 7 2 10 Execution Times Break Register BETR When the execution times break condition of channel B is enabled this register specifies the numbe...

Page 199: ...register is shifted every branch Bit Bit Name Initial Value R W Description 31 SVF 0 R BRSR Valid Flag Indicates whether the address and the pointer by which the branch source address can be calculated When a branch source address is fetched this flag is set to 1 This flag is cleared to 0 in reading BRSR 0 The value of BRSR register is invalid 1 The value of BRSR register is valid 30 to 28 PID2 to...

Page 200: ...ranch destination address is stored When a branch destination address is fetched this flag is set to 1 This flag is set to 0 in reading BRDR 0 The value of BRDR register is invalid 1 The value of BRDR register is valid 30 to 28 R Reserved These bits are always read as 0 The write value should always be 0 27 to 0 BDA27 to BDA0 R Branch Destination Address These bits store the first fetched address ...

Page 201: ...e BBRA and BBRB CPU cycle DMAC cycle select instruction fetch data access select and read write select are each set No user break will be generated if even one of these groups is set with 00 The respective conditions are set in the bits of the BRCR 2 When the break conditions are satisfied the UBC sends a user break request to the interrupt controller The break type will be sent to CPU indicating ...

Page 202: ...ed after execution the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction As with pre execution breaks this cannot be used with overrun fetch instructions When this kind of break is set for a delay branch instruction the break is generated at the instruction that then first accepts the break 4 When an instruction fetc...

Page 203: ... specified operand size When the data value is included select either byte or word 7 3 4 Sequential Break 1 By specifying SEQ in BRCR is set to 1 the sequential break is issued when channel B break condition matches after channel A break condition matches A user break is ignored even if channel B break condition matches before channel A break condition matches When channels A and B condition match...

Page 204: ... data access where the break occurred 7 3 6 PC Trace 1 Setting PCTE in BRCR to 1 enables PC traces When branch branch instruction repeat and interrupt is generated the address from which the branch source address can be calculated and the branch destination address are stored in BRSR and BRDR respectively The branch address and the pointer which corresponds to the branch are included in BRSR 2 The...

Page 205: ...s stored in the PC trace register is read BRSR and BRDR share the read pointer Read BRSR and BRDR in order the queue only shifts after BRDR is read When reading BRDR longword access should be used Also the PC trace has a trace pointer which initially points to the bottom of the queues The first pair of branch addresses will be stored at the bottom of the queues then push up when next pairs come in...

Page 206: ...ead operand size is not included in the condition No ASID check is included A user break occurs after an instruction of address H 00000404 is executed or before instructions of adresses H 00008010 to H 00008016 are executed 2 Register specifications BARA H 00037226 BAMRA H 00000000 BBRA H 0056 BARB H 0003722E BAMRB H 00000000 BBRB H 0056 BDRB H 00000000 BDMRB H 00000000 BRCR H 00000008 BASRA H 80 ...

Page 207: ...ASID check is included On channel A no user break occurs since instruction fetch is not a write cycle On channel B no user break occurs since instruction fetch is performed for an even address 4 Register specifications BARA H 00037226 BAMRA H 00000000 BBRA H 005A BARB H 0003722E BAMRB H 00000000 BBRB H 0056 BDRB H 00000000 BDMRB H 00000000 BRCR H 00000008 BASRA H 80 BASRB H 70 Specified conditions...

Page 208: ...hannel B a user break occurs before the fifth instruction execution after instructions of address H 00001000 are executed four times 6 Register specifications BARA H 00008404 BAMRA H 00000FFF BBRA H 0054 BARB H 00008010 BAMRB H 00000006 BBRB H 0054 BDRB H 00000000 BDMRB H 00000000 BRCR H 00000400 BASRA H 80 BASRB H 70 Specified conditions Channel A channel B independent mode Channel A Address H 00...

Page 209: ...ead to address H 00123456 or byte read to address H 00123456 On channel B a user break occurs with ASID H 70 when word H A512 is written in addresses H 000ABC00 to H 000ABCFE Break Condition Specified to a DMAC Data Access Cycle 1 Register specifications BARA H 00314156 BAMRA H 00000000 BBRA H 0094 BARB H 00055555 BAMRB H 00000000 BBRB H 00A9 BDRB H 00000078 BDMRB H 0000000F BRCR H 00000080 BASRA ...

Page 210: ...in BRCR and an instruction fetch cycle in BBRA the attention is as follows A break is issued and condition match flags in BRCR are set to 1 when the bus cycle conditions both for channels A and B match simultaneously 4 The change of a UBC register value is executed in MA memory access stage Therefore even if the break condition matches in the instruction fetch address following the instruction in ...

Page 211: ... the WAIT pin Wait state insertion can be controlled through software Register settings can be used to specify the insertion of 1 to 10 cycles independently for each area 1 to 38 cycles for areas 5 and 6 and the PCMCIAT interface only The type of memory connected can be specified for each area and control signals are output for direct memory connection Wait cycles are automatically inserted to avo...

Page 212: ... an interrupt request signal when the refresh counter overflows WCR1 WCR2 BCR1 Module bus MCR BSC RFCR RTCNT Comparator Refresh controller Peripheral bus Internal bus Interrupt controller Memory controller Area controller Wait controller CS0 CS6 to CS2 CE2A CE2B WAIT BS RD RD WR WE3 to WE0 RASx CASx CKE ICIORD ICIOWR IOIS16 WCR BCR MCR PCR Legend Bus interface RTCSR RTCOR BCR2 PCR Wait state contr...

Page 213: ... O When PCMCIA is used CE2A and CE2B Read write RD WR O Data bus direction indicator signal Synchronous DRAM write indicator signal Row address strobe L RASL O When synchronous DRAM is used RASL for lower 32 Mbyte address Row address strobe U RASU O When synchronous DRAM is used RASU for upper 32 Mbyte address Column address strobe CASL O When synchronous DRAM is used CASL signal for lower 32 Mbyt...

Page 214: ...little endian mode Bus release request BREQ I Bus release request signal Bus release acknowledgment BACK O Bus release acknowledge signal 8 3 Area Overview Space Allocation In the architecture of this LSI both logical spaces and physical spaces have 32 bit address spaces The logical space is divided into five areas by the value of the upper bits of the address The physical space is divided into ei...

Page 215: ...rea Physical address space Logical address space P0 U0 P1 P2 P3 P4 Note For logical address spaces P0 and P3 when the memory management unit MMU is on it can optionally generate a physical address for the logical address It can be applied when the MMU is off and when the MMU is on and each physical address for the logical address is equal except for upper three bits See table 8 2 for information o...

Page 216: ... H 20000000 n Shadow n 1 to 6 H 14000000 to H 15FFFFFF 32 Mbytes H 16000000 to H 17FFFFFF 32 Mbytes 8 16 32 3 6 5 Ordinary memory 1 PCMCIA burst ROM H 14000000 H 20000000 n to H 17FFFFFF H 20000000 n Shadow n 1 to 6 H 18000000 to H 19FFFFFF H 1A000000 to H 1BFFFFFF 32 Mbytes 8 16 32 3 6 6 Ordinary memory 1 PCMCIA burst ROM H 18000000 H 20000000 n to H 1BFFFFFF H 20000000 n Shadow n 1 to 6 7 7 Rese...

Page 217: ... byte 8 bits word 16 bits or longword 32 bits on power on reset The correspondence between the external pins MD4 and MD3 and memory size is listed in table below Table 8 3 Correspondence between External Pins MD4 and MD3 and Memory Size MD4 MD3 Memory Size 0 0 Reserved Setting prohibited 0 1 8 bits 1 0 16 bits 1 1 32 bits For areas 2 to 6 byte word and longword may be chosen for the bus width usin...

Page 218: ...pports PCMCIA standard interface specifications in physical space areas 5 and 6 except for WP The interfaces supported are basically the IC memory card interface and I O card interface stipulated in JEIDA Specifications Ver 4 2 PCMCIA2 1 Table 8 4 PCMCIA Interface Characteristics Item Feature Access Random access Data bus 8 16 bits Memory type Mask ROM OTPROM EPROM EEPROM flash memory SRAM Memory ...

Page 219: ...D 10 A11 I Address A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE PGM I Write enable WE PGM I Write enable WE 16 RDY BSY O Ready Busy IREQ O Ready Busy 17 VCC Operation power VCC Operation power 18 VPP1 Program power VPP1 Program peripheral power 19 A16 I Address A16 I Address A16 20 A15 ...

Page 220: ... O Data D14 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2A or CE2B 43 VS1 I Voltage sense 1 VS1 I Voltage sense 1 44 RFU Reserved IORD I I O read ICIORD 45 RFU Reserved IOWR I I O write ICIOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A19 49 A20 I Address A20 I Address A20 50 A21 I Address A21 I Address A21 51...

Page 221: ...on CD2 O Card detection 68 GND Ground GND Ground Note This LSI does not support WP 8 4 Register Description The BSC has 11 registers The synchronous DRAM also has a built in synchronous DRAM mode register These registers control direct connection interfaces to memory wait states and refreshes Refer to section 23 List of Registers for more details of the addresses and access sizes Bus control regis...

Page 222: ...Pull Up Specifies whether or not pins D31 to D0 are pulled up when not in use 0 Not pulled up 1 Pulled up 13 HIZMEM 0 R W Hi Z memory control Specifies the state of A25 to 0 BS CS RD WR WE DQM RD CE2A CE2B and DRAK0 1 in standby mode 0 High impedance state in standby mode 1 Driven in standby mode 12 HIZCNT 0 R W Hi Z Control Specifies the state of the RAS and the CAS signals at standby and bus rig...

Page 223: ...de in physical space area 5 When burst ROM and PCMCIA burst mode are used set the number of burst transfers 00 Access area 5 as ordinary memory 01 Burst access of area 5 4 consecutive accesses Can be used when bus width is 8 16 or 32 10 Burst access of area 5 8 consecutive accesses Can be used when bus width is 8 or 16 11 Burst access of area 5 16 consecutive accesses Can be used only when bus wid...

Page 224: ...onous DRAM 2 3 100 Reserved Setting prohibited 101 Reserved Setting prohibited 110 Reserved Setting prohibited 111 Reserved Setting prohibited 1 A5PCM 0 R W Area 5 Bus Type Designates whether to access physical space area 5 as PCMCIA space 0 Access physical space area 5 as ordinary memory 1 Access physical space area 5 as PCMCIA space 0 A6PCM 0 R W Area 6 Bus Type Designates whether to access phys...

Page 225: ...ad as 0 The write value should always be 0 13 12 A6SZ1 A6SZ0 1 1 R W R W Area 6 Bus Size Specification Specify the bus sizes of physical space area 6 When port A B is unused 00 Reserved Setting prohibited 01 Byte 8 bit size 10 Word 16 bit size 11 Longword 32 bit size When port A B is used 00 Reserved Setting prohibited 01 Byte 8 bit size 10 Word 16 bit size 11 Reserved Setting prohibited 11 10 A5S...

Page 226: ...10 Word 16 bit size 11 Longword 32 bit size When port A B is used 00 Reserved Setting prohibited 01 Byte 8 bit size 10 Word 16 bit size 11 Reserved Setting prohibited 7 6 A3SZ1 A3SZ0 1 1 R W R W Area 3 Bus Size Specification Specify the bus sizes of physical space area 3 When port A B is unused 00 Reserved Setting prohibited 01 Byte 8 bit size 10 Word 16 bit size 11 Longword 32 bit size When port ...

Page 227: ... read as 0 The write value should always be 0 8 4 3 Wait State Control Register 1 WCR1 Wait state control register 1 WCR1 is a 16 bit read write register that specifies the number of idle wait state cycles inserted for each area For some memories the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off This can result in conflicts bet...

Page 228: ... physical space 00 1 idle cycle inserted 01 1 idle cycle inserted 10 2 idle cycles inserted 11 3 idle cycles inserted 11 10 A5IW1 A5IW0 1 1 R W R W Area 5 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 5 to another space or between a read access to a write access in the same physical space 00 1 idle cycle inserted 01...

Page 229: ...ification Specify the number of idles inserted between bus cycles when switching between physical space area 2 to another space or between a read access to a write access in the same physical space 00 1 idle cycle inserted 01 1 idle cycle inserted 10 2 idle cycles inserted 11 3 idle cycles inserted 3 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 A0IW1 A0...

Page 230: ...in combination with A6W3 in PCR Also specify the burst pitch for burst transfer Refer to table 8 6 for details 12 11 10 A5W2 A5W1 A5W0 1 1 1 R W R W R W Area 5 Wait Control Specify the number of wait states inserted into physical space area 5 in combination with A5W3 in PCR Also specify the burst pitch for burst transfer Refer to table 8 7 for details 9 8 7 A4W2 A4W1 A4W0 1 1 1 R W R W R W Area 4 ...

Page 231: ...inserted into physical space area 2 For Ordinary memory Inserted Wait States WAIT Pin 00 0 Ignored 01 1 Enabled 10 2 Enabled 11 3 Enabled For Synchronus DRAM Synchronus DRAM CAS Latency 00 1 01 1 10 2 11 3 2 1 0 A0W2 A0W1 A0W0 1 1 1 R W R W R W Area 0 Wait Control Specify the number of wait states inserted into physical space area 0 Also specify the burst pitch for burst transfer Refer to table 8 ...

Page 232: ...ble 2 Enable 0 2 Enable 3 Enable 0 1 1 3 Enable 4 Enable 0 4 Enable 4 Enable 0 1 6 Enable 6 Enable 0 8 Enable 8 Enable 1 1 1 10 Enable 10 Enable Table 8 7 Area 5 Wait Control Normal Memory I F Description WCR2 s bits First Cycle Burst Cycle Excluding First Cycle Bit 12 A5W2 Bit 11 A5W1 Bit 10 A5W0 Inserted Wait States WAIT WAIT WAIT WAIT Pin Number of States Per Data Transfer WAIT WAIT WAIT WAIT P...

Page 233: ...able 0 4 Enable 0 1 6 Enable 0 8 Enable 1 1 1 10 Enable Table 8 9 Area 0 Wait Control Description WCR2 s bits First Cycle Burst Cycle Excluding First Cycle Bit 2 A0W2 Bit 1 A0W1 Bit 0 A0W0 Inserted Wait States WAIT WAIT WAIT WAIT Pin Number of States Per Data Transfer WAIT WAIT WAIT WAIT Pin 0 0 Ignored 2 Enable 0 1 1 Enable 2 Enable 0 2 Enable 3 Enable 0 1 1 3 Enable 4 Enable 0 4 Enable 4 Enable ...

Page 234: ...ues to the other bits When using synchronous DRAM do not access areas 2 and 3 until this register is initialized Bit Bit Name Initial Value R W Description 15 14 TPC1 TPC0 0 0 R W R W RAS Precharge Time When synchronous DRAM interface is selected as connected memory they set the minimum number of cycles until output of the next bank active command after precharge The number of cycles to be inserte...

Page 235: ...and This is valid only when synchronous DRAM is connected After the write cycle the next bank active command is not issued for the period TPC TRWL 00 1 cycle 01 2 cycles 10 3 cycles 11 Reserved Setting prohibited 9 8 TRAS1 TRAS0 0 0 R W R W CAS Before RAS Refresh RAS Assert Time When synchronous DRAM interface is selected as connected memory no bank active command is issues during the period TPC T...

Page 236: ...ks 0101 The row address begins with A10 The A10 value is output at A1 when the row address is output 128 M 2 M 16 bits 4 banks 64 M 2 M 8 bits 4 banks 0110 Cannot be set 0111 The row address begins with A9 The A9 value is output at A1 when the row address is output 64 M 512 k 32 bits 4 banks 2 1000 Reserved Setting prohibited 1001 Reserved Setting prohibited 1010 Reserved Setting prohibited 1011 R...

Page 237: ...H bit is 1 When the RFSH bit is 1 and this bit is 0 a CAS before RAS refresh or an auto refresh is performed on synchronous DRAM at the period set by the refresh related registers RTCNT RTCOR and RTCSR When a refresh request occurs during an external bus cycle the bus cycle will be ended and the refresh cycle performed When the RFSH bit is 1 and this bit is also 1 the synchronous DRAM will wait fo...

Page 238: ...fer Set this bit to 0 when area 6 is not set to PCMCIA Refer to table 8 10 for details 14 A5W3 0 R W Area 5 Wait Control The A5W3 bit specifies the number of inserted wait states for area 5 combined with bits A5W2 to A5W0 in WCR2 It also specifies the number of transfer states in burst transfer Set this bit to 0 when area 5 is not set to PCMCIA The relationship between the setting value and the nu...

Page 239: ...EH0 0 0 0 R W R W R W Area 5 OE WE Negate Address Delay The A5TEH bits specify the OE WE negate address delay time for the PCMCIA interface connected to area 5 000 0 5 cycle delay 001 1 5 cycle delay 010 2 5 cycle delay 011 3 5 cycle delay 100 4 5 cycle delay 101 5 5 cycle delay 110 6 5 cycle delay 111 7 5 cycle delay 8 1 0 A6TEH2 A6TEH1 A6TEH0 0 0 0 R W R W R W Area 6 OE WE Negate Address Delay T...

Page 240: ...T WAIT WAIT Pin 0 0 0 0 0 Ignored 2 Enabled 0 0 0 1 1 Enabled 2 Enabled 0 0 1 0 2 Enabled 3 Enabled 0 0 1 1 3 Enabled 4 Enabled 0 1 0 0 4 Enabled 5 Enabled 0 1 0 1 6 Enabled 7 Enabled 0 1 1 0 8 Enabled 9 Enabled 0 1 1 1 10 Enabled 11 Enabled 1 0 0 0 12 Enabled 13 Enabled 1 0 0 1 14 Enabled 15 Enabled 1 0 1 0 18 Enabled 19 Enabled 1 0 1 1 22 Enabled 23 Enabled 1 1 0 0 26 Enabled 27 Enabled 1 1 0 1 ...

Page 241: ...gister of area 2 random data is written to the address H FFFFD000 address Y H 08C0 value X or H FFFFD8C0 As a result H 0230 is written to the SDMR register The range for value X is H 0000 to H 0FFC When H 0230 is written to the SDMR register of area 3 random data is written to the address H FFFFE000 address Y H 08C0 value X or H FFFFE8C0 As a result H 0230 is written to the SDMR register The range...

Page 242: ...COR match Set condition RTCNT RTCOR Note Contents don t change when 1 is written to CMF 6 CMIE 0 R W Compare Match Interrupt Enable Enables or disables an interrupt request caused when the CMF of RTCSR is set to 1 Do not set this bit to 1 when using auto refresh 0 Disables an interrupt request caused by CMF 1 Enables an interrupt request caused by CMF 5 4 3 CKS2 CKS1 CKS0 0 0 0 R W R W R W Clock S...

Page 243: ... Set Conditions When the RFCR value has exceeded the count limit value set in LMTS Note Contents don t change when 1 is written to OVF 1 OVIE 0 R W Refresh Count Overflow Interrupt Enable OVIE selects whether to suppress generation of interrupt requests by OVF when the OVF bit of RTCSR is set to 1 0 Disables interrupt requests from the OVF 1 Enables interrupt requests from the OVF 0 LMTS 0 R W Ref...

Page 244: ...d as 0 7 to 0 All 0 R W 8 bit counter 8 4 10 Refresh Time Constant Register RTCOR The refresh time constant register RTCOR is a 16 bit read write register The values of RTCOR and RTCNT bottom 8 bits are constantly compared When the values match the CMF of RTCSR is set and RTCNT is cleared to 0 When the refresh bit RFSH of the individual memory control register MCR is set to 1 and the refresh mode ...

Page 245: ...ts are always read as 0 9 to 0 All 0 R W 10 bit counter 8 5 Operation 8 5 1 Endian Access Size and Data Alignment This LSI supports both big endian in which the 0 address is the most significant byte in the byte data and little endian in which the 0 address is the least significant byte This switchover is designated by an external pin MD5 pin at the time of a power on reset After a power on reset ...

Page 246: ... 8 Data 7 to 0 Assert Assert Longword access at 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 8 12 16 Bit External Device Big Endian Access and Data Alignment Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE3 WE3 WE3 DQMUU DQMUU DQMUU DQMUU WE2 WE2 WE2 WE2 DQMUL DQMUL DQMUL DQMUL WE1 WE1 WE1 WE1 DQMLU DQMLU DQMLU DQMLU WE0...

Page 247: ...QMLU DQMLU DQMLU DQMLU WE0 WE0 WE0 WE0 DQMLL DQMLL DQMLL DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert 1st time at 0 Data 15 to 8 Assert Word access at 0 2nd time at 1 Data 7 to 0 Assert 1st time at 2 Data 15 to 8 Assert Word access at 2 2nd time at 3 Data 7 to 0 Assert 1st time at 0 Data 31 to ...

Page 248: ... 8 Data 7 to 0 Assert Assert Longword access at 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 8 15 16 Bit External Device Little Endian Access and Data Alignment Data Bus Strobe Signals Operation D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE3 WE3 WE3 DQMUU DQMUU DQMUU DQMUU WE2 WE2 WE2 WE2 DQMUL DQMUL DQMUL DQMUL WE1 WE1 WE1 WE1 DQMLU DQMLU DQMLU DQMLU ...

Page 249: ...DQMLU DQMLU DQMLU DQMLU WE0 WE0 WE0 WE0 DQMLL DQMLL DQMLL DQMLL Byte access at 0 Data 7 to 0 Assert Byte access at 1 Data 7 to 0 Assert Byte access at 2 Data 7 to 0 Assert Byte access at 3 Data 7 to 0 Assert 1st time at 0 Data 7 to 0 Assert Word access at 0 2nd time at 1 Data 15 to 8 Assert 1st time at 2 Data 7 to 0 Assert Word access at 2 2nd time at 3 Data 15 to 8 Assert 1st time at 0 Data 7 to ...

Page 250: ...ddresses A31 to A29 are ignored and the address range is H 04000000 H 20000000 n to H 07FFFFFF H 20000000 n n 0 to 6 and n 1 to 6 are the shadow spaces Area 1 is the area specifically for the internal peripheral modules The external memories cannot be connected Control registers of peripheral modules shown below are mapped to this area 1 Their addresses are physical address to which logical addres...

Page 251: ...trols DQMHH DQMHL DQMLH and DQMLL are all asserted and addresses multiplexed Control of RAS CAS and data timing and of address multiplexing is set with MCR Area 4 Area 4 physical addresses A28 to A26 are 100 Addresses A31 to A29 are ignored and the address range is H 10000000 H 20000000 n to H 13FFFFFF H 20000000 n n 0 to 6 and n 1 to 6 are the shadow spaces Only ordinary memories like SRAM and RO...

Page 252: ...d hold times of address CS5 for the read write strobe signals can be set in the range 0 5 to 7 5 using A5TED2 to A5TED0 and A5TEH2 to A5TEH0 bits of the PCR register Area 6 Area 6 physical addresses A28 to A26 are 110 Addresses A31 to A29 are ignored and the address range is the 64 Mbytes at H 18000000 H 20000000 n H 1BFFFFFF H 20000000 n n 0 to 6 and n 1 to 6 are the shadow spaces Ordinary memori...

Page 253: ...one cycle to indicate the start of a bus cycle The CSn signal is negated on the T2 clock falling edge to secure the negation period Therefore in case of access at minimum pitch there is a half cycle negation period There is no access size specification when reading The correct access start address is output in the least significant bit of the address but since there is no access size specification...

Page 254: ...Section 8 Bus State Controller BSC Rev 5 00 May 29 2006 page 206 of 698 REJ09B0146 0500 T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS T2 Read Write Figure 8 5 Basic Timing of Basic Interface ...

Page 255: ...ples of connection to 32 16 and 8 bit data width static RAM respectively A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 8 6 Example of 32 Bit Data Width Static RAM Connection ...

Page 256: ...OE I O7 I O0 WE A17 A1 CSn RD D15 D8 WE1 D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 8 7 Example of 16 Bit Data Width Static RAM Connection A16 A0 CSn RD D7 D0 WE0 This LSI 128k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 8 8 Example of 8 Bit Data Width Static RAM Connection ...

Page 257: ...o A0 CSn RD WR RD D31 to D0 WEn D31 to D0 BS Tw T2 Read Write Figure 8 9 Basic Interface Wait Timing Software Wait Only When software wait insertion is specified by WCR2 the external wait input WAIT signal is also sampled WAIT pin sampling is shown in figure 8 10 A 2 cycle wait is specified as a software wait Sampling is performed at the transition from the Tw state to the T2 state therefore if th...

Page 258: ...xternal address area In 16 byte DMA transfer or single addressing mode or when transferring data from an external device with DACK to the external address area When accessing cache for write back T1 CKIO A25 to A0 CSn RD WR RD D31 to D0 WEn D31 to D0 WAIT Tw Tw Tw T2 Read Write BS Wait states inserted by WAIT signal Figure 8 10 Basic Interface Wait State Timing Wait State Insertion by WAIT WAIT WA...

Page 259: ...r than CS2 and CS3 are common to all areas and signals other than CKE are valid and fetched to the synchronous DRAM only when CS2 or CS3 is asserted Synchronous DRAM can therefore be connected in parallel to a number of areas CKE is negated low only when self refreshing is performed and is always asserted high at other times In the refresh cycle and mode register write cycle RASU and RASL or CASU ...

Page 260: ...E CSn RASx CASx RD WR D31 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL This LSI 64M synchronous DRAM 1M 16 bit 4 bank A13 A12 A11 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML A13 A12 A11 A0 CLK CKE CS RAS CAS WE DQ15 DQ0 DQMU DQML Note x is U or L Figure 8 11 Example of 64 Mbit Synchronous DRAM Connection 32 Bit Bus Width ...

Page 261: ...e address multiplex specification bits AMX3 AMX0 in MCR Table 8 17 shows the relationship between the address multiplex specification bits and the bits output at the address pins A25 to A17 and A0 are not multiplexed the original values are always output at these pins When A0 the LSB of the synchronous DRAM address is connected to this LSI it performs longword address specification Connection shou...

Page 262: ... L H 3 A21 4 A22 4 A15 32 bits 512k 32 bits 4 banks 2 0 1 1 1 Row address A9 to A16 A17 A18 A19 A20 A21 4 A22 4 A23 Column address A1 to A8 A9 A10 L H 3 A12 A23 A24 4 A25 4 8M 16 bits 4 banks 1 1 1 1 0 Row address A11 to A18 A19 A20 A21 A22 A23 A24 4 A25 4 Column address A1 to A8 A9 A10 L H 3 A12 A22 A23 4 A24 4 4M 16 bits 4 banks 2 1 1 0 1 Row address A10 to A17 A18 A19 A20 A21 A22 A23 4 A24 4 Co...

Page 263: ...a burst read In the example below it is assumed that four 2M 8 bit synchronous DRAMs are connected and a 32 bit data width is used and the burst length is 1 Following the Tr cycle in which ACTV command output is performed a READ command is issued in the Tc1 Tc2 and Tc3 cycles and a READA command in the Tc4 cycle and the read data is accepted on the rising edge of the external command clock CKIO fr...

Page 264: ...ycle in which an NOP command is issued for the synchronous DRAM is inserted between the Tr cycle and the Tc cycle The number of cycles from READ and READA command output cycles Tc1 Tc4 to the first read data latch cycle Td1 can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A2W1 and A2W0 or A3W1 and A3W0 in WCR2 This number of cycles corresponds to the number of synchron...

Page 265: ... is updated each time CAS is asserted As the unit of burst transfer is 16 bytes address updating is performed for A3 and A2 only A3 A2 and A1 for a 16 bit bus width The order of access is as follows in a fill operation in the event of a cache miss the missed data is read first then 16 byte boundary data including the missed data is read in wraparound mode CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 ...

Page 266: ...hen a cache through area is accessed CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Td1 Tpc Address upper bits A12 or A11 1 Address lower bits 2 Notes 1 2 Command bit Column address Figure 8 15 Basic Timing for Synchronous DRAM Single Read Burst Write The timing chart for a burst write is shown in figure 8 16 In this LSI a burst write occurs only in the event of cache write back or 16 b...

Page 267: ...therefore no command can be issued for the same bank until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started following the write command Issuance of a new command for the same bank is postponed during this interval The number of Trwl cycles can be specified by the TRWL bit...

Page 268: ... performed in the synchronous DRAM after completion of the write command and therefore no command can be issued for the same bank until precharging is completed Consequently in addition to the precharge wait cycle Tpc used in a read access cycle Trwl is also added as a wait interval until precharging is started following the write command Issuance of a new command for the same bank is postponed du...

Page 269: ...rmined by the TPC bit in MCR Whether faster execution speed is achieved by use of bank active mode or by use of basic access is determined by the probability of accessing the same row address P1 and the average number of cycles from completion of one access to the next access Ta If Ta is greater than Tpc the delay due to the precharge wait when reading is imperceptible If Ta is greater than Trw1 T...

Page 270: ...f the cycle in figure 8 19 or 8 22 An access to a different area 3 space during this time has no effect If there is an access to a different row address in the bank active state after this is detected the bus cycle in figure 8 19 or 8 22 is executed instead of that in figure 8 19 or 8 22 In bank active mode too all banks become inactive after a refresh cycle or after the bus is released as the res...

Page 271: ...006 page 223 of 698 REJ09B0146 0500 CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Address upper bits A12 or A11 1 Address lower bits 2 Notes 1 2 Command bit Column address Figure 8 18 Burst Read Timing No Precharge ...

Page 272: ... page 224 of 698 REJ09B0146 0500 CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 to D0 BS Tnop Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Address upper bits A12 or A11 1 Address lower bits 2 Notes 1 2 Command bit Column address Figure 8 19 Burst Read Timing Same Row Address ...

Page 273: ...e 225 of 698 REJ09B0146 0500 CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 to D0 BS Tp Tr Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Address upper bits A12 or A11 1 Address lower bits 2 Notes 1 2 Command bit Column address Figure 8 20 Burst Read Timing Different Row Addresses ...

Page 274: ...ay 29 2006 page 226 of 698 REJ09B0146 0500 CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 to D0 BS Tr Tc1 Tc2 Tc3 Tc4 Address upper bits A12 or A11 1 Address lower bits 2 Notes 1 2 Command bit Column address Figure 8 21 Burst Write Timing No Precharge ...

Page 275: ...ay 29 2006 page 227 of 698 REJ09B0146 0500 CKIO CS2 or CS3 RASx CASx RD WR DQMxx D31 to D0 BS Tc1 Tc2 Tc3 Tc4 Address upper bits A12 or A11 1 Address lower bits 2 Notes 1 2 Command bit Column address Figure 8 22 Burst Write Timing Same Row Address ...

Page 276: ...re 8 23 Burst Write Timing Different Row Addresses Refreshing The bus state controller is provided with a function for controlling synchronous DRAM refreshing Auto refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR If synchronous DRAM is not accessed for a long period self refresh mode in which the power consumption for data retention is low can be acti...

Page 277: ...rated and an auto refresh is performed At the same time RTCNT is cleared to zero and the count up is restarted Figure 8 25 shows the auto refresh cycle timing All bank precharging is performed in the Tp cycle then an REF command is issued in the TRr cycle following the interval specified by the TPC bits in MCR After the TRr cycle new command output cannot be performed for the duration of the numbe...

Page 278: ...d correctly and auto refreshing is performed at the correct intervals When self refreshing is activated from the state in which auto refreshing is set or when exiting standby mode other than through a power on reset auto refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self refresh mode is cleared If the transition from clearing of self refresh mode to the start of auto r...

Page 279: ...request occurs when the bus has been released by the bus arbiter refresh execution is deferred until the bus is acquired If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed so that a new refresh request is generated the previous refresh request is eliminated In order for refreshing to be performed normally care must be taken to ensure that no bus cycle or bus master...

Page 280: ... To set burst read single write CAS latency 1 to 3 wrap type sequential and burst length 1 supported by this LSI arbitrary data is written in a byte size access to the following addresses Area 2 Area 3 32 bit CAS latency 1 FFFFD840 FFFFE840 Bus width CAS latency 2 FFFFD880 FFFFE880 CAS latency 3 FFFFD8C0 FFFFE8C0 Area 2 Area 3 16 bit CAS latency 1 FFFFD420 FFFFE420 Bus width CAS latency 2 FFFFD440...

Page 281: ...ieved automatically while various kinds of initialization are being performed after auto refresh setting but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed With simple read or write access the address counter in the synchronous DRAM used for auto refreshing is not initialized and so the cycle must al...

Page 282: ...er of consecutive accesses can be set as 4 8 or 16 by bits A0BST 1 to 0 A5BST 1 to 0 or A6BST 1 to 0 When 16 bit ROM is connected 4 or 8 can be set in the same way When 32 bit ROM is connected only 4 can be set WAIT pin sampling is performed in the first access if one or more wait states are set and is always performed in the second and subsequent accesses The second and subsequent access cycles a...

Page 283: ...5 00 May 29 2006 page 235 of 698 REJ09B0146 0500 T1 TW TW TB2 TB1 TW TB2 CKIO A25 to A4 A3 to A0 CSn RD WR RD D31 to D0 BS WAIT T2 Note For a write cycle a basic bus cycle write cycle is performed TB1 Figure 8 28 Burst ROM Wait Access Timing ...

Page 284: ... In this LSI setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I O card interface as stipulated in JEIDA version 4 2 PCMCIA2 1 Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I O card interface as stipulated in JEIDA version 4 2 Figure 8 30 shows the PCMCIA space allocation When the PCMCIA i...

Page 285: ...red in the following cases In 16 byte DMA transfer or dual addressing mode or when writing data to the external address area In 16 byte DMA transfer or single addressing mode or when transferring data from an external device with DACK to the external bus area When accessing cache for write back I O space I O space I O space Area 5 H 14000000 Area 5 H 16000000 Area 6 H 18000000 Area 6 H 1A000000 Ar...

Page 286: ...WAIT IOIS16 This LSI A25 to A0 D15 to D0 CE2 OE WE PGM IORD IOWR WAIT IOIS16 CD1 CD2 CE1 PC card memory IO G G G DIR DIR G D7 to D0 D15 to D8 A25 to A0 D15 to D0 CE2 OE WE PGM WAIT CD1 CD2 CE1 PC card memory IO G G G DIR DIR G D7 to D0 D15 to D8 CE2B CE2A Output port Card detection circuit Card detection circuit Figure 8 31 Example of PCMCIA Interface ...

Page 287: ... A24 to A0 card enable CS5 CE2A CS6 CE2B and write data D15 to D0 in a write cycle become insufficient with respect to RD and WR the WE pin in this LSI This LSI provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register Also software waits by means of a WCR2 register setting and hardware waits by means of the WAIT pin can be inserted in the sa...

Page 288: ...Rev 5 00 May 29 2006 page 240 of 698 REJ09B0146 0500 CKIO Tpcm0 A25 to A0 RD WR CExx RD read D15 to D0 read D15 to D0 write WE write BS WAIT Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w Figure 8 33 Wait Timing for PCMCIA Memory Card Interface ...

Page 289: ...A5BST0 in BCR1 for physical space area 5 or bits A6BST1 and A6BST0 in BCR1 for area 6 This burst access mode is not stipulated in JEIDA version 4 2 PCMCIA2 1 but allows high speed data access using ROM provided with a burst mode etc Burst access mode timing is shown in figures 8 34 and 8 35 CKIO Tpcm1 A25 to A4 CExx A3 to A0 RD WR RD read D15 to D0 read BS Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2...

Page 290: ...8 35 Wait Timing for PCMCIA Memory Card Interface Burst Access When the entire 32 Mbyte memory space is used as IC memory card interface space the common memory attribute memory switching signal REG is generated using a port etc If 16 Mbytes or less of memory space is sufficient using 16 Mbytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be...

Page 291: ...rom H 1A000000 to H 1BFFFFFF is accessed When accessing a PCMCIA I O card the access should be performed using a non cacheable area in virtual space P2 or P3 space or an area specified as non cacheable by the MMU When an I O card interface access is made to a PCMCIA card in little endian mode dynamic sizing of the I O bus width is possible using the IOIS16 pin When a 16 bit bus width is set for ar...

Page 292: ... Controller BSC Rev 5 00 May 29 2006 page 244 of 698 REJ09B0146 0500 CKIO Tpci1 Tpci2 A25 to A0 RD WR CExx ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS Figure 8 36 Basic Timing for PCMCIA I O Card Interface ...

Page 293: ...00 May 29 2006 page 245 of 698 REJ09B0146 0500 CKIO A25 to A0 RD WR CExx ICIORD read ICIOWR write D15 to D0 read D15 to D0 write BS WAIT IOIS16 Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w Figure 8 37 Wait Timing for PCMCIA I O Card Interface ...

Page 294: ...006 page 246 of 698 REJ09B0146 0500 CKIO Tpci0 A25 to A1 CExx A0 RD WR ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS WAIT IOIS16 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w Figure 8 38 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 295: ... when an access is followed by an access to a different area and when a read access is followed by a write access from this LSI When this LSI performs consecutive write cycles the data transfer direction is fixed from this LSI to other memory and there is no problem With read accesses to the same area in principle data is output from the same data buffer and wait cycle insertion is not performed B...

Page 296: ...write cycle Bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size i e in the bus cycles when longword access is executed for the 8 bit memory At the negation of BREQ BACK is negated and bus use is restarted See Appendix B Pin Functions for the pin state when the bus is released This LSI sometimes needs to retrieve a bus it...

Page 297: ...he SR BL bit 8 5 9 Bus Pull Up With this LSI address pin pull up can be performed when the bus is released by setting the PULA bit in BCR1 to 1 The address pins are pulled up for a 4 clock period after BACK is asserted Figure 8 40 shows the address pin pull up timing Similarly data pin pull up can be performed by setting the PULD bit in BCR1 to 1 The data pins should be pulled up when the data bus...

Page 298: ...Rev 5 00 May 29 2006 page 250 of 698 REJ09B0146 0500 Pull up CKIO D31 to D0 RD CSn Pull up Figure 8 41 Pins D31 to D0 Pull Up Timing Read Cycle Pull up CKIO D31 to D0 WEn CSn Pull up Figure 8 42 Pins D31 to D0 Pull Up Timing Write Cycle ...

Page 299: ...de Direct address transfer mode The values specified in the DMAC registers indicates the transfer source and transfer destination Two bus cycles are required for one data transfer Indirect address transfer mode Data is transferred with the address stored prior to the address specified in the transfer source address in the DMAC Other operations are the same as those of direct address transfer mode ...

Page 300: ... level On chip module request Requests from on chip peripheral modules such as serial communications interface SCIF A D converter A D and a timer CMT This request can be accepted in all the channels Auto request The transfer request is generated automatically within the DMAC Selectable bus modes Cycle steal mode or burst mode Selectable channel priority levels Fixed mode The channel priority is fi...

Page 301: ...r On chip peripheral module DAR_n DMATCR_n CHCR_n DMAOR SCIF A D converter CMT DEI_n External RAM External ROM External I O memory mapped External I O with acknowledge DACK0 DACK1 DRAK0 DRAK1 DMAOR SAR_n DAR_n DMATCR_n CHCR_n DEI_n Note n 0 to 3 DMAC operation register DMAC source address register DMAC destination address register DMAC transfer count register DMAC channel control register DMA tran...

Page 302: ...ice to channel 1 DREQ acknowledge DACK1 O Strobe output to an external I O at DMA transfer request from external device to channel 1 1 DMA request acknowledge DRAK1 O Output showing that DREQ1 has been accepted 9 3 Register Description DMAC has a total of 17 registers Each channel has four control registers One other control register is shared by all channels Refer to section 23 List of Registers ...

Page 303: ...ring data in 16 byte units a 16 byte boundary address 16n must be set for the source address value Specifying other addresses does not guarantee operation The initial value is undefined by resets The previous value is held in standby mode When accessed in 16 bits the other 16 bit data which has not been accessed is held 9 3 2 DMA Destination Address Registers 0 to 3 DAR_0 to DAR_3 DMA destination ...

Page 304: ... bits are always read as 0 The write value should always be 0 When using 16 byte transfer an integral multiple of 4 4n must be set for the number of transfers to ensure normal operation The initial value is undefined by resets The previous value is held in standby mode Bit Bit Name Initial Value R W Description 31 to 24 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 305: ... Direct address mode 1 Indirect address mode 19 RO 0 R W 2 Source Address Reload RO selects whether the source address initial value is reloaded in channel 2 This bit is only valid in CHCR_2 and is not used in CHCR_0 to CHCR_1 or CHCR_3 Writing to this bit is invalid in CHCR_0 CHCR_1 and CHCR_3 0 is read if this bit is read When using 16 byte transfer this bit must be cleared to 0 specifying non r...

Page 306: ...nowledge signal output is high active or low active This bit is only valid in CHCR_0 and CHCR_1 Writing to this bit is invalid in CHCR_2 and CHCR_3 0 is read if this bit is read 0 Low active output of DACK 1 High active output of DACK 15 14 DM1 DM0 0 0 R W R W Destination Address Mode DM1 and DM0 select whether the DMA destination address is incremented decremented or left fixed 00 Fixed destinati...

Page 307: ...n 16 byte transfer 10 Source address is decremented 1 in 8 bit transfer 2 in 16 bit transfer 4 in 32 bit transfer illegal setting in 16 byte transfer 11 Reserved Setting prohibited Notes If the transfer source is specified in indirect address specify the address in which the data to be transferred is stored and which is stored as data indirect address SAR_3 Specification of SAR_3 increment or decr...

Page 308: ... device with DACK external address space 0100 Auto request 0101 Reserved Setting prohibited 0110 Reserved Setting prohibited 0111 Reserved Setting prohibited 1000 Reserved Setting prohibited 1001 Reserved Setting prohibited 1010 Reserved Setting prohibited 1011 Reserved Setting prohibited 1100 SCIF transmission 1101 SCIF reception 1110 Internal A D 1111 CMT Notes 1 External request specification i...

Page 309: ...request is specified specification of this bit is ignored and detection at the falling edge is fixed except in an auto request 0 DREQ detected in low level 1 DREQ detected at falling edge 5 TM 0 R W Transmit Mode TM specifies the bus mode when transferring data 0 Cycle steal mode 1 Burst mode 4 3 TS1 TS0 0 0 R W R W Transmit Size Bits 1 and 0 TS1 and TS0 specify the size of data to be transferred ...

Page 310: ... the count specified in DMATCR Clear condition Writing 0 after TE 1 read at power on reset or manual reset 1 Data transfer ends by the specified count 0 DE 0 R W DMAC Enable DE enables channel operation 0 Disables channel operation 1 Enables channel operation Note If an auto request is specifies specified in RS3 to RS0 transfer starts when this bit is set to 1 In an external request or an internal...

Page 311: ...lect the priority level between channels when there are transfer requests for multiple channels simultaneously 00 CH0 CH1 CH2 CH3 01 CH0 CH2 CH3 CH1 10 CH2 CH0 CH1 CH3 11 Round robin 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 AE 0 R W Address Error Flag AE indicates that an address error occurred during DMA transfer If this bit is set during data t...

Page 312: ...0 after NMIF 1 read power on reset manual reset 1 NMI input DMA transfer is disabled Setting condition This bit is set by occurrence of an NMI interrupt 0 DME 0 R W DMA Master Enable DME enables or disables DMA transfers on all channels If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1s transfer is enabled in the corresponding channel If this bit is cleared during tr...

Page 313: ...CR_0 to CHCR_3 and DMA operation register DMAOR are set the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 2 When a transfer request comes and transfer is enabled the DMAC transfers 1 transfer unit of data depending on the TS0 and TS1 settings For an auto request the transfer begins automatically when the DE bit and DME b...

Page 314: ...ated DEI interrupt request when IE 1 No Yes No Yes No Yes Yes No Yes No 3 2 Start Transfer aborted DMATCR 0 Transfer request occurs 1 DE DME 1 and NMIF TE 0 NMIF 1 or DE 0 or DME 0 Transfer end Notes 1 In auto request mode transfer begins when NMIF and TE are all 0 and the DE and DME bits are set to 1 2 DREQ level detection in burst mode external request or cycle steal mode 3 DREQ edge detection i...

Page 315: ...e transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and the AE but and NMIF bit of DMAOR are all 0 External Request Mode In this mode a transfer is performed at the request signal DREQ of an external device Choose one of the modes shown in table 9 2 according to the application system When this mode is selected if the DMA transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 a transfer is perfo...

Page 316: ...er request the transfer source must be the SCI s transmit data register TDR And if the transfer requester is the A D converter the data transfer source must be the A D data register ADDR Table 9 3 Selecting On Chip Peripheral Module Request Modes with the RS Bit RS3 RS2 RS1 RS0 DMA Transfer Request Source DMA Transfer Request Signal Source Desti nation Bus Mode 1 0 1 0 1 0 1 1 1 1 0 0 SCIF transmi...

Page 317: ... Two modes fixed mode and round robin mode are selected by the priority bits PR1 and PR0 in the DMA operation register DMAOR Fixed Mode In this mode the priority levels among the channels remain fixed There are three kinds of fixed modes as follows CH0 CH1 CH2 CH3 CH0 CH2 CH3 CH1 CH2 CH0 CH1 CH3 These are selected by the PR1 and the PR0 bits in the DMA operation register DMAOR Round Robin Mode Eac...

Page 318: ...annels 0 and 1 which were higher than channel 2 are also shifted If immediately after there is a request to transfer channel 1 only channel 1 becomes bottom priority and the priority of channels 0 and 3 which were higher than channel 1 are also shifted Channel 0 becomes bottom priority The priority of channel 0 which was higher than channel 3 is also shifted Channel 0 becomes bottom priority Prior...

Page 319: ...ds channel 0 becomes lowest priority 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends channel 1 becomes lowest priority 7 The channel 3 transfer begins 8 When the channel 3 transfer ends channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority Transfer req...

Page 320: ... data transfer timing depends on the bus mode which has cycle steal mode and burst mode Table 9 4 Supported DMA Transfers Destination Source External Device with DACK External Memory Memory Mapped External Device On Chip Peripheral Module External device with DACK Not available Dual single Dual single Not available External memory Dual single Dual Dual Dual Memory mapped external device Dual singl...

Page 321: ...red in the DMAC In the transfer between external memories as shown in figure 9 5 data is read to the DMAC from one external memory in a data read cycle and then that data is written to the other external memory in a write cycle Figures 9 6 to 9 8 show examples of the timing at this time Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module ...

Page 322: ... source address Transfer destination address CKIO A25 to A0 CSn D31 to D0 RD WEn DACKn Note Transfer between external memories DACK output in a read cycle DACK output timing is the same as that of CSn Figure 9 6 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode Transfer Source Ordinary Memory Transfer Destination Ordinary Memory ...

Page 323: ...g in the Direct Address Mode in the Dual Address Mode 16 Byte Transfer Transfer Source Ordinary Memory Transfer Destination Ordinary Memory 4 8 12 A25 to A0 CKIO CSn RAS CAS WEn RD WR DACKn D31 to D0 Data read cycle 1st cycle 2nd cycle Data write cycle Note Transfer between external memories DACK output in a read cycle DACK output timing is the same as that of CSn Transfer source address Transfer ...

Page 324: ...orarily stored in the DMAC Next the read value is output as an address and the value stored in that address is stored in the DMAC again Then the value read afterwards is written to the address specified in the transfer destination address this completes one DMA transfer 16 byte transfer is not possible Figure 9 9 shows one example In this example the transfer destination the transfer source and th...

Page 325: ...ry Transfer source module Data bus Address bus Transfer destination module SAR_3 DAR_3 Data buffer Temporary buffer D M A C First and second bus cycles When the value in the temporary buffer is an address the data is read from the transfer source module to the data buffer Third bus cycle Fourth bus cycle When the value in SAR_3 is an address the value in the data buffer is written to the transfer ...

Page 326: ...buffer DMAC data buffer 1 The internal address bus value does not change and controlled by the port 2 The DMAC does not fetch the value until 32 bit data is output to the internal data bus Notes Address read cycle NOP cycle Data read cycle NOP cycle Data write cycle 1st 2nd 3rd 4th Indirect address Transfer source address L Transfer destination address Indirect address Indirect address H Indirect ...

Page 327: ... device involved in the transfer For example in the case of transfer between external memory and an external device with DACK as shown in figure 9 11 when the external device outputs data to the data bus that data is written to the external memory in the same bus cycle DMAC SH7706 DACK DREQ External address bus External data bus External memory External device with DACK Data flow Figure 9 11 Data ...

Page 328: ...e with DACK Write strobe signal to external memory space Address output to external memory space Data output from external memory space DACK signal active low to external device with DACK Read strobe signal to external memory space a External device with DACK external memory space ordinary memory b External memory space external device with DACK active low CKI0 A25 to A0 D31 to D0 DACKn CSn WE BS ...

Page 329: ...9 2006 page 281 of 698 REJ09B0146 0500 CKIO A25 to A0 D31 to D0 RD WEn DACKn CSn Transfer source address 4 8 12 Figure 9 13 Example of DMA Transfer Timing in the Single Address Mode 16 Byte Transfer External Memory Space Ordinary Memory External Device with DACK ...

Page 330: ...of DMA transfer timing in the cycle steal mode Transfer conditions shown in the figure are Dual address mode DREQ level detection CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU CPU DREQ Bus cycle Bus right returned to CPU Read Write Write Read Figure 9 14 DMA Transfer Example in the Cycle Steal Mode Burst Mode In the burst mode once the bus right is obtained the transfer is performed continuously without...

Page 331: ...ule All 2 B C 3 8 16 32 4 0 to 3 5 Dual On chip peripheral module and on chip peripheral module All 2 B C 3 8 16 32 4 0 to 3 5 External device with DACK and external memory External B C 8 16 32 128 0 1 Single External device with DACK and memory mapped external device External B C 8 16 32 128 0 1 B Burst C Cycle steal Notes 1 External requests auto requests and on chip peripheral module requests a...

Page 332: ...ound robin mode it will not give the bus to the CPU since channel 1 is in the burst mode This example is illustrated in figure 9 16 CPU DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1 CPU 1 2 1 Round robin mode in DMAC CH0 and CH1 DMAC CH1 Burst mode CPU CPU 1 Cycle steal mode 2 Burst mode Notes DMAC CH1 Burst mode Figure 9 16 Bus State when Multiple Channels Are Operating Priority ...

Page 333: ... the case where DREQ is not detected and sampling is subsequently executed every cycle Figure 9 21 shows an example of edge detection in the cycle steal mode Burst Mode Level Detection In the case of burst mode with level detection the DREQ sampling timing is the same as in the cycle steal mode For example in figure 9 22 DMAC transfer begins at the earliest three cycles after the first sampling is...

Page 334: ... Cycle Steal Mode Level Input CPU Access 2 Cycles CPU CPU CKIO DRAK High active DREQ DACK DMAC Read DMAC Write DMAC Read 1st sampling 2nd sampling 3rd sampling Bus cycle Figure 9 18 Cycle Steal Mode Level Input CPU Access 3 Cycles CKIO DRAK High active Bus cycle DREQ DACK RD output DMAC Read CPU DMAC Write DMAC Read CPU 1st sampling 2nd sampling 3rd sampling Figure 9 19 Cycle Steal Mode Level inpu...

Page 335: ...RAK High active Bus cycle DREQ DACK RD output CPU CPU DMAC Write DMAC Read DMAC Write DMAC Read CPU High High High High 3rd sampling is performed but since there is no DREQ falling edge per cycle sampling starts 2nd sampling is performed but since there is no DREQ falling edge per cycle sampling starts 1st sampling 2nd sampling 3rd sampling Note When a DREQ falling edge is detected DREQ must be hi...

Page 336: ...or each four transfers by setting the RO bit in CHCR_2 to 1 16 byte transfer cannot be used Figure 9 24 shows this operation Figure 9 25 shows the timing chart of the source address reload function which is under the following conditions burst mode auto request 16 bit transfer data size SAR_2 count up DAR_2 fixed reload function on and usage of only channel 2 SAR_2 initial value DMAC Transfer requ...

Page 337: ...ecrements 1 each time a transfer ends regardless of whether a reload function is on or off Consequently be sure to specify the value multiple of four in DMATCR_2 when the reload function is on Specifying other values does not guarantee the operation Though the counters that count transfers of four times for the reload function are reset by clearing the DME bit in DMAOR or the DE bit in CHCR_2 by s...

Page 338: ... external request internal request and auto request The timing from the point where the ending conditions are satisfied to the point where the DMAC stops operating differs from that in cycle steal mode In the edge detection in the burst mode though only one transfer request is generated to start up the DMAC stop request sampling is performed in the same timing as transfer request sampling in the c...

Page 339: ...it in the DMAOR is set to 1 or when the DME bit in the DMAOR is cleared to 0 Transfers ending when the AE bit or NMIF bit is set to 1 in DMAOR When an NMI interrupt occurs the AE bit or NMIF bit is set to 1 in the DMAOR and all channels stop their transfers according to the conditions in a to d described above and pass the bus right to other bus masters Consequently even if the AE bit or NMI bit i...

Page 340: ...tures Four types of counter input clock can be selected One of four internal clocks Pφ 4 Pφ 8 Pφ 16 Pφ 64 can be selected Generate DMA transfer request when compare match occurs Internal bus Bus interface Control circuit Clock selection CMSTR CMCSR CMCOR Comparator CMCNT Module bus CMT Pφ 4 Pφ 8 Pφ 16 Pφ 64 CMSTR CMCSR CMCOR CMCNT Legend Compare match timer start register Compare match timer contr...

Page 341: ...are match constant register CMCOR Compare Match Timer Start Register CMSTR The compare match timer start register CMSTR is a 16 bit register that selects whether to operate or halt the channel 0 and channel 1 counter CMCNT Bit Bit Name Initial Value R W Description 15 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 R W Reserved This bit can be read or w...

Page 342: ... and CMCOR values have matched or not 0 CMCNT and CMCOR values have not matched Clearing condition Write 0 to CMF after reading CMF 1 1 CMCNT and CMCOR values have matched 6 0 R W Reserved Both read and write are available The write value should always be 0 5 to 2 0 R Reserved These bits always read as 0 The write value should always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock select 1 and 0 These bits s...

Page 343: ...Match Constant Register CMCOR The compare match constant register CMCOR is a 16 bit register that sets the compare match period with the CMCNT The CMCOR is initialized to H FFFF by resets It retains its previous value in standby mode 9 5 3 Operation Period Count Operation When a clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR0 bit of the CMSTR is set to 1 the CMCNT ...

Page 344: ...lock CMCNT0 N 1 N Figure 9 28 Count Timing Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match The compare match signal is generated upon the final state of the match timing at which the CMCNT counter matching count value is updated Consequently after the CMCOR register and the CMCNT c...

Page 345: ...ck Compare match signal CMF CMI CMCNT N N 0 Figure 9 29 CMF Set Timing Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1 Figure 9 30 shows the timing when the CMF bit is cleared by the CPU Peripheral clock Pφ CMF CMCSR0 write cycle T1 T2 Figure 9 30 Timing of CMF Clear by the CPU ...

Page 346: ...quest generated at end of transfer CHCR_2 H 00089E35 Channel priority order 0 2 3 1 DMAOR H 0101 When the address reload function is on the values set in SAR_0 to SAR_3 returns to the initially set value at each four transfers In this example when an interrupt request is generated from A D converter longword data is read from the register in address H 04000080 in A D converter and it is written to...

Page 347: ...ransfers are executed until the value in DMATCR_2 reaches 0 and the IE bit in CHCR_2 has been set to 1 2 The transfer request source flag is cleared regardless of whether the address reload function is on or off if transfers are executed until the value in DMATCR_2 reaches 0 3 Specify the burst mode to use the address reload function This function may not be correctly executed in the cycle steal m...

Page 348: ...d that read value is used as an address again and the value stored in that address is read and stored in the corresponding address set in DAR_0 to DAR_3 In the example shown in table 9 3 when an SCIF transfer request is generated the DMAC reads the value in address H 00400000 set in SAR_3 Since the value H 00450000 is stored in that address the DMAC reads the value H 00450000 Next the DMAC uses th...

Page 349: ... normally write 0 to DMATCR_0 to DMATCR_3 Otherwise normal DMA transfer may not be performed 8 When using the address reload function specify the burst mode as a transfer mode In the cycle steal mode normal DMA transfer may not be performed 9 When using the address reload function set the value multiple of four in DMATCR_0 to DMATCR_3 Specifying other values does not guarantee normal operation 10 ...

Page 350: ...curs if the frequency multiplication ratio bits STC 2 0 are modified at the same time as IFC 2 0 These problems may be avoided by either of the following measures 1 Do not use the DMAC when in sleep mode or set the clock ratio for Iφ Bφ to 1 1 before entering sleep mode 2 Do not use the DMAC when modifying only the internal clock frequency division ratio bits IFC 2 0 to produce a clock ratio for I...

Page 351: ...ect crystal input and external clock input are available Three clocks generated independently An internal clock for the CPU cache and TLB Iφ a peripheral clock Pφ for the on chip supporting modules and a bus clock CKIO for the external bus interface Frequency change function CPU and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG F...

Page 352: ... Divider 1 CPU clock Iφ Cycle Icyc Peripheral clock Pφ Cycle Pcyc Standby control Divider 2 Clock pulse generator PLL circuit 2 1 4 Crystal oscillator CPG control unit Clock frequency control circuit Standby control circuit 1 1 2 1 3 1 4 1 1 2 1 3 1 4 1 6 Bus clock Bφ Cycle Bcyc Legend FRQCR Frequency control register STBCR Standby control register Figure 10 1 Block Diagram of Clock Pulse Generato...

Page 353: ...2 1 3 or 1 4 times the output frequency of PLL circuit 1 as long as it stays at or above the clock frequency of the CKIO pin The division ratio is set in the frequency control register 5 Divider 2 Divider 2 generates a clock at the operating frequency used by the bus clock Bφ and peripheral clock Pφ The operating frequency of the peripheral clock can be 1 1 2 1 3 1 4 or 1 6 times the output freque...

Page 354: ...t an external clock Clock I O pin CKIO I O Inputs or outputs an external clock CAP1 I Connects capacitor for PLL circuit 1 operation recommended value 470 pF Capacitor connection pins for PLL CAP2 I Connects capacitor for PLL circuit 2 operation recommended value 470 pF 10 3 Clock Operating Modes Table 10 2 shows the relationship between the mode control pin MD2 to MD0 combinations and the clock o...

Page 355: ...used The frequency ratio between EXTAL input clock and CKIO output clock is 1 4 An input clock frequency of 6 25 MHz to 16 67 MHz can be used and the CKIO frequency range is 25 MHz to 66 67 MHz Mode 2 The on chip crystal oscillator operates with the oscillation frequency being multiplied by 4 by PLL circuit 2 before being supplied inside this LSI allowing a low crystal frequency to be used The fre...

Page 356: ... 25 MHz to 33 34 MHz H A100 ON 3 ON 1 3 1 1 25 MHz to 33 34 MHz 25 MHz to 33 34 MHz H A101 ON 3 ON 1 3 1 1 2 25 MHz to 44 44 MHz 25 MHz to 44 44 MHz H E100 ON 3 ON 1 1 1 1 25 MHz to 33 34 MHz 25 MHz to 33 34 MHz 0 H E101 ON 3 ON 1 1 1 1 2 25 MHz to 44 44 MHz 25 MHz to 44 44 MHz H 0100 ON 1 ON 4 4 4 4 6 25 MHz to 8 34 MHz 25 MHz to 33 34 MHz H 0101 ON 1 ON 4 4 4 2 6 25 MHz to 16 67 MHz 25 MHz to 66...

Page 357: ...4 MHz 25 MHz to 33 34 MHz 7 H E101 ON 3 OFF 1 1 1 2 25 MHz to 44 44 MHz 25 MHz to 44 44 MHz Notes 1 This LSI cannot operate in an FRQCR value other than that listed in table 10 3 2 Taking input clock as 1 Max frequency Iφ 133 34 MHz Bφ CKIO 66 67 MHz Pφ 33 34 MHz Cautions 1 The input to divider 1 is the output of the PLL circuit 1 When PLL circuit 1 is on 2 The input of divider 2 is the output of ...

Page 358: ...quency Control Register FRQCR The frequency control register FRQCR is a 16 bit read write register used to specify the frequency multiplication ratio of PLL circuit 1 and the frequency division ratio of the CPU clock and the peripheral clock Only word access can be used on the FRQCR register The FRQCR register is initialized to H 0102 at a power on reset by the RESETP pin and retains its previous ...

Page 359: ...3 1 0 PFC2 PFC1 PFC0 0 0 0 R W R W R W Peripheral Clock Frequency Division Ratio These bits specify the division ratio Divider 2 of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin 000 1 001 1 2 100 1 3 010 1 4 101 1 6 Other than the above Reserved Setting prohibited Note Do not set the peripheral clock frequency...

Page 360: ... register CKS2 to CKS0 bits Division ratio of WDT count clock WTCNT counter Initial counter value 3 Set the desired value in the STC2 STC1 and STC0 bits The division ratio can also be set in the IFC2 to IFC0 bits and PFC2 to PFC0 bits 4 The processor pauses internally and the WDT starts incrementing At this time the CPU Iφ and peripheral clocks Pφ both stop and the clock is continuously output to ...

Page 361: ... 1 µF as a passive capacitor for each VSS VCC pair Mount the passive capacitors as close as possible to the SH7706 power supply pins and use components with a frequency characteristic suitable for the chip s operating frequency as well as a suitable capacitance value Digital system VSS VCC pairs 11 to 13 19 to 21 25 to 27 37 to 39 49 to 51 61 to 63 84 to 86 93 to 95 115 to 117 137 to 139 148 to 15...

Page 362: ...2 Vss PLL1 Avoid crossing signal lines Power supply Reference values C2 C1 Figure 10 3 Points for Attention when Using PLL Oscillator Circuit Notes on Wiring Power Supply Pins To avoid crossing signal lines wire VCC PLL1 VCC PLL2 and VSS PLL2 as three patterns from the power supply source on the board so that they are independent of digital VCC and VSS ...

Page 363: ...t Interrupt control Interrupt request Legend WTCSR Watchdog timer control status register WTCNT Watchdog timer counter Figure 11 1 Block Diagram of the WDT 11 1 Feature The WDT has the following features Can be used to ensure the clock setting time Use the WDT to cancel software standby mode and the temporary standbys that occur when the clock frequency is changed Can switch between watchdog timer...

Page 364: ... with H 5A in the upper byte Use a byte access to read WTCNT Bit Bit Name Initial Value R W Description 7 to 0 All 0 R W 8 bit counter Note The watchdog timer counter WTCNT is more difficult to write to than other registers to prevent from the erroneous writing to the register Refer to section 11 2 3 Notes on Register Access 11 2 2 Watchdog Timer Control Status Register WTCSR The watchdog timer co...

Page 365: ...as watchdog timer Note If WT IT is modified when the WDT is running the up count may not be performed correctly 5 RSTS 0 R W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode In interval timer mode this setting is ignored 0 Power on reset 1 Manual reset 4 WOVF 0 R W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode This bit ...

Page 366: ... Ensure that these bits are modified only when the WDT is not running Note The watchdog timer control status register WTCSR is more difficult to write to than other registers to prevent from the erroneous writing to the register Refer to 11 2 3 Notes on Register Access 11 2 3 Notes on Register Access The WTCNT and WTCSR are more difficult to write to than other registers The procedure for writing ...

Page 367: ...the count overflows 2 Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter These values should ensure that the time till count overflow is longer than the clock oscillation settling time 3 Move to software standby mode by executing a SLEEP instruction to stop the clock 4 The WDT starts counting by detecting the edge change o...

Page 368: ...essor resumes operation The WOVF flag in WTCSR is not set when this happens 5 The counter stops at the values H 00 to H 01 The stop value depends on the clock ratio 6 Confirm that the value of WTCNT is H 00 before writing WTCNT when WTCNT is written after the frequency change 11 3 3 Using Watchdog Timer Mode 1 Set the WT IT bit in the WTCSR register to 1 set the reset type in the RSTS bit set the ...

Page 369: ... interrupts to be generated at set periods 1 Clear the WT IT bit in the WTCSR register to 0 set the type of count clock in the CKS2 to CKS0 bits and set the initial value of the counter in the WTCNT counter 2 Set the TME bit in WTCSR to 1 to start the count in interval timer mode 3 When the counter overflows the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent t...

Page 370: ...Section 11 Watchdog Timer WDT Rev 5 00 May 29 2006 page 322 of 698 REJ09B0146 0500 ...

Page 371: ...pheral modules Note See section 10 Clock Pulse Generator CPG for more information All channels can operate when this LSI is in software standby mode When the RTC output clock is being used as the counter input clock this LSI is still able to count in software standby mode Synchronized read TCNT is a sequentially changing 32 bit register Since the peripheral module used has an internal bus width of...

Page 372: ...0 Interrupt controller Interrupt controller Interrupt controller Counter controller Counter controller TUNI1 TUNI2 TICPI2 TCR_2 TCPR_2 TCNT_2 TCOR_2 TMU Ch 1 Ch 2 Clock controller TOCR TSTR TCR_n Timer output control register Timer start register Timer control register TCNT_n TCOR_n TCPR_2 32 bit timer counter 32 bit timer constant register 32 bit input capture register Note n 0 1 2 Legend Figure ...

Page 373: ...C output pin 12 3 Register Description The TMU has the following registers Refer to section 23 List of Registers for more details of the addresses and access sizes Timer output control register TOCR Timer start register TSTR Timer constant register 0 TCOR_0 Timer counter 0 TCNT_0 Timer control register 0 TCR_0 Timer constant register 1 TCOR_1 Timer counter 1 TCNT_1 Timer control register 1 TCR_1 T...

Page 374: ... Description 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TCOE 0 R W Timer Clock Pin Control Selects use of the timer clock pin TCLK as an external clock output pin or input pin for input capture control for the on chip timer or as an output pin for the on chip RTC output clock As the TCLK pin is multiplexed as the PTE6 pin when the TCLK pin is used ...

Page 375: ...tiplying ratio of PLL circuit 1 or MSTP2 bit in STBCR is set to a logic one only when an external clock TCLK or the peripheral clock Pφ is used as the input clock Bit Bit Name Initial Value R W Description 7 to 3 All 0 R Reserved These bits are always read 0 The write value should always be 0 2 STR2 0 R W Counter Start 2 Selects whether to run or halt timer counter 2 TCNT_2 0 Halt TCNT_2 count 1 S...

Page 376: ...TCR_0 to TCR_2 are initialized to H 0000 by a power on reset and manual reset They are not initialized in standby mode In cases of Channel 0 and 1 Bit Bit Name Initial Value R W Description 15 to 9 All 0 R Reserved These bits are always read as 0 The write value should always be 0 8 UNF 0 R W Underflow Flag Status flag that indicates occurrence of a TCNT_0 and TCNT_1 underflow 0 TCNT has not under...

Page 377: ...ising and falling edge Note X Don t care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R W R W R W Timer Prescalers 2 to 0 These bits select the TCNT_0 and TCNT_1 count clock 000 Internal clock count on Pφ 4 001 Internal clock count on Pφ 16 010 Internal clock count on Pφ 64 011 Internal clock count on Pφ 256 100 Internal clock count on clock output of on chip RTC RTCCLK 101 External clock count on TCLK pin input...

Page 378: ...Clearing condition When 0 is written to UNF 1 TCNT has underflowed Setting condition When TCNT_2 underflows Note Contents do not change when 1 is written to UNF 7 6 ICPE1 ICPE0 0 0 R W R W Input Capture Control A function of channel 2 only determines whether the input capture function can be used and when used whether or not to enable interrupts When using this input capture function it is necessa...

Page 379: ...rising and falling edge Note X Don t care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R W R W R W Timer Prescalers These bits select the TCNT_2 count clock 000 Internal clock count on Pφ 4 001 Internal clock count on Pφ 16 010 Internal clock count on Pφ 64 011 Internal clock count on Pφ 256 100 Internal clock count on clock output of on chip RTC RTCCLK 101 External clock count on TCLK pin input 110 Reserved Set...

Page 380: ...n the upper and lower halves To correct the discrepancy a buffer register is connected to TCNT so that upper and lower halves are not read separately The entire 32 bit data in TCNT can thus be read at once TCNT is initialized to H FFFFFFFF by a power on reset or manual reset it is not initialized in standby mode and retains its contents 12 3 6 Input Capture Register 2 TCPR_2 The input capture regi...

Page 381: ...ction 3 Note When an interrupt has been generated clear the flag in the interrupt handler that caused it If interrupts are enabled without clearing the flag another interrupt will be generated Select the counter clock with the TPSC0 TPSC2 bits in the timer control register If the external clock is selected set the TCLK pin to input mode with the TOCE bit in TOCR and select its edge with the CKEG1 ...

Page 382: ... during underflow Time Figure 12 3 Auto Reload Count Operation TCNT count timing 1 Internal Clock Operation Set the TPSC2 to TPSC0 bits in TCR to select whether peripheral module clock Pφ or one of the four internal clocks created by dividing it is used Pφ 4 Pφ 16 Pφ 64 Pφ 256 Figure 12 4 shows the timing Pφ Internal clock Timer counter input clock TCNT N 1 N N 1 Figure 12 4 Count Timing when Inte...

Page 383: ...les for single edges or 2 5 peripheral module clock cycles for both edges A shorter pulse width will result in accurate operation Figure 12 5 shows the timing for both edge detection Pφ External clock input pin TCLK TCNT input clock TCNT N 1 N N 1 Figure 12 5 Count Timing when External Clock Is Operating Both Edges Detected 3 On Chip RTC Clock Operation Set the TPSC2 to TPSC0 bits in TCR to select...

Page 384: ...ntrol register TCR_2 Also designate use of the input capture function and whether to generate interrupts on using it with the IPCE1 and IPCE0 bits in TCR_2 and designate the use of either the rising or falling edge of the TCLK pin to set the timer counter TCNT_2 value into the input capture register TCPR_2 with the CKEG1 and CKEG0 bits in TCR_2 The input capture function cannot be used in standby ...

Page 385: ...TICPI2 12 5 1 Status Flag Set Timing UNF is set to 1 when the TCNT underflows Figure 12 8 shows the timing Pφ TCNT Underflow signal UNF TUNI TCOR value H 00000000 Figure 12 8 UNF Set Timing 12 5 2 Status Flag Clear Timing The status flag can be cleared by writing 0 from the CPU Figure 12 9 shows the timing Pφ Peripheral address bus UNF ICPF TCR address T1 T2 TCR write cycle T3 Figure 12 9 Status F...

Page 386: ...ts TMU interrupt sources Table 12 2 TMU Interrupt Sources Channel Interrupt Source Description Priority 0 TUNI0 Underflow interrupt 0 High 1 TUNI1 Underflow interrupt 1 2 TUNI2 Underflow interrupt 2 TICPI2 Input capture interrupt 2 Low 12 6 Usage Note 12 6 1 Writing to Registers Synchronization processing is not performed for timer counting during register writes When writing to registers always c...

Page 387: ...lay seconds minutes hours date day of the week month and year 1 Hz to 64 Hz timer binary display Start stop function 30 second adjust function Alarm interrupt frame comparison of seconds minutes hours date day of the week and month can be used as conditions for the alarm interrupt Cyclic interrupts the interrupt cycle may be 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second or 2 ...

Page 388: ...J EXTAL2 32 768 kHz 128 Hz XTAL2 Externally connected circuit Oscillator circuit Prescaler 128 RMONAR R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT 64 Hz counter Second counter Minute counter Hour counter Day of the week counter Date counter Month counter Year counter RSECAR RHRAR RMINAR RWKAR RDAYAR RMONAR RCR1 RCR2 Second alarm register Minute alarm register Hour alarm register Day...

Page 389: ...Notes 1 Except for in hardware standby mode even if only the RTC is used software standby mode power must be supplied to all power supply pins including these RTC power supply pins In hardware standby mode it is possible to stop supplying power to the power supply pins except for the RTC power supply pins 2 Pull up Vcc EXTAL2 and open NC XTAL2 when the RTC is not used 13 3 Register Description RTC...

Page 390: ...tes the state of the RTC divider circuit between 64 Hz and 1 Hz R64CNT is reset to H 00 by setting the RESET bit in RCR2 or the ADJ bit in RCR2 to 1 R64CNT is not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 7 0 R Always read as 0 6 to 0 R 64Hz counter Each bit bits 6 to 0 indicates the state of the RTC divider circuit between 64 and...

Page 391: ...ode The range can be set from 0 to 5 decimal 3 to 0 R W Counter for 1 unit of second in the BCD code The range can be set from 0 to 9 decimal 13 3 3 Minute Counter RMINCNT The minute counter RMINCNT is an 8 bit read write register used for setting counting in the BCD coded minute section of the RTC The count operation is performed by a carry for each minute of the second counter The range of minut...

Page 392: ...Bit Name Initial Value R W Description 7 6 All 0 R Always read as 0 5 4 R W Counter for 10 unit of hour in the BCD code The range can be set from 0 to 2 decimal 3 to 0 R W Counter for 1 unit of hour in the BCD code The range can be set from 0 to 9 decimal 13 3 5 Day of the Week Counter RWKCNT The day of the week counter RWKCNT is an 8 bit read write register used for setting counting in the BCD co...

Page 393: ...ration is performed by a carry for each day of the hour counter The range of date can be set is 01 to 31 decimal Errant operation will result if any other value is set Carry out write processing after halting the count operation with the START bit in RCR2 RDAYCNT is not initialized by a power on reset or manual reset or in standby mode The RDAYCNT range that can be set changes with each month and ...

Page 394: ...th in the BCD code The range can be set from 0 to 9 decimal 13 3 8 Year Counter RYRCNT The year counter RYRCNT is an 8 bit read write register used for setting counting in the BCD coded year section of the RTC The least significant 2 digits of the western calendar year are displayed The count operation is performed by a carry for each year of the month counter The range for year can be set is 00 t...

Page 395: ...Initial Value R W Description 7 0 R W Second Alarm Enable 0 No compared 1 Compared 6 to 4 R W Setting value for 10 unit of second alarm in the BCD code The range can be set from 0 to 5 decimal 3 to 0 R W Setting value for 1 unit of second alarm in the BCD code The range can be set from 0 to 9 decimal 13 3 10 Minute Alarm Register RMINAR The minute alarm register RMINAR is an 8 bit read write regis...

Page 396: ...RHRCNT value is performed From among the RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR registers the counter and alarm register comparison is performed only on those with ENB bits set to 1 and if each of those coincide an RTC alarm interrupt is generated The range of hour can be set is 00 to 23 decimal Errant operation will result if any other value is set The ENB bit in RHRAR is initialized by a power ...

Page 397: ...n those with ENB bits set to 1 and if each of those coincide an RTC alarm interrupt is generated The range of day of the week can be set 0 to 6 decimal Errant operation will result if any other value is set The ENB bit in RWKAR is initialized by a power on reset The remaining RWKAR fields are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Desc...

Page 398: ...an RTC alarm interrupt is generated The range of date can be set 01 to 31 decimal Errant operation will result if any other value is set The RDAYCNT range that can be set changes with some months and in leap years Please confirm the correct setting The ENB bit in RDAYAR is initialized by a power on reset The remaining RDAYAR fields are not initialized by a power on reset or manual reset or in stan...

Page 399: ...with ENB bits set to 1 and if each of those coincide an RTC alarm interrupt is generated The range of month can be set 01 to 12 decimal Errant operation will result if any other value is set The ENB bit in RMONAR is initialized by a power on reset The remaining RMONAR fields are not initialized by a power on reset or manual reset or in standby mode Bit Bit Name Initial Value R W Description 7 ENB ...

Page 400: ...hand This register is not initialized in standby mode Bit Bit Name Initial Value R W Description 7 CF R W Carry Flag Status flag that indicates that a carry has occurred CF is set to 1 when a count up to R64CNT or RSECCNT occurs A count register value read at this time cannot be guaranteed another read is required 0 No count up of R64CNT or RSECCNT Clearing condition When 0 is written to CF 1 Coun...

Page 401: ...1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 AF 0 R W Alarm Flag The AF flag is set to 1 when the alarm time set in an alarm register only registers with ENB bit set to 1 matches the clock and calendar time This flag is cleared to 0 when 0 is written but holds the previous value when 1 is to be written 0 Clock calendar and alarm register have not matched ...

Page 402: ...terrupts not generated with the period designated by the PES bits Clearing condition When 0 is written to PEF 1 Interrupts generated with the period designated by the PES bits Setting condition When 1 is written to PEF 6 5 4 PES2 PES1 PES0 0 0 0 R W R W R W Periodic Interrupt Flags These bits specify the periodic interrupt 000 No periodic interrupts generated 001 Periodic interrupt generated every...

Page 403: ...rcuit will be simultaneously reset This bit always reads 0 0 Runs normally 1 30 second adjustment 1 RESET 0 R W Reset When 1 is written initializes the divider circuit RTC prescaler and R64CNT This bit always reads 0 0 Runs normally 1 Divider circuit is reset 0 START 1 R W Start Bit Halts and restarts the counter clock 0 Second minute hour day week month year counter halts 1 Second minute hour day...

Page 404: ...irm that the change has taken effect by reading the R64CNT value wait at least 107 µs after setting the RESET bit to 1 before reading the R64CNT counter Note that the divider circuit RTC prescaler is also initialized when the RESET bit is set to 1 2 Incrementing RSECCNT by Initializing R64CNT Either method a or method b below may be used a After setting the RESET bit to 1 and confirming that R64CN...

Page 405: ...r Yes No Confirm R64CNT is not 0 Stop clock Reset divider circuit Order is irrelevant Figure 13 2 a Setting the Time Write 1 to RESET and 0 to START in the RCR2 register Order is irrelevant Write to RCR2 Set seconds minutes hour day day of the week month and year Confirm R64CNT is 0 Yes No Confirm R64CNT is not 0 Stop clock Reset divider circuit Start clock Reset divider circuit Write 1 to RESET a...

Page 406: ...mming simple method a should normally be used Write 0 to CF in RCR1 Note Set AF in RCR1 to 1 so that alarm flag is not cleared Write 0 to CIE in RCR1 Read RCR1 and check CF Write 0 to CIE in RCR1 Carry flag 1 No Yes Clear the carry flag Disable the carry interrupt Read counter register Write 1 to CIE in RCR1 and write 0 to CF in RCR1 Note Set AF in RCR1 to 1 so that alarm flag is not cleared Inter...

Page 407: ...aced to 0 When the clock and alarm times match 1 is set in the AF bit bit 0 in RCR1 Alarm detection can be checked by reading this bit but normally it is done by interrupt If 1 is placed in the AIE bit bit 3 in RCR1 an interrupt is generated when an alarm occurs Disable interrupt to prevent errorneous interruption AIE bit in RCR1 is cleared Then write 1 Clock running Set alarm time Set whether to ...

Page 408: ...Built in resistance value Rf Typ value 10 MΩ RD Typ value 400 kΩ 3 Cin and Cout values include floating capacitance due to the wiring Take care when using a ground plane 4 The crystal oscillation settling time depends on the mounted circuit constants floating capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capa...

Page 409: ...riodic interrupt function is shown in figure 13 6 A periodic interrupt can be generated periodically at the interval set by the periodic interrupt enable flag PES0 to PES2 in RCR2 When the time set by the PES0 to PES2 has elapsed the PEF is set to 1 The PEF is cleared to 0 upon periodic interrupt generation when the periodic interrupt enable flag PES0 to PES2 is set Periodic interrupt generation c...

Page 410: ... the setting to affect the value read from the second counter RSECCNT If the result of 30 second adjustment by the ADJ bit in RCR2 needs to be reflected in the value read from the second counter be sure to read from the second counter only after at least 91 6 µs approximately has passed after the ADJ bit has been set to 1 Note that 30 second adjustment is actually performed for the second counter ...

Page 411: ...p that employs a standard asynchronous serial system It can also communicate with two or more other processors using the multiprocessor communication function There are 12 selectable serial data communication formats Data length Seven or eight bits Stop bit length One or two bits Parity Even odd or none Multiprocessor bit 1 or 0 Receive error detection Parity overrun and framing errors Break detec...

Page 412: ...lting the clock supply for the saving power Figure 14 1 shows a SCI block diagram RxD0 TxD0 SCK0 SCI SCBRR SCSSR SCSCR SCTDR SCTSR SCRDR SCRSR SCSMR SCPDR SCPCR Parity generation Parity check Clock External clock Module data bus Internal data bus Pφ Pφ 4 Pφ 16 Pφ 64 TXI TEI RXI ERI Bus interface Baud rate generator Transmit receive control SCRSR SCRDR SCTSR SCTDR SCSMR Receive shift register Recei...

Page 413: ...erial clock output Serial clock input R SCP1MD0 PCRW Reset C Q Q D R SCP1MD1 PCRW Reset C Q D R SCP1DT1 PDRW Reset SCPT 1 SCK0 C D PDRR Note When reading the SCK0 pin clear the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0 and set the SCP1MD1 bit in SCPCR to 1 Legend PDRW SCPDR write PDRR SCPDR read PCRW SCPCR write Figure 14 2 SCPT 1 SCK0 Pin ...

Page 414: ...nsmission output Q R SCP0DT1 PDRW Reset SCPT 0 TxD0 C D R SCP0MD0 PCRW Reset C Q D R SCP0MD1 PCRW Reset C Q D Legend PCRW PDRW SCPCR write SCPDR write Figure 14 3 SCPT 0 TxD0 Pin SCI Serial receive data Internal data bus PDRR SCPT 0 RxD0 Note When reading the RxD0 pin set the RE bit in SCSCR to 1 Legend PDRR PDR read Figure 14 4 SCPT 0 RxD0 Pin ...

Page 415: ...and the C A bit in SCSMR Break state transmission and detection can be performed by means of the SCI s SCPDR 14 3 Register Description The SCI has the registers listed below These registers select the communication mode asynchronous or clock synchronous specify the data format and bit rate and control the transmitter and receiver sections SCI has the registers listed below Refer to section 23 List...

Page 416: ...ed to H 00 by a reset or in standby or module standby modes 14 3 3 Transmit Shift Register SCTSR The transmit shift register SCTSR transmits serial data The SCI loads transmit data from the SCTDR into the SCTSR then transmits the data serially to the TxD0 pin LSB bit 0 first After transmitting one byte data the SCI automatically loads the next transmit data from the SCTDR into the SCTSR and starts...

Page 417: ...seven bit or eight bit data length in the asynchronous mode In the clock synchronous mode the data length is always eight bits regardless of the CHR setting 0 Eight bit data 1 Seven bit data Note When seven bit data is selected the MSB bit 7 in the SCTDR is not transmitted 5 PE 0 R W Parity Enable Selects whether to add a parity bit to the transmit data or to check the parity of receive data in as...

Page 418: ...ombined 1 Odd parity Note If odd parity is selected the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined 3 STOP 0 R W Stop Bit Length Selects one or two bits as the stop bit length in the asynchronous mode This setting is used on...

Page 419: ...in the clock synchronous mode For the multiprocessor communication function see section 14 4 2 Multiprocessor Communication 0 Multiprocessor function disabled 1 Multiprocessor format selected 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0 These bits select the internal clock source of the on chip baud rate generator Four clock sources are available Pφ Pφ 4 Pφ 16 and Pφ 64 For further information o...

Page 420: ...est TXI is disabled Note The TXI interrupt request can be cleared by reading TDRE after it has been set to 1 then clearing TDRE to 0 or by clearing TIE to 0 1 Transmit data empty interrupt request TXI is enabled 6 RIE 0 R W Receive Interrupt Enable Enables or disables the receive data full interrupt RXI request when the serial receive data is transferred from SCRSR to SCRDR and the receive data re...

Page 421: ...eared to 0 after writing of transmit data into the SCTDR Specify the transmit format to the SCSMR before setting TE to 1 4 RE 0 R W Receive Enable Enables or disables the SCI serial receiver 0 Reception disabled Note Clearing RE to 0 does not affect the receive flags RDRF FER PER ORER These flags retain their previous values 1 Reception enabled Note Serial reception starts when a start bit is dete...

Page 422: ... in the serial status register SCSSR are disabled until data with a multiprocessor bit of 1 is received Note The SCI does not transfer receive data from the SCRSR to the SCRDR does not detect receive errors and does not set the RDRF FER and ORER flags in the serial status register SCSSR When it receives data that includes MPB 1 the SCSSR s MPB flag is set to 1 and the SCI automatically clears MPIE...

Page 423: ...selecting the SCI operating mode in the serial mode register SCSMR set CKE1 and CKE0 For further details on selection of the SCI clock source see table 14 9 Asynchronous mode 00 Internal clock SCK0 pin is used for input pin input signal is ignored 1 01 Internal clock SCK0 pin is used for clock output 2 01 External clock SCK0 pin is used for clock input 3 11 External clock SCK0 pin is used for cloc...

Page 424: ...ains valid transmit data Clearing condition TDRE is read as 1 then written to with 0 1 SCTDR does not contain valid transmit data Setting conditions 1 The chip is reset or enters standby mode 2 TE bit in the serial control register SCSCR is 0 3 SCTDR contents are loaded into SCTSR so new data can be written in SCTDR 6 RDRF 0 R W Receive Data Register Full Indicates that SCRDR contains received dat...

Page 425: ...s standby mode 2 ORER is read as 1 then written to with 0 1 A receive overrun error occurred 2 Setting condition Reception of the next serial data has ended when RDRF is set to 1 Notes 1 Clearing the RE bit to 0 in the serial control register does not affect the ORER bit which retains its previous value 2 SCRDR continues to hold the data received before the overrun error so subsequent receive data...

Page 426: ...Note Clearing the RE bit to 0 in the serial control register does not affect the FER bit which retains its previous value 1 A receive framing error occurred Setting condition When the SCI has completed receiving the stop bit at the end of receive data is checked and found to be 0 Note When the stop bit length is two bits only the first bit is checked The second stop bit is not checked When a frami...

Page 427: ...ber of 1s in receive data including the parity bit does not match the even or odd parity setting of the parity mode bit O E in SCSMR When a parity error occurs the SCI transfers the receive data into the SCRDR but does not set RDRF Serial receiving cannot continue while PER is set to 1 In the clock synchronous mode serial transmitting also cannot continue 2 TEND 1 R Transmit End Indicates that whe...

Page 428: ...ed the MPB retains its previous value 1 Multiprocessor bit value in receive data is 1 Note Clearing the RE bit to 0 in the maltiprocessor format which retain its previous value 0 MPBT 0 R W Multiprocessor Bit Transfer Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode The MPBT setting is ignored in th...

Page 429: ...nly 0 should be written here 11 10 9 8 7 6 5 4 SCP5MD1 SCP5MD0 SCP4MD1 SCP4MD0 SCP3MD1 SCP3MD0 SCP2MD1 SCP2MD0 1 0 1 0 1 0 0 0 R W R W R W R W R W R W R W R W See section 17 1 10 SC Port Control Register SCPCR 3 2 SCP1MD1 SCP1MD0 1 0 R W R W Serial clock port I O These bits specify serial port SCK0 pin I O When the SCK0 pin is actually used as a port I O pin clear the C A bit of SCSMR and bits CKE...

Page 430: ...W Serial clock port data Specifies the serial port SCK0 pin I O data Input or output is specified by the SCP1MD0 and SCP1MD1 bits In output mode the value of the SCP1DT bit is output to the SCK0 pin 0 I O data is low 0 1 I O data is high 1 0 SCP0DT 0 R W Serial port break data Specifies the serial port RxD0 pin input data and TxD0 pin output data The TxD0 pin output condition is specified by the S...

Page 431: ...ch channel has independent baud rate generator control so different values can be set in two channels The SCBRR setting is calculated as follows Asynchronous mode N Pφ 64 22n 1 B 106 1 Clock synchronous mode N Pφ 8 22n 1 B 106 1 B Bit rate bit s N SCBRR setting for baud rate generator 0 N 255 Pφ Operating frequency for peripheral modules MHz n Baud rate generator clock source n 0 1 2 3 for the clo...

Page 432: ...27 0 00 1200 0 191 0 00 0 207 0 16 0 255 0 00 2400 0 95 0 00 0 103 0 16 0 127 0 00 4800 0 47 0 00 0 51 0 16 0 63 0 00 9600 0 23 0 00 0 25 0 16 0 31 0 00 19200 0 11 0 00 0 12 0 16 0 15 0 00 31250 0 6 5 33 0 7 0 00 0 9 1 70 38400 0 5 0 00 0 6 6 99 0 7 0 00 Pφ φ φ φ MHz 10 12 12 288 Bit Rate bits s n N Error n N Error n N Error 110 2 177 0 25 2 212 0 03 2 217 0 08 150 2 129 0 16 2 155 0 16 2 159 0 00...

Page 433: ... 0 00 0 64 0 16 19200 0 23 0 00 0 25 0 16 0 31 0 00 0 32 1 36 31250 0 14 1 70 0 15 0 00 0 19 1 70 0 19 0 00 38400 0 11 0 00 0 12 0 16 0 15 0 00 0 15 1 73 Pφ φ φ φ MHz 24 24 576 28 7 30 Bit Rate bits s n N Error n N Error n N Error n N Error 110 3 106 0 44 3 108 0 08 3 126 0 31 3 132 0 13 150 3 77 0 16 3 79 0 00 3 92 0 46 3 97 0 35 300 2 155 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 2 79 ...

Page 434: ...y 29 2006 page 386 of 698 REJ09B0146 0500 Pφ φ φ φ MHz 33 34 Bit Rate bits s n N Error 110 3 147 0 00 150 3 108 0 43 300 2 216 0 03 600 2 108 0 43 1200 1 216 0 03 2400 1 108 0 43 4800 0 216 0 03 9600 0 108 0 43 19200 0 53 0 49 31250 0 32 1 03 38400 0 26 0 49 ...

Page 435: ...24 3 249 500 2 249 3 124 3 223 3 233 1k 2 124 2 249 3 111 3 116 2 5k 1 199 2 99 2 178 2 187 5k 1 99 1 199 2 89 2 93 10k 0 199 1 99 1 178 1 187 25k 0 79 0 159 1 71 1 74 50k 0 39 0 79 0 143 0 149 100k 0 19 0 39 0 71 0 74 250k 0 7 0 15 0 29 500k 0 3 0 7 0 14 1M 0 1 0 3 2M 0 0 0 1 Note Settings with an error of 1 or less are recommended Blank No setting possible Setting possible but error occurs Conti...

Page 436: ... is used Tables 14 6 and 14 7 list the maximum rates for external clock input Table 14 5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ φ φ φ MHz Maximum Bit Rate bits s n N 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 750000 0 0 24 576 768000 0 0 28 7 896875 0 0 30 937500 0 0 ...

Page 437: ...000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 0000 312500 24 6 0000 375000 24 576 6 1440 384000 28 7 7 1750 448436 30 7 5000 468750 Table 14 7 Maximum Bit Rates during External Clock Input Clock Synchronous Mode Pφ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bits s 8 1 3333 1333333 3 16 2 6667 2666666 7 24 4 0000 4000000 ...

Page 438: ...cter length In receiving it is possible to detect framing errors parity errors overrun errors and breaks An internal or external clock can be selected as the SCI clock source When an internal clock is selected the SCI operates on the clock of the on chip baud rate generator and can output a serial clock signal with a frequency matching the bit rate When an external clock is selected the external c...

Page 439: ...t set 2 bits 0 1 bit 0 1 8 bit 2 bits 0 1 bit Asynchronous multiprocessor format 0 1 1 1 7 bit Set 2 bits Clock synchronous 1 8 bit Not set Not set None Legend Don t care Table 14 9 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR SCSCR Settings SCI Transmit Receive Clock Mode Bit 7 C A A A A Bit 1 CKE1 Bit 0 CKE0 Clock Source SCK Pin Function 0 SCI does not use the SCK pin 0 1 Intern...

Page 440: ...serial communication the communication line is normally held in the mark high state The SCI monitors the line and starts serial communication when the line goes to the space low state indicating a start bit One serial character consists of a start bit low data LSB first parity bit high or low and stop bit high in that order When receiving in the asynchronous mode the SCI synchronizes on the fallin...

Page 441: ...ve Format and Frame Length CHR PE MP STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 START 8 Bit data STOP 0 0 0 1 START 8 Bit data STOP STOP 0 1 0 0 START 8 Bit data P STOP 0 1 0 1 START 8 Bit data P STOP STOP 1 0 0 0 START 7 Bit data STOP 1 0 0 1 START 7 Bit data STOP STOP 1 1 0 0 START 7 Bit data P STOP 1 1 0 1 START 7 Bit data P STOP STOP 0 1 0 START 8 Bit data MPB STOP 0 1 1 START 8 Bit data MPB STOP...

Page 442: ...KE1 and CKE0 in the SCSCR table 14 9 When an external clock is input on the SCK0 pin it must have a frequency equal to 16 times the desired bit rate When the SCI operates on an internal clock it can output a clock signal on the SCK0 pin The frequency of this output clock is equal to the bit rate The phase is aligned as in figure 14 6 so that the rising edge of the clock occurs at the center of eac...

Page 443: ...ed Figure 14 7 is a sample flowchart for initializing the SCI Initialize Clear TE and RE bits in SCSCR to 0 Select transmit receive format in SCSMR Set value to SCBRR Set CKE1 and CKE0 bits in SCSCR TE and RE bits are 0 Wait Set TE and RE bits in SCSCR to 1 and set RIE TEIE and MPIE bits Has a 1 bit interval elapsed End No Yes Select the clock source in the SCSCR Leave RIE TIE TEIE MPIE TE and RE ...

Page 444: ...0 End transmission Yes Read TDRE bit in SCSSR No No Yes No No Start transmission Set SCPDR and SCPCR SCI status check and transmit data write Read the serial status register SCSSR check that the TDRE bit is 1 then write transmit data in the SCTDR and clear TDRE to 0 To continue transmitting serial data Read the TDRE bit to check whether it is safe to write if it reads 1 if so write data in SCTDR t...

Page 445: ...utput b Transmit data Seven or eight bits of data are output LSB first c Parity bit or multiprocessor bit One parity bit even or odd parity or one multiprocessor bit is output Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit One or two 1 bits stop bits are output e Marking Output of 1 bits continues until the start bit of the next transmit da...

Page 446: ...ta Stop bit Start bit Data Stop bit Idling marking TXI interrupt request generated Example 8 bit data with parity and one stop bit TEI interrupt request generated Writes data to SCTDR with the TXI interrupt processing routine and clear TDRE bit to 0 1 frame D 0 D 1 D 7 D 0 D 1 D 7 0 1 TXI interrupt request generated Figure 14 9 SCI Transmit Operation in Asynchronous Mode ...

Page 447: ...ar RDRF bit in SCSSR to 0 Receive error processing and break detection If a receive error occurs read the ORER PER and FER bits of the SCSSR to identify the error After executing the necessary error processing clear ORER PER and FER all to 0 Receiving cannot resume if ORER PER or FER remain set to 1 When a framing error occurs the RxD0 pin can be read to detect the break state SCI status check and...

Page 448: ...9B0146 0500 Error processing ORER 1 Overrun error processing FER 1 Yes Break No Framing error processing PER 1 Yes Parity error processing Clear ORER PER and FER bits in SCSSR to 0 End No No No Yes Yes Clear RE bit in SCSCR to 0 Figure 14 10 Sample Flowchart for Receiving Serial Data cont ...

Page 449: ...ores the received data in the SCRDR If one of the checks fails receive error the SCI operates as indicated in table 14 11 Note When a receive error flag is set further receiving is disabled The RDRF bit is not set to 1 Be sure to clear the error flags 4 After setting RDRF to 1 if the receive data full interrupt enable bit RIE is set to 1 in the SCSCR the SCI requests a receive data full interrupt ...

Page 450: ...ormat In multiprocessor communication each receiving processor is addressed by a unique ID A serial communication cycle consists of an ID sending cycle that identifies the receiving processor and a data sending cycle The multiprocessor bit distinguishes ID sending cycles from data sending cycles The transmitting processor starts by sending the ID of the receiving processor with which it wants to c...

Page 451: ... ID transmit cycle specifies receiving station Serial data Transmitting station Receiving station D Data transmit cycle data transmission to receiving station specified by ID MPB Multiprocessor bit Example Sending data H AA to receiving processor A Figure 14 12 Communication Among Processors Using Multiprocessor Format Communication Formats Four formats are available Parity bit settings are ignore...

Page 452: ...SCSSR Clear TDRE bit to 0 No No Yes No No Start transmission Clear TE bit SCSCR to 0 SCI status check and transmit data write Read the SCSSR check that the TDRE bit is 1 then write transmit data in the SCTDR Also set MPBT multiprocessor bit transfer to 0 or 1 in SCSSR Finally clear TDRE to 0 To continue transmitting serial data Read the TDRE bit to check whether it is safe to write if it reads 1 i...

Page 453: ...owing order from the TxD0 pin a Start bit One 0 bit is output b Transmit data Seven or eight bits are output LSB first c Multiprocessor bit One multiprocessor bit MPBT value is output d Stop bit One or two 1 bits stop bits are output e Marking Output of 1 bits continues until the start bit of the next transmit data 3 The SCI checks the TDRE bit when it outputs the stop bit If TDRE is 0 the SCI loa...

Page 454: ...pt request generated Writes data to TDR with the TXI interrupt pro cessing routine and clears TDRE bit to 0 Example 8 bit data with multiprocessor bit and one stop bit 1 frame 0 1 1 1 0 1 0 1 Multi processor bit Serial data Start bit Data Stop bit Start bit Data Stop bit Idling marking D 0 D 1 D 7 D 0 D 1 D 7 0 1 Multi processor bit Figure 14 14 SCI Multiprocessor Transmit Operation ...

Page 455: ...reception No Yes Read receive data in SCRDR ID receive cycle Set the MPIE bit in SCSCR to 1 SCI status check and compare to ID reception Read the SCSSR check that RDRF is set to 1 then read data from the SCRDR and compare with the processor s own ID If the ID does not match the receive data set MPIE to 1 again and clear RDRF to 0 If the ID matches the receive data clear RDRF to 0 SCI status check ...

Page 456: ...8 of 698 REJ09B0146 0500 ORER 1 Break Yes Framing error processing Yes Error processing Overrun error processing Yes FER 1 Clear ORER and FER bits in SCSSR to 0 End No No No Clear RE bit in SCSCR to 0 Figure 14 15 Sample Flowchart for Receiving Multiprocessor Serial Data cont ...

Page 457: ...RDR state is maintained 0 1 1 1 1 0 1 Stop bit MPB Serial data Start bit Data ID1 Data data 1 Start bit MPB Stop bit Idling marking D0 D1 D7 D0 D1 D7 0 RDRF MPIE RDR value b Own ID matches data ID1 ID2 Data2 0 1 1 1 1 0 1 MPB MPB Serial data Start bit Data ID2 Data Data 2 Stop bit Start bit Stop bit Idling marking D0 D1 D7 D0 D1 D7 0 RXI interrupt request multiprocessor interrupt generated MPIE 0 ...

Page 458: ...Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 LSB MSB Synchronization clock Serial data Don t care Don t care One unit of communication data character or frame Note High except in continuous transmitting or receiving Figure 14 17 Data Format in Clock Synchronous Communication In clock synchronous serial communication each data bit is output on the communication line from one falling edge of the serial clock...

Page 459: ...mode or communication format the software must clear the TE and RE bits to 0 in SCSCR then initialize the SCI Clearing TE to 0 sets TDRE to 1 and initializes the SCTSR Clearing RE to 0 however does not initialize the RDRF PER FER and ORER flags and SCRDR which retain their previous contents Figure 14 18 is a sample flowchart for initializing the SCI Initialize Clear TE and RE bits in SCSCR to 0 Ha...

Page 460: ...All data transmitted Yes No End transmission TDRE 1 Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 Yes No Read TEND bit in SCSSR TEND 1 Yes No Clear TE bit in SCSCR to 0 SCI status check and transmit data write Read the serial status register SCSSR check that the TDRE bit is 1 then write transmit data in the transmit data register SCTDR and clear TDRE to 0 To continue transmitti...

Page 461: ...ock Data are output from the TxD0 pin in order from the LSB bit 0 to the MSB bit 7 3 The SCI checks the TDRE bit when it outputs the MSB bit 7 If TDRE is 0 the SCI loads data from the SCTDR into the SCTSR then begins serial transmission of the next frame If TDRE is 1 the SCI sets the TEND bit in the SCSSR to 1 transmits the MSB then holds the transmit data pin TxD0 in the MSB state If the TEIE in ...

Page 462: ...bit in SCSCR to 0 No No Read RDRF bit in SCSSR Yes Error processing Read receive data in SCRDR and clear RDRF bit in SCSSR to 0 Start reception 1 Receive error processing If a receive error occurs read the ORER bit in SCSSR to identify the error After executing the necessary error processing clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 2 SCI status check and receiv...

Page 463: ...table 14 11 This state prevents further transmission or reception While receiving the RDRF bit is not set to 1 Be sure to clear the error flag 3 After setting RDRF to 1 if the RIE is set to 1 in the SCSCR the SCI requests a receive data full interrupt RXI If the ORER bit is set to 1 and the RIE in the SCSCR is also set to 1 the SCI requests a receive error interrupt ERI Figure 14 22 shows an examp...

Page 464: ...n the SCTDR and clear TDRE to 0 The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1 Receive error processing If a receive error occurs read the ORER bit in SCSSR to identify the error After executing the necessary error processing clear ORER to 0 Transmitting receiving cannot resume if ORER remains set to 1 SCI status check and receive data read Read the SCSSR c...

Page 465: ... when the TDRE bit in the SCSSR is set to 1 RXI is requested when the RDRF bit in the SCSSR is set to 1 ERI is requested when the ORER PER or FER bit in the SCSSR is set to 1 TEI is requested when the TEND bit in the SCSSR is set to 1 Where the TXI interrupt indicates that transmit data writing is enabled the TEI interrupt indicates that the transmit operation is complete Table 14 12 SCI Interrupt...

Page 466: ... Receive Data SCSSR Status Flags Receive Error Status RDRF ORER FER PER Receive Data Transfer SCRSR SCRDR Overrun error 1 1 0 0 X Framing error 0 0 1 0 O Parity error 0 0 0 1 O Overrun error framing error 1 1 1 0 X Overrun error parity error 1 1 0 1 X Framing error parity error 0 0 1 1 O Overrun error framing error parity error 1 1 1 1 X Legend X Receive data is not transferred from SCRSR to SCRDR...

Page 467: ...ation Clock Synchronous Mode Only When a receive error flag ORER PER or FER is set to 1 the SCI will not start transmitting even if TDRE is set to 1 Be sure to clear the receive error flags to 0 before starting to transmit Note that clearing RE to 0 does not clear the receive error flags Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode In the asynchronous mode the SCI opera...

Page 468: ...n 2 M 0 5 1 2 16 100 46 875 This is a theoretical value A reasonable margin to allow in system designs is 20 to 30 Cautions for Clock Synchronous External Clock Mode Set TE RE 1 only when the external clock SCK0 is 1 Do not set TE RE 1 until at least four clocks after the external clock SCK0 has changed from 0 to 1 When receiving RDRF is 1 when RE is set to zero 2 5 3 5 clocks after the rising edg...

Page 469: ...rdinary serial communication interface and the smart card interface Figure 15 1 is the block diagram of the smart card interface 15 1 Feature The smart card interface has the following features Asynchronous mode Data length Eight bits Parity bit generation and check Receive mode error signal detection parity error Transmit mode error signal detection and automatic re transmission of data Supports ...

Page 470: ...bus Internal data bus Pφ Pφ 4 Pφ 16 Pφ 64 TXI RXI ERI Bus interface Baud rate generator Transmit receive control SCSCMR SCRSR SCRDR SCTSR SCTDR Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register SCSMR SCSCR SCSSR SCBRR Serial mode register Serial control register Serial status register Bit rate register Legend Figure 15 1 Smart Card...

Page 471: ...nsmit data output 15 3 Register Description The smart card interface has the following registers The SCSMR SCBRR SCSCR SCTDR and SCRDR registers are the same as those of the SCI So see the register description in section 14 Serial Communication Interface Refer to see section 23 List of Registers for more details of the addresses and access sizes Smart card mode register SCSCMR Serial status regist...

Page 472: ...ive data is stored in SCRDR as MSB first 2 SINV 0 R W Smart Card Data Inversion Specifies whether to invert the logic level of the data This function is used in combination with bit 3 for transmitting and receiving with an inverse convention card SINV does not affect the logic level of the parity bit See section 15 4 4 Register Settings for information on how parity is set 0 Contents of SCTDR are ...

Page 473: ... as in the ordinary SCI See section 14 Serial Communication Interface SCI for more information 4 ERS 0 R W Error Signal Status In the smart card interface mode bit 4 indicates the state of the error signal returned from the receiving side during transmission The smart card interface cannot detect framing errors 0 Receiving ended normally with no error signal Clearing conditions 1 The chip is reset...

Page 474: ...e changed as follows 0 Transmission is in progress Clearing condition TDRE is read as 1 then written to with 0 1 End of transmission Setting conditions 1 The chip is reset or enters standby mode 2 TE bit in SCSCR is 0 and the FER ERS bit is also 0 3 C A bit in SCSMR is 0 and TDRE 1 and FER ERS 0 normal transmission 2 5 etu after a one byte serial character is transmitted 4 C A bit in SCSMR is 1 an...

Page 475: ...top type asynchronous communication functions are supported no synchronous communication functions are available 15 4 2 Pin Connections Figure 15 2 shows the pin connection diagram for the smart card interface During communication with an IC card transmission and reception are both carried out over the same data transfer line so connect the TxDφ and RxDφ pins on the chip Pull up the data transfer ...

Page 476: ...e parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re transmitted During transmission if an error signal is sampled the same data is re transmitted Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp With no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE With parity error Transmitting station output...

Page 477: ...it receives an error signal If it does receive an error signal it returns to step 2 to re transmit the erroneous data 15 4 4 Register Settings Table 15 2 shows the bit map of the registers that the smart card interface uses Bits shown as 1 or 0 must be set to the indicated value The settings for the other bits are described below Table 15 2 Register Settings for the Smart Card Interface Register A...

Page 478: ...f IC cards direct convention and inverse convention and their start characters In the direct convention type the logical 1 level is state Z the logical 0 level is state A and communication is LSB first The start character data is H 3B The parity bit is even as specified in the smart card standards and thus 1 In the inverse convention type the logical 1 level is state A the logical 0 level is state...

Page 479: ...n 1 N 1 P φ Where N Value set in SCBRR 0 N 255 B Bit rate bit s Pφ Peripheral module operating frequency MHz n 0 to 3 table 15 3 Table 15 3 Relationship of n to CKS1 and CKS0 n CKS1 CKS0 0 0 0 1 0 1 2 1 0 3 1 1 Table 15 4 Examples of Bit Rate B Bit s for SCBRR Settings n 0 Pφ φ φ φ MHz N 7 1424 10 00 10 7136 13 00 14 2848 16 00 18 00 0 9600 0 13440 9 14400 0 17473 1 19200 0 21505 4 24193 5 1 4800 ...

Page 480: ...le 15 6 Maximum Bit Rates for Frequencies Smart Card Interface Mode Pφ φ φ φ MHz Maximum Bit Rate Bit s N n 7 1424 9600 0 0 10 00 13441 0 0 10 7136 14400 0 0 13 00 17473 0 0 14 2848 19200 0 0 16 00 21505 0 0 18 00 24194 0 0 The bit rate error is found as follows Error 106 1 100 1488 22n 1 B N 1 Pφ Table 15 5 shows example settings of SCBRR and table 15 6 shows the maximum bit rate for each frequen...

Page 481: ...ending or receiving data Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode Figure 15 5 shows an example of initialization process flowchart 1 Clear TE and RE in SCSCR to 0 2 Clear error flags FER ERS PER and ORER to 0 in SCSSR 3 Set the C A bit parity bit O E bit and baud rate generator select bits CKS1 and CKS0 bits in SCSMR At ...

Page 482: ...alization Flowchart Example Serial Data Transmission The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission An example of transmission processing flowchart is shown in figure 15 6 1 Initialize the smart card interface mode as described in Initialization above 2 Check that the FER ...

Page 483: ... be requested when the ERS flag is set to 1 when an error occurs in transmission See Interrupt Operation below for more information Start End transmission Start transmission Initialize Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 Clear TE bit in SCSCR to 0 Error processing FER ERS 0 TEND 1 Yes Yes Yes Yes No No All data transmitted No TEND 1 No Error processing FER ERS 0 Yes No F...

Page 484: ...rrupted When the RIE bit is set to 1 and interrupt requests are enabled a receive data full interrupt RXI will be requested when the RDRF flag is set to 1 at the end of the reception When an error occurs during reception and either the ORER or PER flag is set to 1 a communication error interrupt ERI will be requested See Interrupt Operation below for more information The received data will be tran...

Page 485: ...rupt TEI cannot be requested Set the TEND flag in SCSSR to 1 to request a TXI interrupt Set the RDRF flag in SCSSR to 1 to request an RXI interrupt Set the ORER PER or FER ERS flag in SCSSR to 1 to request an ERI interrupt table 15 8 Table 15 8 Smart Card Mode Operating State and Interrupt Sources Mode State Flag Mask Bit Interrupt Source Normal TEND TIE TXI Transmit mode Error FER ERS RIE ERI Nor...

Page 486: ...D1 Figure 15 8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation For smart card mode M 0 5 1 2N D 0 5 N L 0 5 F 1 F 100 Where M Receive margin N Ratio of bit rate to clock N 372 D Clock duty D 0 to 1 0 L Frame length L 10 F Absolute value of clock frequency deviation Using this equation the receive margin when F 0 and D 0 5 is as follows When D...

Page 487: ... is not set 4 When the received parity bit is checked and no error is found reception is considered to have been completed normally and the RDRF bit in SCSSR is automatically set to 1 If the RIE bit in SCSCR is enabled at this time an RXI interrupt is requested 5 When a normal frame is received the pin maintains a three state state when it transmits the error signal D0 Ds D2 D1 D4 D3 D6 D5 Dp DE D...

Page 488: ... 1 when the transmission of the frame that includes the retransmission is considered completed If the TIE bit in SCSCR is enabled at this time a TXI interrupt will be requested D0 Ds D2 D1 D4 D3 D6 D5 Dp DE D7 D0 Ds D2 D1 D4 D3 D6 D5 Dp DE D7 D0 Ds D2 D1 D4 D3 nth transfer frame TEND FER ERS Transfer from TDR to TRS Transfer from TDR to TRS Transfer from TDR to TRS 1 2 4 3 Retransmitted frame Tran...

Page 489: ...selectable serial data communication formats Data length Seven or eight bits Stop bit length One or two bits Parity Even odd or none Receive error detection Parity and framing errors Break detection Full duplex communication The transmitting and receiving sections are independent so the SCI can transmit and receive simultaneously Both sections use 16 stage FIFO buffering so high speed continuous d...

Page 490: ...DR Parity generation Parity check Clock External clock Module data bus Internal data bus Pφ Pφ 4 Pφ 16 Pφ 64 TXI TEI RXI BVRI Bus interface Baud rate generator Transmit receive control SCRSR2 SCFRDR2 SCTSR2 SCFTDR2 SCSMR2 SCSCR2 Receive shift register 2 Receive FIFO data register 2 Transmit shift register 2 Transmit FIFO data register 2 Serial mode register 2 Serial control register 2 SCSSR2 SCBRR...

Page 491: ...nput enable SCIF Serial clock output Serial clock input R SCP3MD0 PCRW Reset C Q Q D R SCP3MD1 PCRW Reset C Q D R SCP3DT1 PDRW Reset SCPT 3 SCK2 C D PDRR Note When reading the SCK2 pin clear the CKE1 and CKE0 bits in SCSCR to 0 and set the SCP3MD1 bit in SCSPR to 1 Legend PDRW SCPDR write PDRR SCPDR read PCRW SCPCR write Figure 16 2 SCPT 3 SCK2 Pin ...

Page 492: ...l transmission output Q R SCP2DT1 PDRW Reset SCPT 2 TxD2 C D R SCP2MD0 PCRW Reset C Q D R SCP2MD1 PCRW Reset C Q D Legend PCRW SCPCR write PDRW SCPDR write Figure 16 3 SCPT 2 TxD2 Pin SCIF Serial receive data Internal data bus PDRR SCPT 2 RxD2 Note When reading the RxD2 pin set the RE bit in SCSCR to 1 Legend PDRR SCPDR read Figure 16 4 SCPT 2 RxD2 Pin ...

Page 493: ... Clear to send pin CTS2 Input Clear to send 16 3 Register Description SCIF has the registers listed below These registers specify the data format and bit rate and control the transmitter and receiver sections Refer to section 23 List of Registers for more details of the addresses and access sizes Serial mode register 2 SCSMR2 Bit rate register 2 SCBRR2 Serial control register 2 SCSCR2 Transmit FIF...

Page 494: ...CFRFR2 the value is undefined When the received data in this register becomes full the subsequent serial data is lost 16 3 3 Transmit Shift Register 2 SCTSR2 The transmit shift register 2 SCTSR2 is an eight bit register that transmits serial data The CPU cannot read from or write to the SCTSR2 directly The SCI loads transmit data from the SCFTDR2 into the SCTSR2 then transmits the data serially fr...

Page 495: ... always read 0 The write value should always be 0 6 CHR 0 R W Character Length Selects seven bit or eight bit data in the asynchronous mode 0 Eight bit data 1 Seven bit data Note When seven bit data is selected the MSB bit 7 in SCFTPR2 is not transmitted 5 PE 0 R W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data 0 Parity bit not added or c...

Page 496: ...mbined 1 Odd parity Note If odd parity is selected the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined 3 STOP 0 R W Stop Bit Length Selects one or two bits as the stop bit length In receiving only the first stop bit is ...

Page 497: ...ronous mode enables disables interrupt requests and selects the transmit receive clock source The CPU can always read and write the SCSCR2 Bit Bit Name Initial Value R W Description 7 TIE 0 R W Transmit Interrupt Enable Enables or disables the transmit FIFO data empty interrupt TXI requested when the serial transmit data is transferred from the SCFTDR2 to SCTSR2 and the quantity of data in the SCF...

Page 498: ... or by clearing RIE to 0 At RDF read 1 from the RDF flag and clear it to 0 after reading the received data from SCFRDR2 until the quantity of received data becomes less than the specified number of the receive triggers 1 Receive data full interrupt RXI and receive error interrupt ERI requests are enabled 5 TE 0 R W Transmit Enable Enables or disables the SCIF serial transmitter 0 Transmitter disab...

Page 499: ...ck input The CKE0 setting is valid only when the SCI is operating with the internal clock CKE1 0 The CKE0 setting is ignored when an external clock source is selected CKE1 1 Always select the SCIF operating mode in the SCSMR2 before setting CKE1 and CKE0 For further details on selection of the SCIF clock source see table 16 7 in section 16 4 Operation 00 Internal clock SCK pin used for I O pin inp...

Page 500: ...E BRK OPER and DR These flags can be cleared to 0 only if they have first been read after being set to 1 Bits 3 FER and 2 PER are read only bits and cannot be written Bit Bit Name Initial Value R W Description 15 to 12 PER3 to PER0 All 0 R Number of parity errors These bits indicate the number of data items that contain a parity error in the receive data stored in the SCFRDR2 The number of parity ...

Page 501: ...he total number of 1 s in the received data and in the parity bit does not match the even odd parity specification specified by the O E bit of the SCSMR Setting conditions 1 The stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one data receive 2 2 The total number of 1 s in the received data and in the parity bit does not match the even odd pari...

Page 502: ...st bit of a serial character was transmitted the SCFTDR2 did not contain valid data so transmission has ended 0 Transmission is in progress Clearing condition Data is written to SCFTDR2 1 End of transmission Setting conditions 1 When the chip is reset or enters standby mode TE in the SCSCR2 is cleared to 0 2 SCFTDR2 contains no transmit data when the last bit of a one byte serial character is tran...

Page 503: ...of transmission triggers Clearing condition When data exceeding the specified number of transmission triggers is written to SCFTDR2 software reads TDFE after it has been set to 1 then writes 0 to TDFE 1 End of transmission Setting conditions 1 The chip is power on reset or enters standby mode 2 The quantity of transmission data in SCFTDR2 becomes less than the specified number of transmission trig...

Page 504: ...of the received data H 00 to SCFRDR2 stops after detection When the break ends and the receive signal becomes mark 1 the transfer of the received data resumes The received data of a frame in which a break signal is detected is transferred to SCFRDR2 After this however no received data is transferred until a break ends with the received signal being mark 1 and the next data is received 3 FER 0 R Fr...

Page 505: ... Indicates a parity error in the data read from the SCFRDR2 0 No parity error occurred in the data read from SCFRDR2 Clearing conditions 1 The chip is power on reset or enters standby mode 2 No parity error is present in the data read from SCFRDR2 1 A parity error occurred in the data read from SCFRDR2 Setting condition A parity error is present in the data read from SCFRDR2 ...

Page 506: ...2 When SCFRDR2 is read until the quantity of receive data in SCFRDR2 becomes less than the specified number of receive triggers software reads RDF after it has been set to 1 and then writes 0 to RDF 1 The quantity of receive data in SCFRDR2 is more than the specified number of receive triggers Setting condition The quantity of receive data which is greater than the specified number of receive trig...

Page 507: ... is in progress or no received data remains in SCFRDR2 after the receive ended normally Clearing conditions 1 The chip is power on reset or enters standby mode 2 DR is read as 1 then written to with 0 1 Next receive data is not received Setting condition SCFRDR2 stores the data which is less than the specified number of receive triggers and that next data is not yet received after 15 etu has elaps...

Page 508: ...et or in module standby or standby mode Each channel has independent baud rate generator control so different values can be set in two channels The SCBRR2 setting is calculated as follows Asynchronous mode N Pφ 64 2 2n 1 B 106 1 B Bit rate bit s N SCBRR2 setting for baud rate generator 0 N 255 Pφ Operating frequency for peripheral modules MHz n Baud rate generator clock source n 0 1 2 3 for the cl...

Page 509: ... 95 0 00 0 103 0 16 0 127 0 00 4800 0 47 0 00 0 51 0 16 0 63 0 00 9600 0 23 0 00 0 25 0 16 0 31 0 00 19200 0 11 0 00 0 12 0 16 0 15 0 00 31250 0 6 5 33 0 7 0 00 0 9 1 70 38400 0 5 0 00 0 6 6 99 0 1 0 00 Pφ φ φ φ MHz 10 12 12 288 Bit Rate bit s n N Error n N Error n N Error 110 2 177 0 25 1 212 0 03 2 217 0 08 150 2 129 0 16 1 155 0 16 2 159 0 00 300 2 64 0 16 1 77 0 16 2 79 0 00 600 1 129 0 16 0 1...

Page 510: ...5 0 00 2 103 0 16 2 127 0 00 2 129 0 16 600 1 191 0 00 1 207 0 16 1 255 0 00 1 64 0 16 1200 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 2400 0 191 0 00 0 207 0 16 0 255 0 00 0 64 0 16 4800 0 95 0 00 0 103 0 16 0 127 0 00 0 129 0 16 9600 0 47 0 00 0 51 0 16 0 63 0 00 0 64 0 16 19200 0 23 0 00 0 25 0 16 0 31 0 00 0 32 1 36 31250 0 14 1 70 0 15 0 00 0 19 1 70 0 19 0 00 38400 0 11 0 00 0 12 0 16 0 15 0...

Page 511: ...55 0 16 2 159 0 00 2 186 0 08 2 194 0 16 600 2 77 0 16 2 79 0 00 2 92 0 46 2 97 0 35 1200 1 155 0 16 1 159 0 00 1 186 0 08 1 194 0 16 2400 1 77 0 16 1 79 0 00 1 92 0 46 1 97 0 35 4800 0 155 0 16 0 159 0 00 0 186 0 08 0 194 1 36 9600 0 77 0 16 0 79 0 00 0 92 0 46 0 97 0 35 19200 0 38 0 16 0 39 0 00 0 46 0 61 0 48 0 35 31250 0 23 0 00 0 24 1 70 0 28 1 03 0 29 0 00 38400 0 19 2 34 0 19 0 00 0 22 1 55...

Page 512: ... 00 150 3 108 0 43 300 2 216 0 03 600 2 108 0 43 1200 1 216 0 03 2400 1 108 0 43 4800 0 216 0 03 9600 0 108 0 43 19200 0 53 0 49 31250 0 32 1 03 38400 26 0 49 11520 0 8 0 49 500000 0 1 4 19 Table 16 4 lists the maximum bit rates in the asynchronous mode when the baud rate generator is used Table 16 5 lists the maximum bit rates when an external clock input is used ...

Page 513: ...0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 6608 614400 0 0 20 625000 0 0 24 750000 0 0 24 576 768000 0 0 28 7 896875 0 0 30 937500 0 0 Table 16 5 Maximum Bit Rates during External Clock Input Asynchronous Mode Pφ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bit s 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 19 6608 4 9152 307200 20 5 ...

Page 514: ...SSR2 is set to 1 when the receiving data count has exceeded the following trigger number Trigger number of receive data 00 1 01 4 10 8 11 14 5 4 TTRG1 TTRG0 0 0 R W R W Trigger of the Number of Transmit FIFO Data Set the reference number of the send data empty The TDFE in SCSSR2 is set to 1 when the transmitting data count has fallen the following trigger number Trigger number of transmit data 00 ...

Page 515: ...eset operation Note The reset is executed in a hardware reset or the standby mode 1 RFRST 0 R W Receive FIFO Data Register Reset Cancels the receive data in the SCFRDR2 and resets the data to the empty state 0 Disables reset operation 1 Enables reset operation Note The reset is executed in a hardware reset or the standby mode 0 LOOP 0 R W Loop Back Test Internally connects the transmit output pin ...

Page 516: ...lower eight bits of this register indicate the number of receive data items stored in the SCFRDR2 The H 00 means no receive data and the H 10 means that the full of receive data are stored in the SCFRDR2 Bit Bit Name Initial Value R W Description 15 to 13 All 0 R Reserved These bits are always read as 0 12 to 8 T4 to T0 All 0 R Number of non transmitted data 7 to 5 All 0 R Reserved These bits are ...

Page 517: ...he preceding selections constitutes the communication format and character length In receiving it is possible to detect framing errors FER parity errors PER receive FIFO data full receive data ready and breaks In transmitting it is possible to detect transmit FIFO data empty The number of stored data for both the transmit and receive FIFO registers is displayed An internal or external clock can be...

Page 518: ... frequency 16 times the bit rate 16 4 1 Serial Operation Transmit Receive Formats Table 16 8 lists eight communication formats that can be selected The format is selected by settings in the SCSMR2 Table 16 8 Serial Communication Formats SCSMR2 Bits Serial Transmit Receive Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 START 8 Bit data STOP 0 0 1 START 8 Bit data STOP STOP 0 1...

Page 519: ...ialize the SCIF as follows When changing the communication format always clear the TE and RE bits to 0 before following the procedure given below Clearing TE to 0 initializes the transmit shift register SCTSR2 Clearing TE and RE to 0 however does not initialize the serial status register SCSSR2 transmit FIFO data register SCFTDR2 or receive FIFO data register SCFRDR2 which retain their previous co...

Page 520: ...t or RE bit in SCSR2 to 1 Also set the RIE and TIE bits Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used When transmitting the SCIF will go to the mark state when receiving it will go to the idle state waiting for a start bit Clear TE and RE bits in SCSCR2 to 0 Set TFRST and RFRST bits in SCFCR2 to 1 1 bit interval elapsed Set RTRG1 0 TTRG1 0 and MCE in SCFCR2 Clear TFRST and R...

Page 521: ...ag is set to 1 then write transmit data to the SCFTDR2 read 1 from the TDFE and TEND flags then clear these flags to 0 The number of transmit data bytes that can be written is 16 transmit trigger set number 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR2 and then clear the TDFE fla...

Page 522: ...TDFE flag is set If the TIE bit in SCSCR2 is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the TxD2 pin in the following order a Start bit One bit 0 is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not outpu...

Page 523: ...ure 16 7 Example of Transmit Operation Example with 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the CTS2 input value When CTS2 is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When CTS2 is set to 0 the next transmit data is output starting from the start bit Fig...

Page 524: ...n SCSSR2 to identify any error perform the appropriate error handling then clear the DR ER and BRK flags to 0 In the case of a framing error a break can also be detected by reading the value of the RxD2 pin 2 SCIF status check and receive data read Read the SCSSR2 and check that RDF 1 then read the receive data in SCFRDR2 read 1 from the RDF flag and then clear the RDF flag to 0 The transition of ...

Page 525: ... Read receive data in SCFRDR2 1 Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCSSR2 2 When a break signal is received receive data is not transferred to SCFRDR2 while the BRK flag is set However note that the last data in SCFRDR2 is H 00 and the break data in which a framing error occurred is stored Figur...

Page 526: ...cked b The SCIF checks whether receive data can be transferred from the receive shift register SCRSR2 to SCFRDR2 c Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If all the above checks are passed the receive data is stored in SCFRDR2 Note Reception is not suspended when a receive error occurs 4 If the RIE bit in SCSCR2 is set to 1 when the RDF or DR ...

Page 527: ...ata Stop bit Idling marking D 0 D 1 D 7 D 0 D 1 D 7 0 1 Figure 16 11 Example of SCIF Receive Operation Example with 8 Bit Data Parity One Stop Bit 5 When modem control is enabled the RTS2 signal is output when SCFRDR2 is full When RTS2 is 0 reception is possible When RTS2 is 1 this indicates that SCFRDR2 is full and reception is not possible Figure 16 12 shows an example of the operation when mode...

Page 528: ...st is generated The DMAC can be activated and data transfer performed when the RDF flag in SCSSR2 is set to 1 The RDF flag is cleared to 0 when SCFRDR2 is read until the quantity of receive data in SCFRDR2 becomes less than the specified number of receive triggers by the DMAC the RDF flag is read as 1 then 0 is written to the RDF flag When the ER flag in SCSSR2 is set to 1 an ERI interrupt request...

Page 529: ...lowing efficient continuous reception However if the number of data bytes in SCFRDR2 is greater than the trigger number the RDF flag will be set to 1 again even if it is cleared to 0 The RDF flag should therefore be cleared to 0 after being read as 1 after all the receive data has been read The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count regist...

Page 530: ...tes on a base clock with a frequency of 16 times the transfer rate In reception the SCIF synchronizes internally with the fall of the start bit which it samples on the base clock Receive data is latched at the rising edge of the eighth base clock pulse The timing is shown in figure 16 13 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 6 7 8 9 101112131415 0 1 2 3 4 5 Base clock Receive data RxD2 Sync...

Page 531: ...ay 29 2006 page 483 of 698 REJ09B0146 0500 From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 Equation 2 When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 This is a theoretical value A reasonable margin to allow in system designs is 20 to 30 ...

Page 532: ...Section 16 Serial Communication Interface with FIFO SCIF Rev 5 00 May 29 2006 page 484 of 698 REJ09B0146 0500 ...

Page 533: ...ns Table 17 1 List of Multiplexed Pins Port Port Function Related Module Other Function Related Module A PTA7 I O port D23 I O data bus A PTA6 I O port D22 I O data bus A PTA5 I O port D21 I O data bus A PTA4 I O port D20 I O data bus A PTA3 I O port D19 I O data bus A PTA2 I O port D18 I O data bus A PTA1 I O port D17 I O data bus A PTA0 I O port D16 I O data bus B PTB7 I O port D31 I O data bus ...

Page 534: ... O port WE2 output BSC DQMUL output BSC ICIORD output BSC C PTC0 I O port BS output BSC D PTD7 I O port CE2B output PCMCIA D PTD6 I O port CE2A output PCMCIA D PTD5 I O port IOIS16 input PCMCIA D PTD4 I O port CKE output BSC D PTD3 I O port CASU output BSC D PTD2 I O port CASL output BSC D PTD1 I O port RASU output BSC D PTD0 I O port RASL output BSC E PTE7 I O port IRQOUT output E PTE6 I O port T...

Page 535: ...put ADC G PTG4 input port AUDCK input AUD G PTG3 input port TRST input AUD H UDI G PTG2 input port TMS input H UDI G PTG1 input port TCK input H UDI G PTG0 input port TDI input H UDI H PTH6 I O port DREQ1 input DMAC H PTH5 I O port DREQ0 input DMAC H PTH4 I O port IRQ4 input INTC H PTH3 I O port IRQ3 input INTC IRL3 input INTC H PTH2 I O port IRQ2 input INTC IRL2 input INTC H PTH1 I O port IRQ1 in...

Page 536: ...put port TxD0 output SCI Initially selected function Note SCPT0 and SCPT2 have the same data register to be accessed although they have different input pins and output pins 17 1 Register Description The pin function controller has the following registers Refer to section 23 List of Registers for more details of the addresses and access sizes Port A control register PACR Port B control register PBC...

Page 537: ...11 Port input Pull up MOS off 13 12 PA6MD1 PA6MD0 0 0 R W R W PA6 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 11 10 PA5MD1 PA5MD0 0 0 R W R W PA5 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 9 8 PA4MD1 PA4MD0 0 0 R W R W PA4 Mode 00 Other function See table 17 1 01...

Page 538: ...1 PA0MD0 0 0 R W R W PA0 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 17 1 2 Port B Control Register PBCR Port B Control Register PBCR is a 16 bit read write register that selects the pin functions and the input pull up MOS control Bit Bit Name Initial Value R W Description 15 14 PB7MD1 PB7MD0 0 0 R W R W PB7 Mode 00 Other function...

Page 539: ...t input Pull up MOS off 7 6 PB3MD1 PB3MD0 0 0 R W R W PB3 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 5 4 PB2MD1 PB2MD0 0 0 R W R W PB2 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 3 2 PB1MD1 PB1MD0 0 0 R W R W PB1 Mode 00 Other function See table 17 1 01 Port outp...

Page 540: ...11 Port input Pull up MOS off 13 12 PC6MD1 PC6MD0 0 0 R W R W PC6 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 11 10 PC5MD1 PC5MD0 0 0 R W R W PC5 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 9 8 PC4MD1 PC4MD0 0 0 R W R W PC4 Mode 00 Other function See table 17 1 01...

Page 541: ...1 PC0MD0 0 0 R W R W PC0 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 17 1 4 Port D Control Register PDCR Port D Control Register PDCR is a 16 bit read write register that selects the pin functions and the input pull up MOS control Bit Bit Name Initial Value R W Description 15 14 PD7MD1 PD7MD0 0 0 R W R W PD7 Mode 00 Other function...

Page 542: ...t input Pull up MOS off 7 6 PD3MD1 PD3MD0 0 0 R W R W PD3 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 5 4 PD2MD1 PD2MD0 0 0 R W R W PD2 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 3 2 PD1MD1 PD1MD0 0 0 R W R W PD1 Mode 00 Other function See table 17 1 01 Port outp...

Page 543: ...11 Port input Pull up MOS off 13 12 PE6MD1 PE6MD0 0 0 R W R W PE6 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 11 10 PE5MD1 PE5MD0 0 0 R W R W PE5 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 9 8 PE4MD1 PE4MD0 0 0 R W R W PE4 Mode 00 Other function See table 17 1 01...

Page 544: ...nction See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 3 2 PE1MD1 PE1MD0 0 0 R W R W PE1 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 1 0 PE0MD1 PE0MD0 0 0 R W R W PE0 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off ...

Page 545: ...R Reserved When ASEMD0 0 this bit is always read as 0 and must only be written with 0 When ASEMD0 1 this bit is always read as 1 and must only be written with 1 14 0 R Reserved This bit is always read as 0 and must only be written with 0 13 12 PF6MD1 PF6MD0 1 0 0 R W R W PF6 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 11 10 PF5MD1...

Page 546: ...up MOS off 5 4 PF2MD1 PF2MD0 1 0 0 R W R W PF2 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 3 2 PF1MD1 PF1MD0 1 0 0 R W R W PF1 Mode 1 00 Other function See table 17 1 01 Reserved Setting prohibited 10 Port input Pull up MOS on 11 Port input Pull up MOS off 1 0 PF0MD1 PF0MD0 1 0 0 R W R W PF0 Mode 1 00 Other function See table 17 1...

Page 547: ...lways be 0 14 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 10 PG5MD1 PG5MD0 1 0 R W R W PG5 Mode 00 Other function See table 17 1 01 Reserved Setting prohibited 10 Port input Pull up MOS on 11 Port input Pull up MOS off 9 8 PG4MD1 PG4MD0 1 0 0 R W R W PG4 Mode 00 Other function See table 17 1 01 Reserved Setting prohibited 10 Port input Pull up MOS on 1...

Page 548: ... Pull up MOS off Note The bit number are out of sequence 17 1 8 Port H Control Register PHCR Port H Control Register PHCR is a 16 bit read write register that selects the pin functions and the input pull up MOS control Bit Bit Name Initial Value R W Description 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 PH6MD1 PH6MD0 0 0 R W R W PH6 Mode 00 Othe...

Page 549: ...nction See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 5 4 PH2MD1 PH2MD0 0 0 R W R W PH2 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 3 2 PH1MD1 PH1MD0 0 0 R W R W PH1 Mode 00 Other function See table 17 1 01 Port output 10 Port input Pull up MOS on 11 Port input Pull up MOS off 1 0 PH0MD1 P...

Page 550: ...e R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 6 PJ3MD1 PJ3MD0 0 0 R W R W PJ3 Mode 00 Other function See table 17 1 01 Reserved Setting prohibited 10 Port input 11 Port input 5 4 PJ2MD1 PJ2MD0 0 0 R W R W PJ2 Mode 00 Other function See table 17 1 01 Reserved Setting prohibited 10 Port input 11 Port input 3 2 PJ1MD1 PJ1MD0 0 0 R W R ...

Page 551: ...bit in SCSCR2 is set to 1 the SCPCR setting is ignored and the TxD2 function is selected When the RE bit in SCSCR2 is set to 1 the SCPCR setting is ignored and the RxD2 function is selected Bit Bit Name Initial Value R W Description 15 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 10 SCP5MD1 SCP5MD0 1 0 R W R W SCP5 Mode 00 Other function See table 17...

Page 552: ...tput 1 TxD2 11 General input SCPT 2 input pin Transmit data output 1 TxD2 Note There is no combination of simultaneous I O of SCPT 2 because one bit SCP2DT is accessed using two pins of TxD2 and RxD2 When the port input is set bit SCPnMD1 is set to 1 and when the TE bit in SCSCR is set to 1 the TxD1 pin is in the output state When the TE bit is cleared to 0 the TxD2 pin is in the high impedance st...

Page 553: ...e data input 0 RxD0 10 SCPT 0 input pin pull up input pin Transmit data output 0 TxD0 11 General input SCPT 0 input pin Transmit data output 0 TxD0 Note There is no combination of simultaneous I O of SCPT 0 because one bit SCP0DT is accessed using two pins of TxD0 and RxD0 When the port input is set bit SCPnMD1 is set to 1 and when the TE bit in SCSCR is set to 1 the TxD0 pin is in the output stat...

Page 554: ...Section 17 Pin Function Controller PFC Rev 5 00 May 29 2006 page 506 of 698 REJ09B0146 0500 ...

Page 555: ... data to the pins 18 1 Port A Port A is an 8 bit I O port with the pin configuration shown in figure 18 1 Each pin has an input pull up MOS which is controlled by Port A Control Register PACR in PFC PTA7 I O D23 I O PTA6 I O D22 I O PTA5 I O D21 I O PTA4 I O D20 I O PTA3 I O D19 I O PTA2 I O D18 I O PTA1 I O D17 I O PTA0 I O D16 I O Port A Figure 18 1 Port A 18 1 1 Register Description Port A has ...

Page 556: ...responding pin level is read Bit Bit Name Initial Value R W Description 7 PA7DT 0 R W Table 18 1 shows the function of PADR 6 PA6DT 0 R W 5 PA5DT 0 R W 4 PA4DT 0 R W 3 PA3DT 0 R W 2 PA2DT 0 R W 1 PA1DT 0 R W 0 PA0DT 0 R W Table 18 1 Read Write Operation of the Port A Data Register PADR PAnMD1 PAnMD0 Pin State Read Write 0 Other function PADR value Value is written to PADR but does not affect pin s...

Page 557: ... which is controlled by Port B Control Register PBCR in PFC PTB7 I O D31 I O PTB6 I O D30 I O PTB5 I O D29 I O PTB4 I O D28 I O PTB3 I O D27 I O PTB2 I O D26 I O PTB1 I O D25 I O PTB0 I O D24 I O Port B Figure 18 2 Port B 18 2 1 Register Description Port B has the following register Refer to section 23 List of Registers for more details of the addresses and access size Port B data register PBDR ...

Page 558: ...responding pin level is read Bit Bit Name Initial Value R W Description 7 PB7DT 0 R W Table 18 2 shows the function of PBDR 6 PB6DT 0 R W 5 PB5DT 0 R W 4 PB4DT 0 R W 3 PB3DT 0 R W 2 PB2DT 0 R W 1 PB1DT 0 R W 0 PB0DT 0 R W Table 18 2 Read Write Operation of the Port B Data Register PBDR PBnMD1 PBnMD0 Pin State Read Write 0 Other function PBDR value Value is written to PBDR but does not affect pin s...

Page 559: ...R in PFC PTC7 I O CS6 output CE1B output PTC6 I O CS5 output CE1A output PTC5 I O CS4 output PTC4 I O CS3 output PTC3 I O CS2 output PTC2 I O WE3 output DQMUU output ICIOWR output PTC1 I O WE2 output DQMUL output ICIORD output PTC0 I O BS output Port C Figure 18 3 Port C 18 3 1 Register Description Port C has the following register Refer to section 23 List of Registers for more details of the addr...

Page 560: ...d to H 00 by a power on reset It retains its previous value in standby mode and sleep mode and in a manual reset Bit Bit Name Initial Value R W Description 7 PC7DT 0 R W Table 18 3 shows the function of PCDR 6 PC6DT 0 R W 5 PC5DT 0 R W 4 PC4DT 0 R W 3 PC3DT 0 R W 2 PC2DT 0 R W 1 PC1DT 0 R W 0 PC0DT 0 R W Table 18 3 Read Write Operation of the Port C Data Register PCDR PCnMD1 PCnMD0 Pin State Read ...

Page 561: ...led by Port D Control Register PDCR in PFC PTD7 I O CE2B output PTD6 I O CE2A output PTD5 I O IOIS16 input PTD4 I O CKE output PTD3 I O CASU output PTD2 I O CASL output PTD1 I O RASU output PTD0 I O RASL output Port D Figure 18 4 Port D 18 4 1 Register Description Port D has the following register Refer to section 23 List of Registers for more details of the addresses and access sizes Port D data ...

Page 562: ...r on reset It retains its previous value in standby mode and sleep mode and in a manual reset Bit Bit Name Initial Value R W Description 7 PD7DT 0 R W Table 18 4 shows the function of PDDR 6 PD6DT 0 R W 5 PD5DT 0 R W 4 PD4DT 0 R W 3 PD3DT 0 R W 2 PD2DT 0 R W 1 PD1DT 0 R W 0 PD0DT 0 R W Table 18 4 Read Write Operation of the Port D Data Register PDDR PDnMD1 PDnMD0 Pin State Read Write 0 Other funct...

Page 563: ...by Port E Control Register PECR in PFC PTE7 I O IRQOUT output PTE6 I O TCLK I O PTE5 I O STATUS1 output PTE4 I O STATUS0 output PTE3 I O DRAK1 output PTE2 I O DRAK0 output PTE1 I O DACK1 output PTE0 I O DACK0 output Port E Figure 18 5 Port E 18 5 1 Register Description Port E has the following register Refer to section 23 List of Registers for more details of the addresses and access sizes Port E ...

Page 564: ...n is set as the initial pin function and the corresponding pin levels are read It retains its previous value in standby mode and sleep mode and in a manual reset Bit Bit Name Initial Value R W Description 7 PE7DT 0 R W Table 18 5 shows the function of PEDR 6 PE6DT 0 R W 5 PE5DT 0 R W 4 PE4DT 0 R W 3 PE3DT 0 R W 2 PE2DT 0 R W 1 PE1DT 0 R W 0 PE0DT 0 R W Table 18 5 Read Write Operation of the Port E...

Page 565: ... is controlled by Port F Control Register PFCR in PFC PTF6 I O ASEBRKAK output PTF5 I O TDO output PTF4 I O AUDSYNC output PTF3 I O AUDATA3 I O PTF2 I O AUDATA2 I O PTF1 input AUDATA1 I O PTF0 I O AUDATA0 I O Port F Figure 18 6 Port F 18 6 1 Register Description Port F has the following register Refer to section 23 List of Registers for more details of the addresses and access sizes Port F data re...

Page 566: ... the corresponding pin levels are read It retains its previous value in standby mode and sleep mode and in a manual reset Bit Bit Name Initial Value R W Description 7 0 R Reserved 6 PF6DT 0 R W Table 18 6 shows the function of PFDR 5 PF5DT 0 R W 4 PF4DT 0 R W 3 PF3DT 0 R W 2 PF2DT 0 R W 1 PF1DT 0 R W 0 PF0DT 0 R W Table 18 6 Read Write Operation of the Port F Data Register PFDR PFnMD1 PFnMD0 Pin S...

Page 567: ...OS which is controlled by Port G Control Register PGCR in PFC PTG5 input ADTRG input PTG4 input AUDCK input PTG3 input TRST input PTG2 input TMS input PTG1 input TCK input PTG0 input TDI input Port G Figure 18 7 Port G 18 7 1 Register Description Port G has the following register Refer to section 23 List of Registers for more details of the addresses and access sizes Port G data register PGDR ...

Page 568: ...ial pin function and the corresponding pin levels are read It retains its previous value in standby mode and sleep mode and in a manual reset Bit Bit Name Initial Value R W Description 7 R Reserved 6 R 5 PG5DT R Table 18 7 shows the function of PGDR 4 PG4DT R 3 PG3DT R 2 PG2DT R 1 PG1DT R 0 PG0DT R Legend Undefined Table 18 7 Read Write Operation of the Port G Data Register PGDR PGnMD1 PGnMD0 Pin ...

Page 569: ...Port H Control Register PHCR in PFC Port H PTH6 I O DREQ1 input PTH5 I O DREQ0 input PTH4 I O IRQ4 input PTH3 I O IRQ3 input IRL3 input PTH2 I O IRQ2 input IRL2 input PTH1 I O IRQ1 input IRL1 input PTH0 I O IRQ0 input IRL0 input Figure 18 8 Port H 18 8 1 Register Description Port H has the following register Refer to section 23 List of Registers for more details of the addresses and access sizes P...

Page 570: ...tandby mode and sleep mode and in a manual reset Note that the low level is read if bits 6 to 0 are read except in general purpose input Bit Bit Name Initial Value R W Description 7 R Reserved 6 PH6DT 0 R W Table 18 8 shows the function of PHDR 5 PH5DT 0 R W 4 PH4DT 0 R W 3 PH3DT 0 R W 2 PH2DT 0 R W 1 PH1DT 0 R W 0 PH0DT 0 R W Legend Undefined Table 18 8 Read Write Operation of the Port H Data Reg...

Page 571: ...ration shown in figure 18 9 PTJ3 input AN3 input DA0 output PTJ2 input AN2 input DA1 output PTJ1 input AN1 input PTJ0 input AN0 input Port J Figure 18 9 Port J 18 9 1 Register Description Port J has the following register Refer to section 23 List of Registers for more details of the addresses and access sizes Port J data register PJDR ...

Page 572: ... function is general input port if the port is read the corresponding pin level is read Bit Bit Name Initial Value R W Description 7 0 R Reserved 6 0 R 5 0 R 4 0 R 3 PJ3DT 0 R Table 18 9 shows the function of PJDR 2 PJ2DT 0 R 1 PJ1DT 0 R 0 PJ0DT 0 R Table 18 9 Read Write Operation of the Port J Data Register PJDR PJnMD1 PJnMD0 Pin State Read Write 0 Other function Low level Ignored no affect on pi...

Page 573: ...lled by SC port Control Register SCPCR in PFC SCPT5 input CTS2 input IRQ5 input SCPT4 I O RTS2 output SCPT3 I O SCK2 I O SCPT2 input RxD2 input SCPT2 output TxD2 output SCPT1 I O SCK0 I O SCPT0 input RxD0 input SCPT0 output TxD0 output SC Port Figure 18 10 SC Port 18 10 1 Register Description Port SC has the following register Refer to section 23 List of Registers for more details of the addresses...

Page 574: ...t port function pull up MOS on is set as the initial pin function and the corresponding pin levels are read from bits SCP5DT to SCP3DT and SCP1DT SCPDR retains its previous value in standby mode and sleep mode and in a manual reset Note that the low level is read if bit 7 is read except in general purpose input When reading the state of the RxD2 and RxD0 pins of the SCP2DT and SCP0DT bits in SCPDR...

Page 575: ...is output from pin 0 Input Pull up MOS on Pin state Value is written to SCPDR but does not affect pin state 1 1 Input Pull up MOS off Pin state Value is written to SCPDR but does not affect pin state Note n 0 to 4 For SCP5DT SCPnMD1 SCPnMD0 Pin State Read Write 0 Other function Low level Ignored no affect on pin state 0 1 Reserved Setting prohibited Ignored no affect on pin state 0 Input Pull up M...

Page 576: ...Section 18 I O Ports Rev 5 00 May 29 2006 page 528 of 698 REJ09B0146 0500 ...

Page 577: ... speed conversion Conversion time minimum 15 µs per channel with Pφ 33 MHz peripheral clock Three conversion modes Single mode A D conversion of one channel Multi mode A D conversion on one to four channels Scan mode Continuous A D conversion on one to four channels Four 16 bit data registers A D conversion results are transferred for storage into data registers corresponding to the channels Sampl...

Page 578: ...essive approxi mation register Comparator Sample and hold circuit ADI interrupt signal AVSS AN0 AN1 AN2 AN3 φ 4 φ 8 ADCSR ADCR AVCC A D converter Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D Internal data bus ADTRG ADDRC Figure 19 1 A D Converter Block Diagram ...

Page 579: ...ut Group 0 analog inputs A D external trigger input pin ADTRG Input External trigger input for starting A D conversion 19 3 Register Description The A D converter has the following registers Refer to section 23 List of Registers for more details of the addresses and access sizes A D data register A ADDRA The upper and lower bytes of ADDRA may be represented by ADDRAH and ADDRAL respectively A D da...

Page 580: ...ts 15 to 8 of the A D data register The lower 2 bits are stored in the lower byte bits 7 and 6 Bits 5 to 0 of an A D data register are reserved bits that always read 0 For the reading of the data see section 19 4 Bus Master Interface and section 19 9 3 Access Size and Read Data Table 19 2 indicates the pairings of analog input channels and A D data registers Bit Bit Name Initial Value R W Descript...

Page 581: ...ions 1 Cleared by reading ADF while ADF 1 then writing 0 in ADF 2 Cleared when DMAC is activated by ADI interrupt and ADDR is read 1 Setting conditions 1 Single mode A D conversion ends 2 Multi mode A D conversion ends in all selected channels 3 Scan mode A D conversion ends in all selected channels 6 ADIE 0 R W A D Interrupt Enable Enables or disables the interrupt ADI requested at the end of A D...

Page 582: ...onversion ends in all selected channels 3 Scan mode A D conversion starts and continues cycling among the selected channels until ADST is cleared to 0 by software reset or by a transition to standby mode 4 MULTI 0 R W Multi Mode Selects single mode multi mode or scan mode For further information on operation in these modes see section 19 6 Operation The mode is selected by the combination of this ...

Page 583: ...ect These bits and the MULTI bit select the analog input channels Clear the ADST bit to 0 before changing the channel selection Single Mode Multi Mode and Scan MULTI 0 Mode MULTI 1 000 AN0 AN0 001 AN1 AN0 AN1 010 AN2 AN0 to AN2 011 AN3 AN0 to AN3 Notes 1 Only 0 can be written to clear the flag 2 The CKS value should be set so that the A D conversion time is 16 µs minimum ...

Page 584: ...ntrol Status Register ADCSR 4 3 All 0 R W Reserved These bits are always read as 0 The write value should always be 0 2 to 0 All 1 R Reserved These bits are always read as 1 The write value should always be 0 19 4 Bus Master Interface ADDRA to ADDRD are 16 bit registers but they are connected to the bus master by the upper 8 bits of the 16 bit peripheral data bus Therefore although the upper byte ...

Page 585: ... interface TEMP H 40 Lower byte of A D data register H 40 Upper byte of A D data register H AA CPU H AA Upper byte read Module internal data bus Bus interface TEMP H 40 CPU H 40 Lower byte read Module internal data bus Lower byte of A D data register H 40 Upper byte of A D data register H AA Figure 19 2 A D Data Register Access Operation Reading H AA40 ...

Page 586: ...3 shows an example of reading ADDRAH ADDRAH Invalid data 15 8 7 0 Figure 19 3 Word Access Example 19 5 2 Longword Access When A D data registers are read in longword the upper byte of the A D data register is read from bits 31 to 24 invalid data from bits 23 to 16 the lower byte of the A D data register from bits 15 to 8 and invalid data from bits 7 to 0 Figure 19 4 shows an example of reading ADD...

Page 587: ...irst clear the ADST bit to 0 in ADCSR to halt A D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the mode or channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 19 5 shows a timing diagram for this example 1 Single mode is selected MULTI 0 input c...

Page 588: ...re channels When the ADST bit in ADCSR is set to 1 by software or external trigger input A D conversion starts on the first channel in the group AN0 when CH2 0 When two or more channels are selected after conversion of the first channel ends conversion of the second channel AN1 starts immediately When A D conversions end on the selected channels the ADST bit is cleared to 0 The conversion results ...

Page 589: ...4 When conversion of all selected channels AN0 to AN2 is completed the ADF flag is set to 1 and ADST bit is cleared to 0 If the ADIE bit is set to 1 an ADI interrupt is requested at this time When the ADST bit is cleared to 0 A D conversion stops After that if the ADST bit is set to 1 A D conversion starts again from the first channel AN0 Channel 0 AN0 operating ADST ADF Channel 1 AN1 operating Ch...

Page 590: ...ion will start again from the first channel in the group The ADST bit can be set at the same time as the mode or channel selection is changed Typical operations when three channels AN0 to AN2 are selected in scan mode are described next Figure 19 7 shows a timing diagram for this example 1 Scan mode is selected MULTI 1 SCN 1 channel group 0 is selected CH2 0 analog input channels AN0 to AN2 are se...

Page 591: ...xample of A D Converter Operation Scan Mode Channels AN0 to AN2 Selected 19 6 4 Input Sampling and A D Conversion Time The A D converter has a built in sample and hold circuit The A D converter samples the analog input at a time tD after the ADST bit in ADCSR is set to 1 then starts conversion Figure 19 8 shows the A D conversion timing Table 19 3 indicates the A D conversion time As indicated in ...

Page 592: ...time tCONV A D conversion time Notes 1 ADCSR write cycle 2 ADCSR address Address 2 tD tSPL tCONV Figure 19 8 A D Conversion Timing Table 19 3 A D Conversion Time Single Mode CKS 0 CKS 1 Symbol Min Typ Max Min Typ Max A D conversion start delay tD 17 28 10 17 Input sampling time tSPL 129 65 A D conversion time tCONV 514 525 259 266 Note Values in the table are numbers of states tcyc ...

Page 593: ...External Trigger Input Timing 19 7 Interrupt Requests The A D converter generates an interrupt ADI at the end of A D conversion The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR 19 8 Definitions of A D Conversion Accuracy The A D converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10 bit digital data T...

Page 594: ...sion characteristics between zero voltage and full scale voltage figure 19 10 item 4 Note that it does not include offset full scale or quantization error 111 110 101 100 011 010 001 000 0 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Analog input voltage Legend FS Full scale voltage 3 Quantization error Ideal A D conversion characteristics 4 Nonlinearity error Ideal A D conversion characteristics Actual A D con...

Page 595: ... example The circuit constants should be selected according to actual application conditions Table 19 4 lists the analog input pin specifications and figure 19 12 shows an equivalent circuit diagram of the analog input ports 0 01 µF 10 µF AVCC AN0 to AN3 AVSS SuperH microprocessor 100 Ω 0 1 µF Note Figure 19 11 Example of Analog Input Protection Circuit 1 0 kΩ AN0 to AN3 20 pF 1 MΩ Figure 19 12 An...

Page 596: ...onship between Access Size and Read Data Bus Width 32 Bits D31 to D0 16 Bits D15 to D0 8 Bits D7 to D0 Access Size Command Endian Big Little Big Little Big Little Byte access MOV L MOV B MOV L MOV B ADDRAH R9 R9 R8 ADDRAL R9 R9 R8 FFFFFFFF C0C0C0C0 FFFFFFFF C0C0C0C0 FFFF C0C0 FFFF C0C0 FF C0 FF C0 Word access MOV L MOV W MOV L MOV W ADDRAH R9 R9 R8 ADDRAL R9 R9 R8 FFxxFFxx C0xxC0xx FFxxFFxx C0xxC0...

Page 597: ...verter AVCC DA0 DA1 DACR DADR0 DADR1 Module data bus Bus interface On chip data bus Control circuit 8 bit D A AVSS Legend DACR DADR0 DADR1 D A control register D A data register 0 D A data register 1 Figure 20 1 D A Converter Block Diagram 20 1 Feature D A converter features are listed below 8 bit resolution Two output channels Conversion time maximum 10 µs with 20 pF capacitive load Output voltag...

Page 598: ...Description The D A converter has the following registers Refer to section 23 List of Registers for more details of the addresses and access sizes D A data register 0 DADR0 D A data register 1 DADR1 D A control register DACR 20 3 1 D A Data Registers 0 and 1 DADR0 and DADR1 The D A data registers DADR0 and DADR1 are 8 bit read write registers that store the data to be converted When analog output ...

Page 599: ...s enabled the D A output is held and the analog power supply current is equivalent to that during D A conversion To reduce the analog power supply current in standby mode clear the DAOE0 and DAOE1 bits and disable the D A output 00 D A conversion is disabled in channels 0 and 1 010 D A conversion is enabled in channel 0 D A conversion is disabled in channel 1 011 D A conversion is enabled in chann...

Page 600: ...DAOE0 is set to 1 in DACR D A conversion starts and DA0 becomes an output pin The converted result is output after the conversion time The output value is DADR0 contents 256 AVcc Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0 3 If the DADR0 value is modified conversion starts immediately and the result is output after the conversion...

Page 601: ...nt Test Action Group IEEE Standard 1149 1 and IEEE Standard Test Access Port and Boundary Scan Architecture specifications The H UDI in the SH7706 supports a boundary scan mode and is also used for emulator connection When using an emulator H UDI functions should not be used Refer to the emulator manual for the method of connecting the emulator Figure 21 1 shows the block diagram of the H UDI SDIR...

Page 602: ... with TCK The protocol conforms to the JTAG standard IEEE Std 1149 1 TRST H UDI reset input pin Input is accepted asynchronously with respect to TCK and when low the H UDI is reset See section 21 4 2 Reset Configuration for more information TDI H UDI serial data input pin Data transfer to the H UDI is executed by changing this signal in synchronization with TCK TDO H UDI serial data output pin Dat...

Page 603: ... a 16 bit read only register The register is in bypass mode in its initial state It is initialized by TRST or in the TAP test logic reset state and can be written by the H UDI irrespective of the CPU mode Operation is not guaranteed when a reserved command is set to this register Bit Bit Name Initial Value R W Description 15 14 13 12 TI3 TI2 TI1 TI0 1 1 1 1 R R R R Test Instruction Bits Cannot be ...

Page 604: ...I 272 D6 IN 297 D31 PTB 7 IN 271 D5 IN 296 D30 PTB 6 IN 270 D4 IN 295 D29 PTB 5 IN 269 D3 IN 294 D28 PTB 4 IN 268 D2 IN 293 D27 PTB 3 IN 267 D1 IN 292 D26 PTB 2 IN 266 D0 IN 291 D25 PTB 1 IN 265 D31 PTB 7 OUT 290 D24 PTB 0 IN 264 D30 PTB 6 OUT 289 D23 PTA 7 IN 263 D29 PTB 5 OUT 288 D22 PTA 6 IN 262 D28 PTB 4 OUT 287 D21 PTA 5 IN 261 D27 PTB 3 OUT 286 D20 PTA 4 IN 260 D26 PTB 2 OUT 285 D19 PTA 3 IN...

Page 605: ...1 PTB 7 Control 199 WE3 DQMUU ICIOWR PTC 2 IN 232 D30 PTB 6 Control 198 CS2 PTC 3 IN 231 D29 PTB 5 Control 197 CS3 PTC 4 IN 230 D28 PTB 4 Control 196 A0 OUT 229 D27 PTB 3 Control 195 A1 OUT 228 D26 PTB 2 Control 194 A2 OUT 227 D25 PTB 1 Control 193 A3 OUT 226 D24 PTB 0 Control 192 A4 OUT 225 D23 PTA 7 Control 191 A5 OUT 224 D22 PTA 6 Control 190 A6 OUT 223 D21 PTA 5 Control 189 A7 OUT 222 D20 PTA ...

Page 606: ... 166 WE2 DQMUL ICIORD PTC 1 OUT 136 A24 Control 165 WE3 DQMUU ICIOWR PTC 2 OUT 135 A25 Control 164 RD WR OUT 134 BS PTC 0 Control 163 CS0 OUT 133 RD Control 162 CS2 PTC 3 OUT 132 WE0 DQMLL Control 161 CS3 PTC 4 OUT 131 WE1 DQMLU WE Control 160 A0 Control 130 WE2 DQMUL ICIORD PTC 1 Control 159 A1 Control 129 WE3 DQMUU ICIOWR PTC 2 Control 158 A2 Control 128 RD WR Control 157 A3 Control 127 CS0 Cont...

Page 607: ...S5 CE1A PTC 6 Control 106 AUDATA 1 PTF 1 IN 76 CS6 CE1B PTC 7 Control 105 AUDATA 2 PTF 2 IN 75 CE2A PTD 6 Control 104 AUDATA 3 PTF 3 IN 74 CE2B PTD 7 Control 103 AUDSYNC PTF 4 IN 73 RASL PTD 0 Control 102 ASEBRKAK PTF 6 IN 72 RASU PTD 1 Control 101 MD1 IN 71 CASL PTD 2 Control 100 CS4 PTC 5 OUT 70 CASU PTD 3 Control 99 CS5 CE1A PTC 6 OUT 69 CKE PTD 4 Control 98 CS6 CE1B PTC 7 OUT 68 IOIS16 PTD 5 C...

Page 608: ... IRQ4 PTH 4 OUT 47 CTS2 IRQ5 SCPT 5 IN 17 DREQ0 PTH 5 OUT 46 IRQ0 IRL0 PTH 0 IN 16 DREQ1 PTH 6 OUT 45 IRQ1 IRL1 PTH 1 IN 15 STATUS0 PTE 4 Control 44 IRQ2 IRL2 PTH 2 IN 14 STATUS1 PTE 5 Control 43 IRQ3 IRL3 PTH 3 IN 13 TCLK PTE 6 Control 42 IRQ4 PTH 4 IN 12 IRQOUT PTE 7 Control 41 NMI IN 11 TxD0 SCPT 0 Control 40 AUDCK PTG 4 IN 10 SCK0 SCPT 1 Control 39 DREQ0 PTH 5 IN 9 TxD2 SCPT 2 Control 38 DREQ1...

Page 609: ...dle 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 1 1 1 0 Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select IR scan 0 0 1 0 0 0 1 0 1 1 1 0 0 Figure 21 2 TAP Controller State Transitions Note The transition condition is the TMS value on the rising edge of TCK The TDI value is sampled on the rising edge of TCK shifting occurs on the falling edge of TCK The TDO value changes on the TCK falling edge Th...

Page 610: ...tion mode and ASE mode settings ASEMD0 H normal operation mode ASEMD0 L ASE mode ASEMD0 pin should be high level when an emulator or H UDI is not used 2 During ASE mode reset hold is enabled by setting RESETP and TRST pins at low level for a constant cycle In this state the CPU does not start up even if RESETP is set to high level When TRST is set to high level H UDI operation is enabled but the C...

Page 611: ...DIR Chip internal reset CPU state Branch to H A0000000 Figure 21 3 H UDI Reset 21 4 4 H UDI Interrupt The H UDI interrupt function generates an interrupt by setting a command from the H UDI in the SDIR An H UDI interrupt is a general exception interrupt operation resulting in a branch to an address based on the VBR value plus offset and return by the RTE instruction This interrupt request has a fi...

Page 612: ...0 In a SAMPLE operation a snapshot of a value to be transferred from an input pin to the internal circuitry or a value to be transferred from the internal circuitry to an output pin is latched into the boundary scan register and read from the scan path Snapshot latching is performed in synchronization with the rise of TCK in the Capture DR state Snapshot latching does not affect normal operation o...

Page 613: ...y for respective clock mode specified in the CPG section Set pins MD 2 0 to the clock mode to be used After powering on wait for the CKIO clock to stabilize before performing a boundary scan test 5 Fix the RESETP pin low 6 Fix the CA pin high and the ASEMD0 pin low 21 6 Usage Note 1 An H UDI command other than an H UDI interrupt once set will not be modified as long as another command is not re is...

Page 614: ...Section 21 User Debugging Interface H UDI Rev 5 00 May 29 2006 page 566 of 698 REJ09B0146 0500 ...

Page 615: ... power consumption The SH7706 has four power down modes 1 Sleep mode 2 Software standby mode 3 Module standby function TMU RTC SCI UBC DMAC DAC ADC and SCIF on chip supporting modules 4 Hardware standby mode Table 22 1 shows the transition conditions for entering the modes from the program execution state as well as the CPU and supporting module states in each mode and the procedures for canceling...

Page 616: ...dby mode Drive CA pin low Halts Halts Held Held Halts 3 Held Self refresh Power on reset Notes 1 The RTC still runs if the START bit in RCR2 is set to 1 see section 13 Realtime Clock RTC TMU still runs when output of the RTC is used as input to its counter see section 12 Timer Unit TMU 2 Depends on the on chip supporting module TMU external pin Held SCI external pin Reset 3 The RTC still runs if t...

Page 617: ...on These are two control registers for the power down modes Refer to section 23 List of Registers for more details of the addresses and access sizes Standby control register STBCR Standby control register 2 STBCR2 22 2 1 Standby Control Register STBCR The standby control register STBCR is an 8 bit read write register that sets the power down mode Bit Bit Name Initial Value R W Description 7 STBY 0...

Page 618: ...nit TMU an on chip supporting module When the MSTP2 bit is set to 1 the supply of the clock to the TMU is halted 0 TMU runs 1 Clock supply to TMU is halted 1 MSTP1 0 R W Module Stop 1 Specifies halting the clock supply to the realtime clock RTC an on chip supporting module When the MSTP1 bit is set to 1 the supply of the clock to RTC is halted When the clock halts all RTC registers become inaccess...

Page 619: ... MD5 to MD0 pin values are latched when returning from software standby mode by means of a reset or interrupt 0 Pins MD5 to MD0 are not changed in software standby mode 1 Pins MD5 to MD0 are changed in software standby mode 5 MSTP8 0 R W Module Stop 8 Specifies halting the clock supply to the user break controller UBC an on chip supporting module When the MSTP8 bit is set to 1 the supply of the cl...

Page 620: ...halting of clock supply to the ADC an on chip peripheral module When the MSTP5 bit is set to 1 the supply of the clock to the ADC is halted and all registers are initialized 0 ADC runs 1 Clock supply to ADC halted and all registers initialized 1 MSTP4 0 R W Module Stop 4 Specifies halting the clock supply to the serial communication interface with FIFO an on chip peripheral module When the MSTP1 b...

Page 621: ... output to the CKIO pin In sleep mode the STATUS1 pin is set high and the STATUS0 pin low Canceling Sleep Mode Sleep mode is canceled by an interrupt NMI IRQ IRL on chip supporting module or reset Interrupts are accepted during sleep mode even when the BL bit in the SR register is 1 If necessary save SPC and SSR in the stack before executing the SLEEP instruction Canceling with an Interrupt When a...

Page 622: ...controller INTC All registers On chip clock pulse generator CPG All registers User Break controller UBC All registers Bus state controller BSC All registers Timer unit TMU TSTR register Registers other than TSTR Realtime clock RTC All registers A D converter ADC All registers D A converter DAC All registers The procedure for moving to software standby mode is as follows 1 Clear the TME bit in the ...

Page 623: ...en the BL bit in the SR register is 1 If necessary save SPC and SSR in the stack before executing the SLEEP instruction Immediately after an interrupt is detected the phase of the clock output of the CKIO pin may be unstable until the processor starts interrupt processing The canceling condition is that the IRL3 to IRL0 level is higher than the mask level in the I3 to I0 bits in the SR register No...

Page 624: ... internally within the chip the STATUS1 and STATUS0 pins both go low interrupts are handled and operation resumes 22 3 3 Module Standby Function Transition to Module Standby Function Setting the standby control register MSTP8 to MSTP4 MSTP2 to MSTP0 bits to 1 halts the supply of clocks to the corresponding on chip supporting modules This function can be used to reduce the power consumption in norm...

Page 625: ... SCIF runs MSTP4 1 Supply of clock to SCIF halted 0 TMU runs MSTP2 1 Supply of clock to TMU halted Registers initialized 1 0 RTC runs MSTP1 1 Supply of clock to RTC halted Register access prohibited 2 0 SCI runs MSTP0 1 Supply of clock to SCI halted Notes 1 The registers initialized are the same as in the software standby mode table 22 3 2 The counter runs Clearing the Module Standby Function The ...

Page 626: ... to 30 Bcyc 3 Notes 1 Reset HH STATUS1 high STATUS0 high 2 Normal LL STATUS1 low STATUS0 low 3 Bcyc Bus clock cycle Figure 22 2 Power On Reset STATUS Output Manual Reset CKIO RESETM 1 STATUS Normal 3 Normal 3 Reset 2 0 Bcyc or more 4 0 to 30 Bcyc 4 Notes 1 During manual reset STATUS becomes HH reset and the internal reset begins after waiting for the executing bus cycle to end 2 Reset HH STATUS1 h...

Page 627: ...e Standby to Interrupt STATUS Output Software Standby to Power On Reset CKIO STATUS Normal 4 Normal 4 Oscillation stops Standby 3 0 to 10 Bcyc 5 0 to 30 Bcyc 5 Reset Reset 2 RESETP 1 6 Notes 1 When software software standby mode is cleared with a power on reset the WDT does not count Keep RESETP low during the PLL s oscillation settling time 2 Reset HH STATUS1 high STATUS0 high 3 Standby LH STATUS...

Page 628: ...not count Keep RESETM low during the PLL s oscillation settling time 2 Reset HH STATUS1 high STATUS0 high 3 Standby LH STATUS1 low STATUS0 high 4 Normal LL STATUS1 low STATUS0 low 5 Bcyc Bus clock cycle Figure 22 6 Software Standby to Manual Reset STATUS Output Timing for Canceling Sleep Mode Sleep to Interrupt CKIO STATUS Normal 2 Normal 2 Sleep 1 Interrupt request Notes 1 Sleep HL STATUS1 high S...

Page 629: ... Reset HH STATUS1 high STATUS0 high 3 Sleep HL STATUS1 high STATUS0 low 4 Normal LL STATUS1 low STATUS0 low 5 Bcyc Bus clock cycle 6 Undefined Figure 22 8 Sleep to Power On Reset STATUS Output Sleep to Manual Reset CKIO 0 to 80 Bcyc 5 0 to 30 Bcyc 5 Reset STATUS Normal 4 Normal 4 Sleep 3 Reset 2 RESETM 1 Notes 1 Keep RESETM low until STATUS becomes reset 2 Reset HH STATUS1 high STATUS0 high 3 Slee...

Page 630: ...standby state Acceptance of interrupts and manual resets is disabled TCLK output is fixed low and the TMU halts 2 During WDT operation when software standby mode is canceled by an interrupt The chip enters hardware standby mode after standby mode is canceled and the CPU resumes operation 3 In sleep mode The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes operatio...

Page 631: ...ck cycles The CA pin must be held low while the chip is in hardware standby mode Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low Normal 3 STATUS CA CKIO Standby 2 RESETP Undefined 2 Rcyc or more 5 0 to 10Bcyc 4 0 to 30Bcyc 4 Notes 1 Reset HH STATUS1 high STATUS0 high 2 Standby LH STATUS1 low STATUS0 high 3 Normal LL STATUS1 low STATUS0 low 4 Bcyc Bus cloc...

Page 632: ...ed 2 Rcyc or more 5 0 to 10 Bcyc 4 Standby 2 WDT operation Notes 1 Reset HH STATUS1 high STATUS0 high 2 Standby LH STATUS1 low STATUS0 high 3 Normal LL STATUS1 low STATUS0 low 4 Bcyc Bus clock cycle 5 Rcyc EXTAL2 32 768 kHz cycle Figure 22 11 Hardware Standby Mode Timing When CA Goes Low during WDT Operation on Standby Mode Cancellation ...

Page 633: ... H FFFFFFE8 8 8 CCR L H FFFFFFEC 32 32 CCR2 I H A40000B0 32 32 TRA L H FFFFFFD0 32 32 EXPEVT L H FFFFFFD4 32 32 INTEVT L H FFFFFFD8 32 32 BARA UBC L H FFFFFFB0 32 32 BAMRA L H FFFFFFB4 32 32 BBRA L H FFFFFFB8 16 16 BARB L H FFFFFFA0 32 32 BAMRB L H FFFFFFA4 32 32 BBRB L H FFFFFFA8 16 16 BDRB L H FFFFFF90 32 32 BDMRB L H FFFFFF94 32 32 BRCR L H FFFFFF98 32 32 BETR L H FFFFFF9C 16 16 BRSR L H FFFFFF...

Page 634: ...6 RTCOR I H FFFFFF72 16 16 RFCR I H FFFFFF74 16 16 SDMR I H FFFFD000 to H FFFFEFFF 8 R64CNT RTC P H FFFFFEC0 8 8 RSECCNT P H FFFFFEC2 8 8 RMINCNT P H FFFFFEC4 8 8 RHRCNT P H FFFFFEC6 8 8 RWKCNT P H FFFFFEC8 8 8 RDAYCNT P H FFFFFECA 8 8 RMONCNT P H FFFFFECC 8 8 RYRCNT P H FFFFFECE 8 8 RSECAR P H FFFFFED0 8 8 RMINAR P H FFFFFED2 8 8 RHRAR P H FFFFFED4 8 8 RWKAR P H FFFFFED6 8 8 RDAYAR P H FFFFFED8 8...

Page 635: ...AC 32 32 TCNT_2 P H FFFFFEB0 32 32 TCR_2 P H FFFFFEB4 16 16 TCPR_2 P H FFFFFEB8 32 32 SCSMR SCI P H FFFFFE80 8 8 SCBRR P H FFFFFE82 8 8 SCSCR P H FFFFFE84 8 8 SCTDR P H FFFFFE86 8 8 SCSSR P H FFFFFE88 8 8 SCRDR P H FFFFFE8A 8 8 SCSCMR P H FFFFFE8C 8 8 INTEVT2 INTC I H 04000000 32 32 IRR0 I H A4000004 16 8 IRR1 I H A4000006 16 8 IRR2 I H A4000008 16 8 ICR1 I H A4000010 16 16 IPRC I H A4000016 16 16...

Page 636: ...00054 32 16 32 DMATCR_3 P H A4000058 32 16 32 CHCR_3 P H A400005C 32 8 16 32 DMAOR P H A4000060 16 8 16 CMSTR CMT P H A4000070 16 8 16 32 CMCSR P H A4000072 16 8 16 32 CMCNT P H A4000074 16 8 16 32 CMCOR P H A4000076 16 8 16 32 ADDRAH A D P H A4000080 8 8 16 32 4 5 ADDRAL P H A4000082 8 8 16 4 ADDRBH P H A4000084 8 8 16 32 4 5 ADDRBL P H A4000086 8 8 16 4 ADDRCH P H A4000088 8 8 16 32 4 5 ADDRCL P...

Page 637: ... PHCR P H A400010E 16 16 PJCR P H A4000110 16 16 SCPCR P H A4000116 16 16 PADR P H A4000120 8 8 PBDR P H A4000122 8 8 PCDR P H A4000124 8 8 PDDR P H A4000126 8 8 PEDR P H A4000128 8 8 PFDR P H A400012A 8 8 PGDR P H A400012C 8 8 PHDR P H A400012E 8 8 PJDR P H A4000130 8 8 SCPDR P H A4000136 8 8 SCSMR2 SCIF P H A4000150 8 8 SCBRR2 P H A4000152 8 8 SCSCR2 P H A4000154 8 8 SCFTDR2 P H A4000156 8 8 SCS...

Page 638: ... L CPU CCN cache and TLB connected I BSC cache DMAC INTC CPG and H UDI connected P BSC and peripheral modules RTC TMU SCI SCIF A D D A DMAC ports CMT connected 3 The access size shown is for control register access read write An incorrect result will be obtained if a different size from that shown is used for access 4 With 16 bit access it is not possible to read data in two registers simultaneous...

Page 639: ...t 2 Bit 1 Bit 0 Module SCSMR C A CHR PE O E STOP MP CKS1 CKS0 SCBRR SCSCR TIE RIE TE RE MPIE TEIE CKE1 CKE0 SCTDR SCSSR TDRE RDRF ORER FER ERS PER TEND MPB MPBT SCRDR SCSCMR SDIR SINV SMIF SCI SCFRDR2 SCFTDR2 SCSMR2 CHR PE O E STOP CKS1 CKS0 SCSCR2 TIE RIE TE RE CKE1 CKE0 SCSSR2 ER TEND TDFE BRK FER PER RDF DR SCBRR2 SCFCR2 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP SCFDR2 SCIF TOCR TCOE TSTR ST...

Page 640: ...t 0 Module TCOR_1 TCNT_1 UNF TCR_1 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCOR_2 TCNT_2 ICPF UNF TCR_2 ICPE1 ICPE0 UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TCPR_2 TMU R64CNT 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz RSECCNT 10 sec 1 sec RMINCNT 10 min 1 min RHRCNT 10 hours 1 hour RWKCNT day of week RDAYCNT 10 days 1 day RMONCNT 10 months 1 month RTC ...

Page 641: ...A TMU2 RTC WDT REF IPRB SCI INTC PULA PULD HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1 BCR1 A5BST0 A6BST1 A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 A5PCM A6PCM A6SZ1 A6SZ0 A5SZ1 A5SZ0 A4SZ1 A4SZ0 BCR2 A3SZ1 A3SZ0 A2SZ1 A2SZ0 WAITSEL A6IW1 A6IW0 A5IW1 A5IW0 A4IW1 A4IW0 WCR1 A3IW1 A3IW0 A2IW1 A2IW0 A0IW1 A0IW0 A6W2 A6W1 A6W0 A5W2 A5W1 A5W0 A4W2 A4W1 WCR2 A4W0 A3W1 A3W0 A2W1 A2W0 A0W2 A0W1 A0W0 TPC1 TPC0 RCD1 RCD...

Page 642: ...B3 BDB2 BDB1 BDB0 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8 BDMRB BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1 BDMB0 BASMA BASMB SCMFCA SCMFCB SCMFDA SCMFDB PCTE PCBA BRCR DBEB PCBB SEQ ETBE BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB1...

Page 643: ...AMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA8 BAMRA BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 BBRA CDA1 CDA0 IDA1 IDA0 RWA1 RWA0 SZA1 SZA0 BETR SVF PID2 PID1 PID0 BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BRSR BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 DVF BDA27 BDA26 BDA25 BDA24 BDA23...

Page 644: ...May 29 2006 page 596 of 698 REJ09B0146 0500 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INTEVT SV MMUCR RC RC TF IX AT CCR CF CB WT CE W3LOAD W3LOCK CCR2 W2LOAD W2LOCK VPN PTEH ASID PPN V PTEL PR PR SZ C D SH TTB TEA CCN ...

Page 645: ... IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R IRR1 DEI3R DEI2R DEI1R DEI0R IRR2 ADIR TXI2R BRI2R RXI2R ERI2R MAI IRQLVL BLMSK IRQ51S IRQ50S IRQ41S IRQ40S ICR1 IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S IRQ3 IRQ2 IPRC IRQ1 IRQ0 IPRD IRQ5 IRQ4 DMAC IPRE SCIF A D INTC SAR_0 DAR_0 DMATCR_0 DI RO RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 CHCR_0 DS TM TS1 TS0 IE TE DE DMAC ...

Page 646: ...0146 0500 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SAR_1 DAR_1 DMATCR_1 DI RO RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 CHCR_1 DS TM TS1 TS0 IE TE DE SAR_2 DAR_2 DMATCR_2 DI RO RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 CHCR_2 DS TM TS1 TS0 IE TE DE DMAC ...

Page 647: ...f 698 REJ09B0146 0500 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SAR_3 DAR_3 DMATCR_3 DI RO RL AM AL DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0 CHCR_3 DS TM TS1 TS0 IE TE DE PR1 PR0 DMAOR AE NMIF DME DMAC CMSTR STR0 CMCSR CMF CKS1 CKS0 CMCNT CMCOR CMT ...

Page 648: ...B6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 PBCR PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 PC7MD1 PC7MD0 PC6MD1 PC6MD0 PC5MD1 PC5MD0 PC4MD1 PC4MD0 PCDR PC3MD1 PC3MD0 PC2MD1 PC2MD0 PC1MD1 PC1MD0 PC0MD1 PC0MD0 PD7MD1 PD7MD0 PD6MD1 PD6MD0 PD5MD1 PD5MD0 PD4MD1 PD4MD0 PDCR PD3MD1 PD3MD0 PD2MD1 PD2D0 PD1MD1 PD1MD0 PD0MD1 PD0MD0 PE7MD1 PE7MD0 PE6MD1 PE6MD0 PE5MD1 PE5MD0 PE4MD1 PE4MD0 PECR PE3MD1 PE3M...

Page 649: ... PA3DT PA2DT PA1DT PA0DT PBDR PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT PCDR PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT PDDR PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT PEDR PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT PFDR PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT PGDR PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT PHDR PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT PJDR PJ3DT PJ2DT PJ1DT PJ0DT...

Page 650: ...zed Initialized Held Held Held Held INTEVT Undefined Undefined Held Held Held Held BARA Initialized Initialized Held Held Held Held UBC BAMRA Initialized Initialized Held Held Held Held BBRA Initialized Initialized Held Held Held Held BARB Initialized Initialized Held Held Held Held BAMRB Initialized Initialized Held Held Held Held BBRB Initialized Initialized Held Held Held Held BDRB Initialized ...

Page 651: ...Held Held RMINCNT Held Held Held Held Held Held RHRCNT Held Held Held Held Held Held RWKCNT Held Held Held Held Held Held RDAYCNT Held Held Held Held Held Held RMONCNT Held Held Held Held Held Held RYRCNT Held Held Held Held Held Held RSECAR Held 3 Held 3 Held Held Held Held RMINAR Held 3 Held 3 Held Held Held Held RHRAR Held 3 Held 3 Held Held Held Held RWKAR Held 3 Held 3 Held Held Held Held RDA...

Page 652: ...R Initialized Initialized Initialized Initialized Initialized Held SCSSR Initialized Initialized Initialized Initialized Initialized Held SCRDR Initialized Initialized Initialized Initialized Initialized Held SCSCMR Initialized Initialized Initialized Initialized Initialized Held INTEVT2 Undefined Undefined Held Held Held Held INTC IRR0 Initialized Initialized Held Held Held Held IRR1 Initialized ...

Page 653: ...ized Initialized Held ADC ADDRAL Initialized Initialized Initialized Initialized Initialized Held ADDRBH Initialized Initialized Initialized Initialized Initialized Held ADDRBL Initialized Initialized Initialized Initialized Initialized Held ADDRCH Initialized Initialized Initialized Initialized Initialized Held ADDRCL Initialized Initialized Initialized Initialized Initialized Held ADDRDH Initial...

Page 654: ... PJDR Initialized Held Held Held Held Held SCPDR Initialized Held Held Held Held Held SCSMR2 Initialized Initialized Initialized Initialized Initialized Held SCIF SCBRR2 Initialized Initialized Initialized Initialized Initialized Held SCSCR2 Initialized Initialized Initialized Initialized Initialized Held SCFTDR2 Undefined Undefined Undefined Undefined Undefined Held SCSSR2 Initialized Initialized...

Page 655: ...tr 55 to 125 C Cautions Operating the chip in excess of the absolute maximum rating may result in permanent damage Order of turning on or off 1 9 V power Vcc Vcc PLL1 Vcc PLL2 Vcc RTC and 3 3 V power VccQ AVcc 1 The voltage of 1 9 V power should not be higher than that of 3 3 V power The period when only 3 3 V power is turned on should be less than 1 ms This period should be as short as possible 2...

Page 656: ...98 REJ09B0146 0500 Waveforms at power on are shown in the following figure Pin states undefined Max 1 ms 3 3 V 1 9 V 3 3 V power 1 9 V power RESETP All other pins Note Except power GND clock related and analog pins Pin states undefined Power on reset state Power On Sequence ...

Page 657: ... 05 V Icc 2 250 400 Vcc 1 9 V Iφ 133 MHz Normal operation IccQ 3 20 40 VccQ 3 3 V Bφ 33 MHz Icc 2 15 30 In sleep mode 1 IccQ 3 10 20 mA Bφ 33 MHz VccQ 3 3 V Vcc 1 9 V Icc 2 40 125 IccQ 3 10 25 Ta 25 C RTC on VccQ 3 3 V Vcc 1 9 V Icc 2 35 110 In standby mode IccQ 3 10 25 Ta 25 C RTC off 5 VccQ 3 3 V Vcc 1 9 V Current dissipation RTC current Icc RTC 4 15 µA Vcc RTC 1 9 V RESETP RESETM NMI IRQ5 to IR...

Page 658: ...put pins VIL 0 3 VccQ 0 2 V Input leak current All input pins I Iin I 1 0 µA Vin 0 5 to VccQ 0 5 V Three state leak current I O all output pins off condition I Isti I 1 0 µA Vin 0 5 to VccQ 0 5 V 2 4 VccQ 3 0 V IOH 200 µA Output high voltage All output pins VOH 2 0 VccQ 3 0 V IOH 2 mA Output low voltage All output pins VOL 0 55 V VccQ 3 6 V IOL 1 6 mA Pull up resistance Port pin Ppull 30 60 120 kΩ...

Page 659: ...VssQ Current dissipation values shown are the values at which all output pins are without load under conditions of VIH min VccQ 0 5 V VIL max 0 5 V 1 No external bus cycles except refresh cycles 2 Total current of Vcc Vcc PLL1 and Vcc PLL2 3 Current of VccQ 4 Current of Vcc RTC 5 Only in software standby mode Table 24 3 Permitted Output Current Values Conditions VccQ 3 3 0 3 V Vcc 1 9 0 15 V AVcc ...

Page 660: ...p Max Unit Remarks CPU cache TLB 25 133 34 External bus 25 66 67 Operating frequency Peripheral module f 6 25 33 34 MHz 24 3 1 Clock Timing Table 24 5 Clock Timing Item Symbol Min Max Unit Figure EXTAL clock input frequency clock mode 0 fEX 25 66 67 MHz EXTAL clock input cycle time clock mode 0 tEXcyc 15 40 ns EXTAL clock input frequency clock mode 1 fEX 6 25 16 67 MHz EXTAL clock input cycle time...

Page 661: ...CKOF 5 ns 24 3 Power on oscillation settling time tOSC1 10 ms 24 4 RESETP setup time at the power on or at the release from standby mode tRESPS 20 ns RESETM setup time at the release from standby mode tRESMS 0 ns RESETP assert time at the power on or at the release from standby mode tRESPW 20 tcyc RESETM assert time at the release from standby mode tRESMW 20 tcyc 24 4 24 5 Standby return oscillati...

Page 662: ...Q 1 2 VCCQ VIL VIL EXTAL input Note The clock input from the EXTAL pin Figure 24 1 EXTAL Clock Input Timing tCKIH tCKIF tCKIR tCKIL tCKIcyc VIH 1 2 VCCQ 1 2 VCCQ VIH VIL VIH VIL CKIO input Figure 24 2 CKIO Clock Input Timing tcyc tCKOL tCKOH VIH 1 2VCCQ CKIO output 1 2VCCQ tCKOR tCKOF VOH VOL VOL VOH Figure 24 3 CKIO Clock Output Timing ...

Page 663: ...2 Oscillation settling time becomes tOSC1 tPLL1 min 100 µs except in clock mode 2 CKIO internal clock Stable oscillation Figure 24 4 Power On Oscillation Settling Time CKIO internal clock Stable oscillation Standby tOSC2 tRESPW MW tRESPS MS RESETP RESETM Note Oscillation settling time in the Clock mode 2 and Oscillation halt mode Figure 24 5 Oscillation Settling Time at Standby Return Return by Re...

Page 664: ...illation settling time in the Clock mode 2 and Oscillation halt mode Figure 24 6 Oscillation Settling Time at Standby Return Return by NMI CKIO internal clock Stable oscillation Standby tOSC4 IRQ4 to IRQ0 Note Oscillation settling time in the Clock mode 2 and Oscillation halt mode Figure 24 7 Oscillation Settling Time at Standby Return Return by IRQ or IRL ...

Page 665: ...1 PLL synchronization Figure 24 8 PLL Synchronization Settling Time by Reset or NMI at the Returning from Standby Mode Return by Reset or NMI EXTAL input or CKIO input Stable input clock IRQ4 to IRQ0 IRL3 to IRL0 interrupt request Stable input clock Normal Normal PLL output CKIO output Internal clock STATUS 0 STATUS 1 Note Oscillation settling time in the Clock mode 0 1 7 and Oscillation halt mode...

Page 666: ...8 of 698 REJ09B0146 0500 EXTAL input 1 PLL output CKIO output 2 Internal clock Multiplication rate modified tPLL2 Notes 1 CKIO input in clock mode 7 2 PLL output in clock mode 7 Figure 24 10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified ...

Page 667: ... 10 ns Bus tri state delay time 1 tBOFF1 0 15 ns Bus tri state delay time 2 tBOFF2 0 15 ns Bus buffer on time 1 tBON1 0 15 ns Bus buffer on time 2 tBON2 0 15 ns 24 14 24 15 Notes 1 RESETP NMI and IRQ5 to IRQ0 are asynchronous Changes are detected at the clock fall when the setup shown is used When the setup cannot be used detection can be delayed until the next clock falls 2 The upper limit of the...

Page 668: ... tRESPS MS tRESPS MS RESETP RESETM tRESPW MW Figure 24 11 Reset Input Timing CKIO RESETP RESETM tRESPH MH tRESPS MS VIH VIL NMI tNMIH tNMIS VIH VIL IRQ5 to IRQ0 tIRQH tIRQS VIH VIL Figure 24 12 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD IRQOUT Figure 24 13 IRQOUT IRQOUT IRQOUT IRQOUT Timing ...

Page 669: ... CAS CSn WEn BS A25 to A0 D31 to D0 tBACKD tBOFF2 tBOFF1 tBON1 tBACKD tBON2 tBREQH tBREQH tBREQS tBREQS Figure 24 14 Bus Release Timing CKIO tSTD tBOFF2 tBOFF1 tSTD tBON2 tBON1 Normal mode Standby mode Normal mode STATUS 0 STATUS 1 RD RD WR RAS CAS CSn WEn BS A25 to A0 D31 to D0 Figure 24 15 Pin Drive Timing at Standby ...

Page 670: ...s 24 16 to 24 21 24 40 to 24 46 Read data setup time 2 tRDS2 5 ns 24 22 to 24 25 24 30 to 24 33 Read data hold time 1 tRDH1 0 ns 24 16 to 24 21 24 40 to 24 46 Read data hold time 2 tRDH2 2 ns 24 22 to 24 25 24 30 to 24 33 Write enable delay time tWED 10 ns 24 16 to 22 18 24 40 to 24 41 Write data delay time 1 tWDD1 12 ns 24 16 to 24 18 24 40 to 24 41 24 44 to 24 46 Write data delay time 2 tWDD2 1 ...

Page 671: ...delay time tCKED 1 5 10 ns 24 38 ICIORD delay time tICRSD 10 ns 24 44 to 24 46 ICIOWR delay time tICWSD 10 ns 24 44 to 24 46 IOIS16 setup time tIO16S 6 ns 24 45 24 46 IOIS16 hold time tIO16H 4 ns 24 45 24 46 DACK delay time 1 tDAKD1 12 ns 24 16 to 24 36 24 39 to 24 46 DACK delay time 2 tDAKD2 10 ns 24 16 to 24 18 24 20 to 24 21 ...

Page 672: ... read WEn D31 to D0 write BS T2 tAD tAH tAD tCSD1 tRWD tRSD tCSD2 tWED tWDD1 tRDS1 tBSD tBSD tDAKD1 tDAKD2 tRDH1 tRDH1 tWED tRSD tAH tRWH tRWD tWDH1 tRWH tRWH tAH tWDH3 DACKn read write tAS Note tRDH1 Stipulated from the faster negate timing of CSn or RD tAH Stipulated from the slower negate timing of CSn RD or WEn Figure 24 16 Basic Bus Cycle No Wait ...

Page 673: ...500 T1 Tw T2 CKIO A25 to A0 CSn RD WR RD D31 to D0 read WEn D31 to D0 write BS WAIT tAD tAD tRWD tRWH tAH tAH tRSD tCSD1 tWED tWDD1 tBSD tWTS tWTH tBSD tRDS1 tCSD2 tWED tRSD tRDH1 tRDH1 tRWD tAH tRWH tWDH3 tWDH1 tRWH tDAKD1 tDAKD2 DACKn read write tAS Figure 24 17 Basic Bus Cycle One Wait ...

Page 674: ...write BS WAIT tAD tAD tRWD tRSD tWED tWTS tWTH tBSD tBSD tRDS1 tWTS tWTH tCSD1 tCSD2 tRSD tWED tRDH1 tAH tRWH tRDH1 tAH tRWH tRWD tRWH tAH tWDH3 tWDH1 tDAKD1 tDAKD2 DACKn tWDD1 read write tAS Note tRDH1 Stipulated from the faster negate timing of CSn or RD tAH Stipulated from the slower negate timing of CSn RD or WEn Figure 24 18 Basic Bus Cycle External Wait ...

Page 675: ...tRWD tBSD tBSD tAH tBSD tDAKD1 tDAKD2 tCSD2 tRSD tRDS1 tWTS tWTH tRDS tRSD T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 tRSD tRDH1 tRSD tAH tRDH1 tRWH tAH tRWH tRWD tRDH1 tBSD Note In the write cycle the basic bus cycle the basic bus cycle is performed tRDH1 Stipulated from the faster negate timing of CSn or RD tAH Stipulated from the slower negate timing of CSn RD or WEn Figure 24 19 Burst ROM Bus Cycle No Wait...

Page 676: ...RD D31 to D0 BS WAIT DACKn tAD tAD tAD tCSD1 tRWH tRWD tRSD tRSD tRDH1 tRDH1 tRDS1 tDAKD1 tDAKD2 tBSD tBSD tWTS tWTH tWTS tWTH T1 Tw Tw TB2 TB1 TB2 Tw T2 T2 tCSD2 tRDS1 tRSD tRSD tAH tAH tRDH1 tAH tRSD tRWD tRWH tRDH1 Note In the write cycle the basic bus cycle is performed tBSD tBSD Figure 24 20 Burst ROM Bus Cycle Two Waits ...

Page 677: ...tCSD2 tRWD tRWH tRDH1 tAH tAH tRWD tRSD tRSD1 tAH tAD tBSD tBSD tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH tBSD tBSD tRDS1 tRDH1 tRSD tDAKD1 tDAKD2 tRDH1 tRWH tRSD1 tRDS Note In the write cycle the basec bus cycle is performed tRDH1 Stipulated from the faster negate timing of CSn or RD tAH Stipulated from the slower negate timing of CSn RD or WEn Figure 24 21 Burst ROM Bus Cycle External Wait ...

Page 678: ... CSn RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tr tAD Tc1 Tc2 Tpc D31 to D0 tAD tAD tAD tAD tCSD3 tRWD tCSD3 tRWD tRASD tDQMD tDQMD tRDH2 tBSD tBSD High tRDS2 tRASD tCASD tCASD tAD tAD tAD DACKn tDAKD1 tDAKD1 Read A command Column address Row address Row address Row address Figure 24 22 Synchronous DRAM Read Bus Cycle RCD 0 CAS Latency 1 TPC 0 ...

Page 679: ...E High A25 to A16 A15 to A0 Tr Trw Trw Tc1 Tcw Td1 Tpc Tpc D31 to D0 tAD tAD tAD tAD tCSD3 tRWD tDQMD tRDH2 tBSD tBSD tRDS2 tCSD3 tRWD tRASD tDQMD tRASD tCASD tCASD tAD tAD tAD tAD DACKn tDAKD1 tDAKD1 Row address Row address Row address Column address Read A command Figure 24 23 Synchronous DRAM Read Bus Cycle RCD 2 CAS Latency 2 TPC 1 ...

Page 680: ...Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 Tpc Tpc D31 to D0 tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD tDQMD tBSD tBSD tRDS2 tRDH2 tRDS2 tRDH2 tDQMD tRASD tCASD tCASD tDAKD1 tDAKD1 DACKn Column address 1 4 Read command Row address Row address Row address Read A command Figure 24 24 Synchronous DRAM Read Bus Cycle Burst Read Single Read 4 RCD 0 CAS Latency 1 TPC 1 ...

Page 681: ...1 Tc2 Tc3 Tc4 Td1 Td2 Td3 Td4 Tpc D31 to D0 read tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tRWD tDQMD tRDS2 tBSD tBSD tRDH2 tRDS2 tRDH2 tCSD3 tRWD tRASD tRASD tCASD tDQMD tCASD High Column address 1 4 tDAKD1 tDAKD1 DACKn Row address Row address Row address Read command Figure 24 25 Synchronous DRAM Read Bus Cycle Burst Read Single Read 4 RCD 1 CAS Latency 3 TPC 0 ...

Page 682: ...DQMxx CKE A25 to A16 A15 to A0 Tr Tc1 Trwl Tpc High D31 to D0 tAD Column address tAD tAD tCSD3 tRWD tRASD tAD tAD tAD tAD tAD tCSD3 tRWD tRWD tRASD tCASD tDQMD tWDD2 tBSD tDQMD tWDH2 tBSD tCASD tDAKD1 tDAKD1 DACKn Row address Row address Row address Write A command Figure 24 26 Synchronous DRAM Write Bus Cycle RCD 0 TPC 0 TRWL 0 ...

Page 683: ... to A16 A15 to A0 Tr Trw Trw Tc1 Trwl Trwl Tpc Tpc High D31 to D0 tAD tAD tAD tAD tAD tAD tAD tCSD3 tRWD tRWD tAD tAD tAD tCSD3 tRWD tRASD tRASD tDQMD tWDD2 tBSD tCASD tDQMD tWDH2 tBSD tCASD tDAKD1 tDAKD1 DACKn Row address Row address Row address Column address Write A command Figure 24 27 Synchronous DRAM Write Bus Cycle RCD 2 TPC 1 TRWL 1 ...

Page 684: ...c1 Tc2 Tc3 Tc4 Trwl Tpc Tpc High D31 to D0 tAD tAD tAD tAD tAD tCSD3 tRWD tRWD tAD tAD tAD tAD tCSD3 tRWD tRASD tRASD tDQMD tWDD2 tWDD2 tBSD tCASD tDQMD tWDH2 tBSD tCASD Column address 1 4 tDAKD1 tDAKD1 DACKn Write A command Row address Row address Row address Write command Figure 24 28 Synchronous DRAM Write Bus Cycle Burst Mode Single Write 4 RCD 0 TPC 1 TRWL 0 ...

Page 685: ... Tr Trw Tc1 Tc2 Tc3 Td4 Trwl Tpc D31 to D0 Write command Column address 1 4 tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD tDQMD tBSD tBSD tWDD2 tWDD2 tWDH2 tDQMD tRASD tCASD tCASD tDAKD1 tDAKD1 DACKn Row address Row address Row address Write A command Figure 24 29 Synchronous DRAM Write Bus Cycle Burst Mode Single Write 4 RCD 1 TPC 0 TRWL 0 ...

Page 686: ...E A25 to A16 A15 to A0 Tnop Tc1 Tc2 Td1 Tc3 Td2 Tc4 Td3 Td4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD2 tDQMD tDQMD tBSD tBSD High tAD tAD tAD tRDS2 tRDH2 tRDS2 tRDH2 tCASD2 tCASD2 tAD Row address Read command Column address tDAKD1 tDAKD1 DACKn Figure 24 30 Synchronous DRAM Burst Read Bus Cycle RAS Down Same Row Address CAS Latency 1 ...

Page 687: ...RWD tDQMD tBSD tRDH2 tRDS2 tRDH2 tRDS2 tBSD tRASD tCASD tDQMD tRWD tCSD3 tAD tAD tAD Tc1 Tc2 Tc3 Td1 Tc4 Td2 Td3 Td4 CKIO A12 or A11 A15 to A0 CSn RD WR RAS CAS DQMxx D31 to D0 BS CKE Row address DACKn tDAKD1 tDAKD1 Column address Read command Figure 24 31 Synchronous DRAM Burst Read Bus Cycle RAS Down Same Row Address CAS Latency 2 ...

Page 688: ...c2 Td1 Tc3 Td2 Tc4 Td3 Td4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD tRASD tDQMD tDQMD tDQMD tBSD tBSD tDAKD1 tDAKD1 HIGH tAD tAD tAD tAD tAD tAD tRDS2 tRDH2 tRDS2 tRDH2 tAD Row address Read command Row address Row address Column address tCASD tCASD DACKn Figure 24 32 Synchronous DRAM Burst Read Bus Cycle RAS Down Different Row Address TPC 0 RCD 0 CAS Latency 1 ...

Page 689: ...d1 Tc3 Td2 Tc4 Td3 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD tRASD tRASD tRASD tDQMD tDQMD tDQMD tBSD tBSD HIGH tAD tAD tAD tAD tAD tAD tRDS2 tRDH2 tRDS2 tRDH2 tAD Td4 Row address Read command Column address tCASD tCASD Row address Row address tDAKD1 tDAKD1 DACKn Figure 24 33 Synchronous DRAM Burst Read Bus Cycle RAS Down Different Row Address TPC 1 RCD 0 CAS Latency 1 ...

Page 690: ...n RAS CAS BS DQMxx CKE A25 to A16 A15 to A0 Tc1 Tc2 Tc3 Tc4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRASD tRASD tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD HIGH tAD tAD tAD tCASD tCASD tAD Row address Write command Column address tDAKD1 tDAKD1 DACKn Figure 24 34 Synchronous DRAM Burst Write Bus Cycle RAS Down Same Row Address ...

Page 691: ... to A16 A15 to A0 Tp Tr Tc1 Tc2 Tc3 Tc4 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRWD tRASD tRASD tDQMD tDQMD tDQMD tBSD tBSD HIGH tAD tAD tAD tAD tAD tAD tAD Row address Write command Row address Row address Column address tCASD tCASD tDAKD1 tDAKD1 DACKn Figure 24 35 Synchronous DRAM Burst Write Bus Cycle RAS Down Different Row Address TPC 0 RCD 0 ...

Page 692: ... Tr Trw Tc1 Tc2 Tc3 D31 to D0 tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRWD tRASD tRASD tRASD tRASD tDQMD tDQMD tDQMD tWDD2 tWDD2 tBSD tBSD HIGH tAD tAD tAD tAD tAD tAD Td4 Write command Column address tCASD tCASD Row address Row address tAD tAD Row address tDAKD1 tDAKD1 DACKn Figure 24 36 Synchronous DRAM Burst Write Bus Cycle RAS Down Different Row Address TPC 1 RCD 1 ...

Page 693: ...TRrw Tpc Tpc TRrw tCSD3 tCSD3 tRASD tRASD tRASD tRASD tCASD tCASD tRWD tRWD High Figure 24 37 Synchronous DRAM Auto Refresh Timing TRAS 1 TPC 1 Tpc TRa1 TRs2 TRs2 TRs3 CKIO CKE CSn RAS CAS RD WR tRWD tRWD tCASD tRASD tCASD tCSD3 tRASD Tp tCSD3 tRASD tRASD Tpc Tpc tCKED tCKED tRWD Figure 24 38 Synchronous DRAM Self Refresh Cycle TPC 0 ...

Page 694: ... to D0 A11 A10 A10 to A2 A9 to A1 TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 High CKE tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tCSD3 tRWD tRWD tRWD tRASD tRASD tRASD tRASD tCASD tCASD tDAKD1 tDAKD1 DACKn Note Items in parentheses apply to 16 bit bus width connections Figure 24 39 Synchronous DRAM Mode Register Write Cycle ...

Page 695: ...46 0500 24 3 7 PCMCIA Timing Tpcm1 Tpcm2 CKIO A25 to A0 CExx RD WR RD D15 to D0 WE1 D15 to D0 BS DACKn tAD tAD tCSD1 tCSD1 tRWD tRSD tRSD tRWD tDAKD1 tDAKD1 tWED tWDD1 tWED tRDS1 tRDH1 tBSD tBSD tWDH4 tWDH1 read read write write Figure 24 40 PCMCIA Memory Bus Cycle TED 0 TEH 0 No Wait ...

Page 696: ...pcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w A25 to A0 CExx RD WR RD read D15 to D0 read WE1 write D15 to D0 write BS DACKn WAIT tAD tCSD1 tRWD tAD tCSD1 tRWD tWDH4 tRSD tRSD tDAKD1 tDAKD1 tWED tWDD1 tWED tWDH1 tRDH1 tBSD tWTS tWTH tWTS tWTH tRDS1 tBSD Figure 24 41 PCMCIA Memory Bus Cycle TED 2 TEH 1 One Wait External Wait ...

Page 697: ...m2 A25 to A4 A3 to A0 CExx RD WR RD D15 to D0 BS DACKn tAD tAD tCSD1 tRWD tCSD1 tRWD tAD tAD tAD tAD tDAKD1 tRSD tRSD tRDH1 tRDH1 tRSD tRSD tBSD tBSD tBSD tBSD tRDS1 tRDS1 Note Even though burst mode is set write cycle operation is the same as in normal mode read read tDAKD1 Figure 24 42 PCMCIA Memory Bus Cycle Burst Read TED 0 TEH 0 No Wait ...

Page 698: ...o A0 CExx RD WR RD read D15 to D0 read BS DACKn WAIT tAD tAD tCSD1 tRWD tCSD1 tDAKD1 tRWD tAD tAD tAD tRSD tRSD tRSD tRSD tDAKD1 tBSD tBSD tBSD tBSD tRDS1 tRDH1 tRDH1 tRDS1 tWTS tWTH tWTS tWTS tWTH tWTH Note Even though burst mode is set the write cycle operation is the same as in normal mode Figure 24 43 PCMCIA Memory Bus Cycle Burst Read TED 1 TEH 1 Two Waits Burst Pitch 3 ...

Page 699: ...9B0146 0500 Tpci1 Tpci2 CKIO A25 to A0 CExx RD WR ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS DACKn tAD tAD tCSD1 tCSD1 tRWD tICRSD tICRSD tRWD tDAKD1 tDAKD1 tICWSD tWDD1 tICWSD tRDH1 tRDS1 tBSD tBSD tWDH1 tWDH4 Figure 24 44 PCMCIA I O Bus Cycle TED 0 TEH 0 No Wait ...

Page 700: ...1w Tpci2 Tpci2w A25 to A0 CExx RD WR ICIORD read D15 to D0 read ICIOWR write D15 to D0 write BS DACKn WAIT IOIS16 tAD tCSD1 tRWD tAD tCSD1 tRWD tICRSD tICRSD tDAKD1 tDAKD1 tICWSD tWDD1 tICWSD tWDH1 tWDH4 tRDH1 tBSD tBSD tWTS tWTH tWTS tWTH tIO16S tIO16H tRDS1 Figure 24 45 PCMCIA I O Bus Cycle TED 2 TEH 1 One Wait External Wait ...

Page 701: ...R ICIORD D15 to D0 ICIOWR D15 to D0 BS WAIT IOIS16 DACKn tAD tAD tCSD1 tCSD1 tRWD tRWD tWDD1 tWDH4 tBSD tAD tAD tICRSD tICRSD tICRSD tICRSD tICWSD tWTS tWTH tWTH tIO16S tIO16H tAD tRDS1 tCSD1 tDAKD1 tDAKD1 tRDS1 tICWSD tICWSD tRDH1 tRDH1 tWDH1 tBSD tWTS read read write write tBSD tBSD tWDH3 tWDD2 tICWSD Figure 24 46 PCMCIA I O Bus Cycle TED 1 TEH 1 One Wait Bus Sizing ...

Page 702: ...e time tSCKR 1 5 Input clock fall time tSCKF 1 5 tcyc Input clock pulse width tSCKW 0 4 0 6 tscyc 24 50 Transmission data delay time tTXD 100 Receive data setup time clock synchronization tRXS 100 Receive data hold time clock synchronization tRXH 100 RTS delay time tRTSD 100 CTS setup time clock synchronization tCTSS 100 SCI CTS hold time clock synchronization tCTSH 100 ns 24 51 Output data delay ...

Page 703: ...nput Figure 24 47 TCLK Input Timing tTCKS tTCKS tTCKWH tTCKWL CKIO TCLK input Figure 24 48 TCLK Clock Input Timing RTC crystal oscillator Stable oscillation VCC VCCmin tROSC Figure 24 49 Oscillation Settling Time at RTC Crystal Oscillator Power on tSCKW tSCKR tSCKF tScyc SCK Figure 24 50 SCK Input Clock Timing ...

Page 704: ...on RxD data reception tRXH tRXS tRTSD RTS CTS tCTSH tCTSS Figure 24 51 SCI I O Timing in Clock Synchronous Mode tPORTS1 CKIO tPORTH1 tPORTS2 tPORTH2 tPORTD tPORTS3 tPORTH3 PORT 7 to 0 read B P clock ratio 1 1 PORT 7 to 0 read B P clock ratio 2 1 PORT 7 to 0 read B P clock ratio 4 1 PORT 7 to 0 write Figure 24 52 I O Port Timing ...

Page 705: ...24 Electrical Characteristics Rev 5 00 May 29 2006 page 657 of 698 REJ09B0146 0500 DREQn CKIO tDRQS tDRQH Figure 24 53 DREQ DREQ DREQ DREQ Input Timing DRAK0 1 CKIO tDRAKD tDRAKD Figure 24 54 DRAK Output Timing ...

Page 706: ... 4 ns 24 55 TRST setup time tTRSTS 12 ns TRST hold time tTRSTH 50 tcyc 24 56 TDI setup time tTDIS 10 ns TDI hold time tTDIH 10 ns TMS setup time tTMSS 10 ns TMS hold time tTMSH 10 ns TDO delay time tTDOD 16 ns 24 57 ASEMD0 setup time tASEMDH 12 ns ASEMD0 hold time tASEMDS 12 ns 24 58 AUDCK cycle time tAUDCYC 66 ms 24 59 AUDATA delay time tAUDD 12 ns AUDSYNC delay time tAUSYD 12 ns tTCKL tTCKf VIL ...

Page 707: ...of 698 REJ09B0146 0500 RESETP tTRSTS tTRSTH TRST Figure 24 56 TRST Input Timing Reset Hold TCK TDI TMS tTDIS tTMSS tTDIH tTCKcyc tTMSH tTDOD TDO Figure 24 57 H UDI Data Transfer Timing tASEMDOS tASEMDOH RESETP ASEMD0 Figure 24 58 ASEMD0 ASEMD0 ASEMD0 ASEMD0 Input Timing ...

Page 708: ...verter Timing Table 24 10 A D Converter Timing Item Symbol Min Typ Max Unit Figure External trigger input pulse width tTRGW 2 tcyc External trigger input start delay time tTRGS 50 ns 24 60 CKS 0 129 Input sampling time CKS 1 tSPL 65 tcyc CKS 0 17 28 A D conversion start delay time CKS 1 tD 10 17 tcyc CKS 0 514 525 A D conversion time CKS 1 tCONV 259 266 tcyc 24 61 tcyc Pφ cycle ...

Page 709: ...put ADCR 1 state tTRGW tTRGS Figure 24 60 External Trigger Input Timing Pφ Write signal ADF 1 Input sampling timing Legend tD A D conversion start delay tSPL Input sampling time tCONV A D conversion time Notes 1 ADCSR write cycle 2 ADCSR address Address 2 tD tSPL tCONV Figure 24 61 A D Conversion Timing ...

Page 710: ...SETP RESETM ASEMD0 ADTRG TRST CA NMI IRQ5 to IRQ0 CKIO and MD5 to MD0 are within VssQ to VccQ Input rise and fall times 1 ns IOL IOH CL VREF LSI output pin DUT output Notes CL is the total value that includes the capacitance of measurement instruments etc and is set as follows for each pin 30 pF CKIO RASx CASxx CS0 CS2 to CS6 CE2A CE2B BACK 50 pF All other pins IOL and IOH are the values shown in ...

Page 711: ...is connected to this LSI s pins is shown below The graph shown in figure 24 63 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device If the connected load capacitance exceeds the range shown in figure 24 63 the graph will not be a straight line 3 2 1 0 0 10 20 30 40 50 Load Capacitance pF Delay Time ns 50 pF stipulated 3...

Page 712: ...log input capacitance 20 pF Permissible signal source single source impedance 5 kΩ Nonlinearity error 3 0 LSB Offset error 2 0 LSB Full scale error 2 0 LSB Quantization error 0 5 LSB Absolute accuracy 4 0 LSB 24 5 D A Converter Characteristics Table 24 12 lists the D A converter characteristics Table 24 12 D A Converter Characteristics Conditions VccQ 3 3 0 3 V Vcc 1 9 0 15 V AVcc 3 3 0 3 V Ta 20 ...

Page 713: ...enable Input with enable WAIT BREQ Input data Input enable Pull up enable VccQ Input with enable Pull up with enable RxD0 SCPT 0 RxD2 SCPT 2 AUDCK PTG 4 Input data Schmitt trigger input ASEMD0 MD 5 0 RESERM NMI RESETP CA Input data Pull up enable Input data Input enable VccQ Input with enable Schmitt trigger input Pull up with enable CTS2 IRQ5 SCPT 5 ADTRG PTG 5 ...

Page 714: ...PTJ 1 0 Input data Input enable Input enable Input analog data Output enable Output analog data Input with enable Analog input with enable Analog output with enable AN 3 2 DA 0 1 PTJ 3 2 Output data Output enable VccQ VssQ 3 state output RD WE0 DQMLL WE1 DQMLU WE CS0 BACK TxD0 SCPT 0 TxD2 SCPT 2 Output data Output enable VccQ VccQ VssQ Pull up enable 3 state output Pull up with enable A 25 12 ...

Page 715: ...D 31 24 PTB 7 0 D 23 16 PTA 7 0 D 15 0 A 11 0 BS PTC 0 WE2 DQMUL ICIORD PTC 1 WE3 DQMUU ICIOWR PTC 2 CS 4 2 PTC 5 3 CS5 CE1A PTC 6 CS6 CE1B PTC 7 CE2A PTD 6 CE2B PTD 7 RASL PTD 0 RASU PTD 1 CASL PTD 2 CASU PTD 3 CKE PTD 4 IOIS16 PTD 5 DACK 1 0 PTE 1 0 DRAK 1 0 PTE 3 2 AUDATA 3 0 PTF 3 0 AUDSYNC PTF 4 TDO PTF 5 ASEBRKAK PTF 6 STATUS 1 0 PTE 5 4 TCLK PTE 6 IRQOUT PTE 7 SCK0 SCPT 1 SCK2 SCPT 3 RTS2 S...

Page 716: ... VccQ VssQ Input data Input data Input enable Pull up enable VccQ 3 state output Input with enable Schmitt trigger input Pull up with enable TDI PTG 0 TCK PTG 1 TMS PTG 2 TRST PTG 3 IRQ 3 0 IRL 3 0 PTH 3 0 IRQ4 PTH 4 Clock out XTAL2 EXTAL2 Clock enable 32 kHz crystal oscillation input EXTAL2 Clock out XTAL EXTAL Clock enable Select Switch between crystal resonator and crystal oscillator input inpu...

Page 717: ...s Released EXTAL I I I I I XTAL O 1 O 1 O 1 O 1 O 1 CKIO IO 1 IO 1 IO 1 12 IO 1 IO 1 EXTAL2 I I I I I XTAL2 O O O O O Clock CAP1 CAP2 RESETP I I I I I RESETM I I I I I BREQ I I I I BACK O O O O L MD 5 0 I I I I I CA I I I I System control STATUS 1 0 PTE 5 4 O OP 3 OP 3 OP 3 OP 3 Interrupt IRQ 3 0 IRL 3 0 PTH 3 0 I 8 I I I I IRQ4 PTH 4 I 8 I I I I NMI I I I I I IRQOUT PTE 7 H OP 3 ZK 3 OP 3 OP 3 Ad...

Page 718: ... H OP 3 ZOK 4 OP 3 ZOP 4 WE0 DQMLL H O ZH 11 O Z WE1 DQMLU WE H O ZH 11 O Z WE2 DQMUL ICIORD PTC 1 H OP 3 ZH 11 K 3 OP 3 ZP 3 WE3 DQMUU ICIOWR PTC 2 H OP 3 ZH 11 K 3 OP 3 ZP 3 RD WR H O ZH 11 O Z RD H O ZH 11 O Z CKE PTD 4 H OP 3 OK 3 OP 3 OP 3 Bus control WAIT Z I Z I Z DREQ0 PTH 5 I ZI 7 Z I I DACK0 PTE 0 O OP 3 ZK 3 OP 3 OP 3 DRAK0 PTE 2 O OP 3 ZH 11 K 3 OP 3 OP 3 DREQ1 PTH 6 I ZI 7 Z I I DACK1...

Page 719: ...S16 PTD 5 I I Z I I ADTRG PTG 5 V 8 I IZ I I H UDI TCK PTG 1 IV I IZ I I TDI PTG 0 IV I IZ I I TMS PTG 2 IV I IZ I I TRST PTG 3 IV I IZ I I AUDSYNC PTF 4 OV OP 3 OK 3 OP 3 OP 3 TDO PTF 5 OV OP 3 OK 3 OP 3 OP 3 AUDCK PTG 4 IV I IZ I I AUDATA 3 0 PTF 3 0 IV I IZ I I ASEBRKAK PTF 6 OV OP 3 OP 3 OP 3 OP 3 ASEMD0 I I Z I I AN 1 0 PTJ 1 0 Z ZI 7 Z I I Analog AN 3 2 DA 0 1 PTJ 3 2 Z ZI 7 OZ 2 IO 9 IO 9 L...

Page 720: ... used I or O when the port function is not used depending on register setting 6 Depending on register setting 7 I or O when the port function is used 8 Input Schmitt buffers of IRQ 5 0 and ADTRG are on Input Schmitt buffers of the other inputs e g PTH CTS2 that are shared with these pins are off 9 O when DA output is enabled otherwise depends on a register setting 10 In the standby mode Z or L dep...

Page 721: ...A D15 to D0 26 28 29 30 31 32 33 34 35 36 38 40 41 42 43 44 L2 L4 M1 M2 M3 M4 N1 N2 N3 N4 P2 R1 R2 P4 T1 T2 I O Data bus A25 to A0 76 75 74 72 70 69 68 67 66 65 64 62 60 59 58 57 56 55 54 53 52 50 48 47 46 45 T11 P10 T10 R9 T9 P9 U8 T8 R8 P8 U7 R7 U6 T6 R6 P6 U5 T5 R5 P5 U4 R4 T3 R3 U2 U1 O Address bus BS PTC 0 77 R11 O I O Bus cycle start signal input output port C RD 78 P11 O Read strobe WE0 DQM...

Page 722: ...s CAS SDRAM input output port D CKE PTD 4 100 N17 O I O CK enable SDRAM input output port D IOIS16 PTD 5 101 M14 I I O IOIS16 PCMCIA input port D BACK 102 M15 O Bus acknowledge BREQ 103 M16 I Bus request WAIT 104 M17 I Hardware wait request DACK0 PTE 0 105 L14 O I O DMA acknowledge 0 input output port E DACK1 PTE 1 106 L15 O I O DMA acknowledge 1 input output port E DRAK0 PTE 2 107 L16 O I O DMA r...

Page 723: ...C port TxD2 SCPT 2 142 C13 O SCIF transmit data 2 SC port SCK0 SCPT 1 141 D13 I O SCI clock 0 SC port SCK2 SCPT 3 143 B13 I O SCIF clock 2 SC port RxD0 SCPT 0 145 D12 I SCI receive data 0 SC port RxD2 SCPT 2 146 C12 I SCIF receive data 2 SC port RTS2 SCPT 4 144 A13 O I O SCIF transmit request 2 SC port CTS2 IRQ5 SCPT 5 147 B12 I SCIF transmit clear external interruption request SC port RESETM 149 ...

Page 724: ... Internal power supply 1 9 V VCC RTC 1 C3 Power supply RTC power supply 1 9 V VCC PLL1 123 E17 Power supply PLL1 power supply 1 9 V VCC PLL2 128 D16 Power supply PLL2 power supply 1 9 V AVCC 175 B3 Power supply Analog power supply 3 3 V VSS Q 11 25 37 49 61 84 93 137 156 G2 L1 P1 U3 P7 R13 R17 A15 D9 Power supply Input output power supply 0 V VSS 19 71 115 130 148 J1 U9 J15 C16 D11 Power supply In...

Page 725: ...ve unconnected VCC PLL1 Power supply 1 9 VSS PLL1 Power supply 0 V When PLL2 is not used CAP2 Leave unconnected VCC PLL2 Power supply 1 9 V VSS PLL2 Power supply 0 V When on chip crystal oscillator is not used XTAL Leave unconnected When EXTAL pin is not used EXTAL Connect to VCCQ or VSSQ When A D converter is not used AN 3 0 Leave unconnected AVCC Power supply 3 3 V AVSS Power supply 0 V When har...

Page 726: ... 0 High High High High CASL PTD 2 High High High High CASU PTD 3 High High High High R High High High High WE0 DQMLL W Low Low High Low R High High High High WE1 WE DQMLU W High High Low Low R High High High High WE2 ICIORD DQMUL PTC 1 W High High High High R High High High High WE3 ICIOWR DQMUU PTC 2 W High High High High CE2A PTD 6 High High High High CE2B PTD 7 High High High High CKE Disabled ...

Page 727: ...High High High High High High High WE2 ICIORD DQMUL PTC 1 W High High Low High High Low Low R High High High High High High High WE3 ICIOWR DQMUU PTC 2 W High High High Low High Low Low CE2A PTD 6 High High High High High High High CE2B PTD 7 High High High High High High High CKE Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 ...

Page 728: ...SL PTD 2 High High High High CASU PTD 3 High High High High R High High High High WE0 DQMLL W Low High Low Low R High High High High WE1 WE DQMLU W High Low High Low R High High High High WE2 ICIORD DQMUL PTC 1 W High High High High R High High High High WE3 ICIOWR DQMUU PTC 2 W High High High High CE2A PTD 6 High High High High CE2B PTD 7 High High High High CKE Disabled Disabled Disabled Disable...

Page 729: ...High High High High High High High WE2 ICIORD DQMUL PTC 1 W High Low High High Low High Low R High High High High High High High WE3 ICIOWR DQMUU PTC 2 W Low High High High Low High Low CE2A PTD 6 High High High High High High High CE2B PTD 7 High High High High High High High CKE Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 ...

Page 730: ...h High High High CASL PTD 2 High High High High CASU PTD 3 High High High High R High High High High WE0 DQMLL W R High High High High WE1 WE DQMLU W R High High High High WE2 ICIORD DQMUL PTC 1 W R High High High High WE3 ICIOWR DQMUU PTC 2 W CE2A PTD 6 High High High High CE2B PTD 7 High High High High CKE Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 Di...

Page 731: ...igh WE2 ICIORD DQMUL PTC 1 W R High High High High High High High WE3 ICIOWR DQMUU PTC 2 W CE2A PTD 6 High High High High High High High CE2B PTD 7 High High High High High High High CKE Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 Disabled Disabled Disabled Disabled Disabled Disabled Disabled A25 t...

Page 732: ...High High High CASL PTD 2 High High High High CASU PTD 3 High High High High R High High High High WE0 DQMLL W R High High High High WE1 WE DQMLU W R High High High High WE2 ICIORD DQMUL PTC 1 W R High High High High WE3 ICIOWR DQMUU PTC 2 W CE2A PTD 6 High High High High CE2B PTD 7 High High High High CKE Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 Disa...

Page 733: ...igh WE2 ICIORD DQMUL PTC 1 W R High High High High High High High WE3 ICIOWR DQMUU PTC 2 W CE2A PTD 6 High High High High High High High CE2B PTD 7 High High High High High High High CKE Disabled Disabled Disabled Disabled Disabled Disabled Disabled WAIT Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 Enabled 1 IOIS16 Disabled Disabled Disabled Disabled Disabled Disabled Disabled A25 t...

Page 734: ...MLL WE0 W Low High High High Low High Low R High Low High High Low High Low DQMLU WE1 W High Low High High Low High Low R High High Low High High Low Low DQMUL WE2 ICIORD W High High Low High High Low Low R High High High Low High Low Low DQMUU WE3 ICIOWR W High High High Low High Low Low CE2A PTD 6 High High High High High High High CE2B PTD 7 High High High High High High High CKE High 2 High 2 ...

Page 735: ...L WE0 W High High High Low High Low Low R High High Low High High Low Low DQMLU WE1 W High High Low High High Low Low R High Low High High Low High Low DQMUL WE2 ICIORD W High Low High High Low High Low R Low High High High Low High Low 1 DQMUU WE3 ICIOWR W Low High High High Low High Low CE2A PTD 6 High High High High High High High CE2B PTD 7 High High High High High High High CKE High 2 High 2 ...

Page 736: ...igh High High High High High High R High High High High High High High High WE0 DQMLL W High High High High High High High High R High High High High High High High High WE1 WE DQMLU W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 ICIORD DQMUL PTC 1 W High High High High High High High High R High High High High High High High High WE3 ICIOWR DQMUU PTC 2 W High High...

Page 737: ...High High High High High High High High R High High High High High High High High WE1 WE DQMLU W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 ICIORD DQMUL PTC 1 W High High High High High High High High R High High High High High High High High WE3 ICIOWR DQMUU PTC 2 W High High High High Low Low Low Low CE2A PTD 6 High High High High High High High High CE2B PTD 7...

Page 738: ...gh High High High High High High R High High High High High High High High WE0 DQMLL W High High High High High High High High R High High High High High High High High WE1 WE DQMLU W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 ICIORD DQMUL PTC 1 W High High High High High High High High R High High High High High High High High WE3 ICIOWR DQMUU PTC 2 W High High ...

Page 739: ...igh High High High High High High WE1 WE DQMLU W Low Low Low Low High High High High R High High High High Low Low Low Low WE2 ICIORD DQMUL PTC 1 W High High High High High High High High R High High High High High High High High WE3 ICIOWR DQMUU PTC 2 W High High High High Low Low Low Low CE2A 3 PTD 6 High High High High High High High High CE2B 3 PTD 7 High High Low Low High High Low Low CKE Dis...

Page 740: ...endix Rev 5 00 May 29 2006 page 692 of 698 REJ09B0146 0500 C Product Lineup Model Marking Package HD6417706F133 176 pin plastic LQFP FP 176C PLQP0176KD A HD6417706BP133 208 pin TFBGA TBP 208A TTBG0208JA A ...

Page 741: ... D E A2 HD A bp b1 c x y ZD ZE L1 Max Nom Min Dimension in Millimeters Symbol Reference 1 25 25 8 26 0 26 2 0 08 0 6 0 5 0 4 0 15 0 20 24 1 40 26 2 26 0 25 8 1 70 0 15 0 10 0 05 0 27 0 22 0 17 0 22 0 17 0 12 0 5 8 0 0 08 1 0 24 1 25 θ θ NOTE 1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH 2 DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET P LQFP176 24x24 0 50 1 9g MASS Typ FP 176C FP 176CV PLQP0176KD A REN...

Page 742: ...6 1 20 12 00 0 08 v w y1 0 2 0 20 0 15 Previous Code JEITA Package Code RENESAS Code TBP 208A TBP 208AV 0 26g MASS Typ 0 80 0 80 ZE ZD SE SD E D T TFBGA208 12x12 0 65 TTBG0208JA A 1 1 A A B S S y S w A S w B v S y1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 B C D E F G H J K L M N P R T U A A e e B A S φ b φ M 4 E Z D Z D E Figure D 2 Package Dimensions TBP 208A TTBG0208JA A ...

Page 743: ...B 145 585 595 602 BCR1 174 586 593 603 BCR2 177 586 593 603 BDMRB 145 585 594 602 BDRB 144 585 594 602 BETR 150 585 595 602 Big endian 20 BRCR 147 585 594 602 BRDR 152 585 595 602 BRSR 151 585 595 602 Burst Mode 282 Bus Modes 282 CCR 101 585 596 602 CCR2 102 585 596 602 Changing the Division Ratio 312 Changing the Multiplication Rate 312 Channel Priority 269 CHCR_0 256 587 597 604 CHCR_1 256 588 5...

Page 744: ...131 587 597 604 IRR2 132 587 597 604 little endian 20 MAC 16 MCR 186 586 593 603 MMUCR 58 585 596 602 Mode 0 307 Mode 1 307 Mode 2 307 Mode 7 307 Multiple Virtual Memory Mode 55 On Chip Peripheral Module Request 268 PACR 489 589 600 605 PADR 508 589 601 606 PBCR 490 589 600 605 PBDR 510 589 601 606 PC 16 PCCR 492 589 605 PCDR 512 589 600 601 606 PCMCIA 170 PCR 190 586 593 603 PDCR 493 589 600 605 ...

Page 745: ... 446 SCSCMR 424 587 591 604 SCSCR 372 587 591 604 SCSCR2 449 589 591 606 SCSMR 369 587 591 604 SCSMR2 447 589 591 606 SCSSR 376 425 587 591 604 SCSSR2 452 589 591 606 SCTDR 368 587 591 604 SCTSR 368 SCTSR2 446 SDBPR 555 SDBSR 556 SDIR 555 589 601 606 SDMR 193 586 594 Self Refreshing 230 Single Address Mode 279 Single Virtual Memory Mode 55 Space Allocation 166 SPC 17 SR 17 SSR 17 STBCR 569 585 594...

Page 746: ...Index Rev 5 00 May 29 2006 page 698 of 698 REJ09B0146 0500 ...

Page 747: ...te 1st Edition September 2001 Rev 5 00 May 29 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 748: ...8 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65...

Page 749: ...SH7706 Group Hardware Manual ...

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