Motorola MPC860 PowerQUICC User Manual Download Page 1091

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MOTOROLA

Index

Index--5

INDEX

data cache operation, 8-25
Ethernet mode, 28-3
external bus interface, 14-1
HDLC bus controller, 24-19
I

IDMA emulation, 20-6
instruction cache operation, 8-22
memory controller, 16-1
MMU, 9-1
MPC860-specific features, 4-4
parallel I/O ports, 34-2
parallel interface port, 33-1
PowerPC architecture-defined, 4-2
SCC HDLC mode, 24-2
SCC UART mode, 23-2
serial communications controllers (SCCs), 22-2
serial interface, 21-3
serial management controllers (SMCs), 30-2
serial peripheral interface, 31-2
SIU, 11-1
SMC in transparent mode, 30-21
SMC in UART mode, 30-10
Transparent mode, 29-1

FIR library functions, DSP, 36-7
Freeze operation, 11-33
FRZ (freeze) signal, 3-6, 13-8
Full completion queue timing, 10-4

General-purpose chip-select machine (GPCM), 16-18
General-purpose signals, 16-40
GPL_Xn (general-purpose line) signal, 3-7, 13-10
GSMR (AppleTalk mode), 25-3
GSMR (general SCC mode register), 22-3
GSMR (general SCC mode register) (asynchronous

HDLC), 26-6

GSMR/DSR configuration for asynchronous HDLC

mode, 26-6

GSMR/PSMR

programming for HDLC bus protocol, 24-23

Hard reset configuration word, 12-9
HDLC bus controller, 24-16
HI-Z instruction, 38-7
HRESET

external, 12-2
hard reset configuration word, 12-9
internal, 12-2
reset configuration, 12-6, 12-6
reset sequence, 12-4
settings at power-on, 15-7

HRESET (hard reset) signal, 3-8, 13-11

I2ADD (I

C address) register, 32-7

I2BRG (I

C baud rate generator) register, 32-7

C controller

buffer descriptors, 32-11
clocking, 32-2
commands, 32-11
master read (slave write), 32-4
master write (slave read), 32-3
overview, xxviii, 32-1
parameter RAM, 32-9
registers, 32-6
signals functions, 32-2
slave read (master write), 32-3
slave write (master read), 32-4
transfers, 32-3

I2CER (I

C event register), 32-8

I2CMR (I

C mask register), 32-8

I2COM (I

C command) register, 32-8

I2MOD (I

C mode) register, 32-6

IC_ADR (instruction cache address) register, 8-8
IC_CST (instruction cache control and status)

IC_CST commands, 8-9
IC_DAT (instruction cache data port) register, 8-8
IDMA

serial performance considerations, B-4
TEA, 20-22

IDMA emulation, 20-5
IDMA host commands, 20-12
IDMA parameter RAM, 20-6
IDMA transfer, 20-21
IDMA transfers, 20-15
IDMR1 (IDMA1 mask register, single-buffer

mode), 20-20

IDMRs (IDMA mask registers), 20-9
IDSR1 (IDMA1 status register, single-buffer

mode), 20-19

IDSRs (IDMA status registers), 20-8
IEEE 1149.1 test access port

boundary scan register, 38-3
BSDL description, 38-8
overview, 38-1
recommended configuration, 38-8
TAP controller, 38-2
usage considerations, 38-7

IMMR (internal memory map register), 11-4
Instruction fetch show cycle, 37-3
Instruction support control (ICTRL) register, 37-39
Instruction timing, 10-1

list of instructions, 10-6

Instructions

branch and flow control

branch instruction address calculation, 6-15

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Summary of Contents for MPC860 PowerQUICC

Page 1: ...IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controller Serial Peripheral Interface I C Controller Parallel Interface Port Parallel I O Port CPM Interrupt Controller Digital Signal Processing System Development and Debugging IEEE 1149 1 Tes...

Page 2: ...IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controller Serial Peripheral Interface I C Controller Parallel Interface Port Parallel I O Port CPM Interrupt Controller Digital Signal Processing System Development and Debugging IEEE 1149 1 Tes...

Page 3: ...MPC860UM AD 07 98 REV 1 MPC860 PowerQUICC ª UserÕs Manual ...

Page 4: ...ned intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application...

Page 5: ...rminology Conventions lxxiii Intended Audience lxxv Contents lxxv Conventions lxxv Acronyms and Abbreviations lxxvi Chapter 1 MPC860 Overview 1 1 Features 1 1 1 2 Architecture Overview 1 5 1 3 Embedded PowerPC Core 1 6 1 4 System Interface Unit SIU 1 7 1 5 PCMCIA Controller 1 7 1 6 Power Management 1 7 1 7 Communications Processor Module CPM 1 8 1 8 Software Compatibility Issues 1 9 Chapter 2 Memo...

Page 6: ...tructions 4 12 4 5 3 3 Store Accesses 4 12 4 5 3 4 Nonspeculative Load Instructions 4 12 4 5 3 5 Unaligned Accesses 4 13 4 5 3 6 Atomic Update Primitives 4 13 4 6 The MPC860 and the PowerPC Architecture 4 14 Chapter 5 PowerPC Core Register Set 5 1 MPC860 Register Implementation 5 1 5 1 1 PowerPC RegistersÑUser Registers 5 2 5 1 1 1 PowerPC User Level Register Bit Assignments 5 2 5 1 1 1 1 Conditio...

Page 7: ...Exceptions 6 7 6 2 3 Instruction Set Overview 6 7 6 2 4 PowerPC UISA Instructions 6 8 6 2 4 1 Integer Instructions 6 8 6 2 4 1 1 Integer Arithmetic Instructions 6 8 6 2 4 1 2 Integer Compare Instructions 6 9 6 2 4 1 3 Integer Logical Instructions 6 10 6 2 4 1 4 Integer Rotate and Shift Instructions 6 10 6 2 4 2 Load and Store Instructions 6 11 6 2 4 2 1 Integer Load and Store Address Generation 6 ...

Page 8: ...6 2 6 3 2 Translation Lookaside Buffer Management Instructions 6 23 6 2 7 Recommended Simplified Mnemonics 6 24 Chapter 7 Exceptions 7 1 Exceptions 7 2 7 1 1 Exception Ordering 7 3 7 1 2 PowerPC Defined Exceptions 7 4 7 1 2 1 System Reset Interrupt 0x00100 7 5 7 1 2 2 Machine Check Interrupt 0x00200 7 5 7 1 2 3 DSI Exception 0x00300 7 6 7 1 2 4 ISI Exception 0x00400 7 6 7 1 2 5 External Interrupt ...

Page 9: ... Invalidate All Command 8 11 8 3 2 Data Cache Control Registers 8 11 8 3 2 1 Reading Data Cache Tags and Copyback Buffer 8 14 8 3 2 2 DC_CST Commands 8 15 8 3 2 2 1 Data Cache Enable Disable Commands 8 16 8 3 2 2 2 Data Cache Load Lock Cache Block Command 8 16 8 3 2 2 3 Data Cache Unlock Cache Block Command 8 17 8 3 2 2 4 Data Cache Unlock All Command 8 17 8 3 2 2 5 Data Cache Invalidate All Comma...

Page 10: ...truction and Data Cache Operation with a Software Monitor Debugger 8 30 Chapter 9 Memory Management Unit MMU 9 1 Features 9 1 9 2 PowerPC Architecture Compliance 9 2 9 3 Address Translation 9 3 9 3 1 Translation Disabled 9 3 9 3 2 Translation Enabled 9 3 9 3 3 TLB Operation 9 5 9 4 Using Access Protection Groups 9 6 9 5 Protection Resolution Modes 9 7 9 6 Memory Attributes 9 8 9 7 Translation Tabl...

Page 11: ...TLB Entries 9 33 9 10 3 Loading Locked TLB Entries 9 34 9 10 4 TLB Invalidation 9 34 Chapter 10 Instruction Execution Timing 10 1 Instruction Execution Timing Examples 10 1 10 1 1 Data Cache Load with a Data Dependency 10 1 10 1 2 Writeback Arbitration 10 2 10 1 3 Private Writeback Bus Load 10 3 10 1 4 Fastest External Load Data Cache Miss 10 3 10 1 5 A Full Completion Queue 10 4 10 1 6 Branch Ins...

Page 12: ...e Service Register SWSR 11 22 11 8 The PowerPC Decrementer 11 23 11 8 1 Decrementer Register DEC 11 23 11 9 The PowerPC Timebase 11 24 11 9 1 Timebase Register TBU and TBL 11 24 11 9 2 Timebase Reference Registers TBREFA and TBREFB 11 25 11 9 3 Timebase Status and Control Register TBSCR 11 26 11 10 The Real Time Clock 11 27 11 10 1 Real Time Clock Status and Control Register RTCSC 11 27 11 10 2 Re...

Page 13: ...rnal Signals 13 1 System Bus Signals 13 5 13 2 Active Pull Up Buffers 13 21 13 3 Internal Pull Up and Pull Down Resistors 13 22 13 4 Recommended Basic Pin Connections 13 22 13 4 1 Reset Configuration 13 23 13 4 1 1 Bus Control Signals and Interrupts 13 23 13 4 2 JTAG and Debug Ports 13 23 13 4 3 Unused Inputs 13 24 13 4 4 Unused Outputs 13 24 13 5 Signal States during Hardware Reset 13 24 Chapter ...

Page 14: ...Transfer Acknowledge TA 14 33 14 4 8 2 Burst Inhibit BI 14 33 14 4 8 3 Transfer Error Acknowledge TEA 14 33 14 4 8 4 Termination Signals Protocol 14 33 14 4 9 Memory Reservation 14 34 14 4 9 1 Cancel Reservation CR 14 35 14 4 9 2 Kill Reservation KR 14 36 14 4 10 Bus Exception Control Cycles 14 37 14 4 10 1 RETRY 14 38 Chapter 15 Clocks and Power Control 15 1 Features 15 1 15 2 The Clock Module 15...

Page 15: ...l High Mode 15 21 15 5 2 Normal Low Mode 15 21 15 5 3 Doze High Mode 15 21 15 5 4 Doze Low Mode 15 22 15 5 5 Sleep Mode 15 23 15 5 6 Deep Sleep Mode 15 23 15 5 7 Power Down Mode 15 24 15 5 7 1 Software Initiation of Power Down Mode with Automatic Wake up 15 24 15 5 7 2 Maintaining the Real Time Clock RTC During Shutdown or Power Failure 15 25 15 5 7 3 Register Lock Mechanism Protecting SIU Registe...

Page 16: ...ng 16 20 16 5 1 3 Relaxed Timing 16 22 16 5 1 4 Output Enable OE Timing 16 25 16 5 1 5 Programmable Wait State Configuration 16 25 16 5 1 6 Extended Hold Time on Read Accesses 16 25 16 5 2 Boot Chip Select Operation 16 27 16 5 3 External Asynchronous Master Support 16 28 16 5 4 Special Case Bursting with External Transfer Acknowledge 16 29 16 6 User Programmable Machines UPMs 16 30 16 6 1 Requests...

Page 17: ...6 8 4 3 Special Signal for External Address Multiplexer Control 16 53 16 8 5 External Master Examples 16 53 16 8 5 1 External Masters and the GPCM 16 53 16 8 5 2 External Masters and the UPM 16 54 16 9 Memory System Interface Examples 16 58 16 9 1 Page Mode DRAM Interface Example 16 59 16 9 2 Page Mode Extended Data Out Interface Example 16 70 Chapter 17 PCMCIA Interface 17 1 System Configuration ...

Page 18: ... 3 1 Timer Global Configuration Register TGCR 18 8 18 2 3 2 Timer Mode Registers TMR1ÐTMR4 18 9 18 2 3 3 Timer Reference Registers TRR1ÐTRR4 18 10 18 2 3 4 Timer Capture Registers TCR1ÐTCR4 18 10 18 2 3 5 Timer Counter Registers TCN1ÐTCN4 18 10 18 2 3 6 Timer Event Registers TER1ÐTER4 18 11 18 2 4 Timer Initialization Examples 18 12 Chapter 19 Communications Processor 19 1 Features 19 1 19 2 Commu...

Page 19: ... SDMA Registers 20 3 20 2 1 SDMA Configuration Register SDCR 20 3 20 2 2 SDMA Status Register SDSR 20 4 20 2 3 SDMA Mask Register SDMR 20 5 20 2 4 SDMA Address Register SDAR 20 5 20 3 IDMA Emulation 20 5 20 3 1 IDMA Features 20 6 20 3 2 IDMA Parameter RAM 20 6 20 3 3 IDMA Registers 20 7 20 3 3 1 DMA Channel Mode Registers DCMR 20 7 20 3 3 2 IDMA Status Registers IDSR1 and IDSR2 20 8 20 3 3 3 IDMA ...

Page 20: ... 21 7 21 2 2 Enabling Connections to the TSA 21 8 21 2 3 SI RAM 21 8 21 2 3 1 Disabling and Reenabling the TSA 21 9 21 2 3 2 One TDM Channel with Static Frames 21 9 21 2 3 3 Two TDM Channels with Static Frames 21 10 21 2 3 4 SI RAM Dynamic Changes 21 10 21 2 3 5 One TDM Channel with Dynamic Frames 21 13 21 2 3 6 Two TDM Channels with Dynamic Frames 21 13 21 2 3 7 Programming the SI RAM 21 14 21 2 ...

Page 21: ...AM 22 14 22 3 1 Function Code Registers RFCR and TFCR 22 16 22 3 2 Handling SCC Interrupts 22 16 22 3 3 Initializing the SCCs 22 17 22 3 4 Controlling SCC Timing with RTS CTS and CD 22 18 22 3 4 1 Synchronous Protocols 22 18 22 3 4 2 Asynchronous Protocols 22 21 22 3 5 Digital Phase Locked Loop DPLL Operation 22 22 22 3 5 1 Encoding Data with a DPLL 22 24 22 3 6 Clock Glitch Detection 22 25 22 3 7...

Page 22: ...23 19 23 20 SCC UART Status Register SCCS 23 21 23 21 SCC UART Programming Example 23 22 23 22 S Records Loader Application 23 23 Chapter 24 SCC HDLC Mode 24 1 SCC HDLC Features 24 2 24 2 SCC HDLC Channel Frame Transmission 24 2 24 3 SCC HDLC Channel Frame Reception 24 3 24 4 SCC HDLC Parameter RAM 24 3 24 5 Programming the SCC in HDLC Mode 24 5 24 6 SCC HDLC Commands 24 5 24 7 Handling Errors in ...

Page 23: ...Asynchronous HDLC Frame Reception Processing 26 2 26 4 Transmitter Transparency Encoding 26 3 26 5 Receiver Transparency Decoding 26 3 26 6 Exceptions to RFC 1549 26 4 26 7 Asynchronous HDLC Channel Implementation 26 5 26 8 Asynchronous HDLC Mode Parameter RAM 26 5 26 9 Configuring GSMR and DSR for Asynchronous HDLC 26 6 26 9 1 General SCC Mode Register GSMR 26 6 26 9 2 Data Synchronization Regist...

Page 24: ... BD RxBD 27 12 27 13 SCC BISYNC Transmit BD TxBD 27 13 27 14 BISYNC Event Register SCCE BISYNC Mask Register SCCM 27 15 27 15 SCC Status Registers SCCS 27 16 27 16 Programming the SCC BISYNC Controller 27 17 27 17 SCC BISYNC Programming Example 27 18 Chapter 28 SCC Ethernet Mode 28 1 Ethernet on the MPC860 28 2 28 2 Features 28 3 28 3 Learning Ethernet on the MPC860 28 4 28 4 Connecting the MPC860...

Page 25: ...Synchronization in NMSI Mode 29 3 29 4 1 1 In Line Synchronization Pattern 29 3 29 4 1 2 External Synchronization Signals 29 4 29 4 1 2 1 External Synchronization Example 29 4 29 4 1 3 Transparent Mode without Explicit Synchronization 29 5 29 4 1 4 End of Frame Detection 29 5 29 4 2 Synchronization and the TSA 29 6 29 4 2 1 In line Synchronization Pattern 29 6 29 4 2 2 Inherent Synchronization 29 ...

Page 26: ... 4 SMC UART Channel Reception Process 30 11 30 3 5 Data Handling Modes Character and Message Oriented 30 11 30 3 6 SMC UART Commands 30 12 30 3 7 Sending a Break 30 12 30 3 8 Sending a Preamble 30 13 30 3 9 Handling Errors in the SMC UART Controller 30 13 30 3 10 SMC UART Receive BD RxBD 30 14 30 3 11 SMC UART Transmit BD TxBD 30 16 30 3 12 SMC UART Event Register SMCE Mask Register SMCM 30 18 30 ...

Page 27: ...egister SMCE Mask Register SMCM 30 36 Chapter 31 Serial Peripheral Interface 31 1 Features 31 2 31 2 SPI Clocking and Signal Functions 31 2 31 3 Configuring the SPI Controller 31 3 31 3 1 The SPI as a Master Device 31 3 31 3 2 The SPI as a Slave Device 31 5 31 3 3 The SPI in Multimaster Operation 31 5 31 4 SPI Registers 31 7 31 4 1 SPI Mode Register SPMODE 31 7 31 4 1 1 SPI Transfers with Differen...

Page 28: ...Parameter RAM 32 9 32 6 I2 C Commands 32 11 32 7 I2 C Buffer Descriptor BD Tables 32 11 32 7 1 I2 C Buffer Descriptors BDs 32 12 32 7 1 1 I2 C Receive Buffer Descriptor RxBD 32 12 32 7 1 2 I2C Transmit Buffer Descriptor TxBD 32 13 Chapter 33 Parallel Interface Port 33 1 Features 33 1 33 2 Core Control vs CP Control 33 2 33 2 1 Core Control 33 2 33 2 2 CP Control 33 2 33 3 The PIP Parameter RAM 33 ...

Page 29: ... 2 Port A 34 2 34 2 1 Port A Registers 34 3 34 2 1 1 Port A Open Drain Register PAODR 34 3 34 2 1 2 Port A Data Register PADAT 34 4 34 2 1 3 Port A Data Direction Register PADIR 34 4 34 2 1 4 Port A Pin Assignment Register PAPAR 34 5 34 2 2 Port A Configuration Examples 34 6 34 2 3 Port A Functional Block Diagrams 34 6 34 3 Port B 34 8 34 3 1 The Port B Registers 34 9 34 3 1 1 Port B Open Drain Re...

Page 30: ... 5 2 CPM Interrupt Pending Register CIPR 35 8 35 5 3 CPM Interrupt Mask Register 35 9 35 5 4 CPM Interrupt In Service Register CISR 35 9 35 5 5 CPM Interrupt Vector Register CIVR 35 10 35 6 Interrupt Handler ExampleÑSingle Event Interrupt Source 35 10 35 7 Interrupt Handler ExampleÑMultiple Event Interrupt Source 35 11 Chapter 36 Digital Signal Processing 36 1 Features 36 1 36 2 DSP Functionality ...

Page 31: ...2 2 IIR Function Descriptor 36 20 36 12 3 IIR Applications 36 21 36 13 Modulation MOD ÐReal Sin Real Cos Complex X and Real Complex Y 36 21 36 13 1 Modulation Table Input and Output Buffers 36 21 36 13 2 MOD Function Descriptor 36 22 36 13 3 MOD Applications 36 22 36 14 DEMODÐReal Sin Real Cos Real X and Complex Y 36 23 36 14 1 Modulation Table Input and Output Buffers and AGC Constant 36 23 36 14...

Page 32: ...nternal Core Events 37 6 37 1 5 3 Detecting the Trace Window Start Address 37 6 37 1 5 4 Detecting the Assertion Negation of VSYNC 37 7 37 1 5 5 Detecting the Trace Window End Address 37 7 37 1 5 6 Efficient Trace Information Capture 37 7 37 2 Watchpoints and Breakpoints Support 37 8 37 2 1 Key Features 37 9 37 2 2 Internal Watchpoints and Breakpoints Logic 37 10 37 2 3 Functional Description 37 1...

Page 33: ... 2 3 3 Selection of Development Port Clock Mode 37 29 37 3 2 4 Development Port Serial CommunicationsÐTrap Enable Mode 37 30 37 3 2 4 1 Serial Data Into Development Port 37 30 37 3 2 4 2 Serial Data Out of Development Port 37 31 37 3 2 5 Development Port Serial CommunicationsÐDebug Mode 37 32 37 3 2 5 1 Serial Data Into Development Port 37 32 37 3 2 5 2 Serial Data Out of Development Port 37 33 37...

Page 34: ...SDL Description 38 8 Appendix A Byte Ordering A 1 Byte Ordering Overview A 1 A 2 MPC860 Byte Ordering Mechanisms A 1 A 3 BE Mode A 2 A 4 TLE Mode A 2 A 4 1 TLE Mode System Examples A 4 A 5 PPC LE Mode A 6 A 5 1 I O Addressing in PPC LE Mode A 8 A 6 Setting the Endian Mode Of Operation A 8 Appendix B Serial Communications Performance B 1 Serial Clocking Peak Rate Limitation B 1 B 2 Bus Utilization ...

Page 35: ...rvisor Registers C 2 C 3 MPC860 Specific SPRs C 2 Appendix D MPC860 Instruction Set Listings D 1 Instructions Sorted by Mnemonic D 1 D 2 Instructions Sorted by Opcode D 9 D 3 Instructions Grouped by Functional Categories D 17 D 4 Instructions Sorted by Form D 27 D 5 Instruction Set Legend D 38 ...

Page 36: ...xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...

Page 37: ... Status Register DC_CST 8 12 8 7 Data Cache Address Register DC_ADR 8 13 8 8 Data Cache Data Port Register DC_DAT 8 14 8 9 Instruction Cache Data Path 8 21 9 1 Read Instruction Fetch Flow Diagram 9 4 9 2 Flow of Load Store Access 9 5 9 3 Effective to Physical Address Translation for 4 Kbyte Pages Block Diagram 9 6 9 4 Two Level Translation Table MD_CTR TWAM 1 9 10 9 5 Two Level Translation Table M...

Page 38: ...System Configuration and Protection Logic 11 3 11 2 Internal Memory Map Register IMMR 11 5 11 3 SIU Module Configuration Register SIUMCR 11 6 11 4 System Protection Control Register SYPCR 11 9 11 5 Transfer Error Status Register TESR 11 10 11 6 Register Lock Mechanism 11 12 11 7 MPC860 Interrupt Structure 11 13 11 8 SIU Interrupt Processing 11 15 11 9 IRQ0 Logical Representation 11 15 11 10 SIU In...

Page 39: ...4 3 14 3 Basic Transfer Protocol 14 6 14 4 Basic Flow Diagram of a Single Beat Read Cycle 14 7 14 5 Single Beat Read CycleÐBasic TimingÐZero Wait States 14 8 14 6 Basic Timing Single Beat Read Cycle One Wait State 14 9 14 7 Basic Flow of a Single Beat Write Cycle 14 10 14 8 Basic Timing Single Beat Write Cycle Zero Wait States 14 11 14 9 Basic Timing Single Beat Write Cycle One Wait State 14 12 14...

Page 40: ...NH 1 or CSRC 1 and DFNL 0 15 13 15 10 BRGCLK Divider 15 14 15 11 SYNCCLK Divider 15 15 15 12 MPC860 Power Rails 15 17 15 13 MPC860 Low Power Mode Flowchart 15 20 15 14 Software initiated Power down Configuration 15 25 15 15 SCCR 15 27 15 16 PLL Low Power and Reset Control Register PLPRCR 15 30 16 1 Memory Controller Block Diagram 16 3 16 2 Memory Controller Machine Selection 16 4 16 3 Simple Syste...

Page 41: ...32 RAM Array Indexing 16 31 16 33 Memory Periodic Timer Request Block Diagram 16 32 16 34 UPM Clock Scheme One Division Factor 1 16 33 16 35 UPM Clock Scheme Two Division Factor 2 16 33 16 36 UPM Signals Timing Example One Division Factor 1 EBDF 00 16 34 16 37 UPM Signals Timing Example Two Division Factor 2 EBDF 01 16 35 16 38 RAM Array and Signal Generation 16 35 16 39 The RAM Word 16 36 16 40 C...

Page 42: ...ce Input Pins Register PIPR 17 8 17 4 PCMCIA Interface Status Changed Register PSCR 17 9 17 5 PCMCIA Interface Enable Register PER 17 10 17 6 PCMCIA Interface General Control Register B PGCRx 17 12 17 7 PCMCIA Base Register PBR 17 13 17 8 PCMCIA Option Register 0Ð7 POR0ÐPOR7 17 13 17 9 PCMCIA Single Beat Read Cycle PRS 0 PSST 1 PSL 3 PSHT 1 17 16 17 10 PCMCIA Single Beat Read Cycle PRS 0 PSST 2 PS...

Page 43: ...iptor Structure 20 10 20 9 Function Code RegistersÑSFCR and DFCR 20 11 20 10 SDACK Timing Diagram Single Address Peripheral Write Externally Generated TA 20 16 20 11 SDACK Timing Diagram Single Address Peripheral Write Internally Generated TA 20 17 20 12 SDACK Timing Diagram Single Address Peripheral Read Internally Generated TA 20 18 20 13 IDMA Channel Mode Register DCMR Single Buffer Mode 20 19 ...

Page 44: ...R_LÑGeneral SCC Mode Register Low Order 22 6 22 4 Data Synchronization Register DSR 22 10 22 5 Transmit on Demand Register TODR 22 10 22 6 SCC Buffer Descriptors BDs 22 12 22 7 SCC BD and Buffer Memory Structure 22 13 22 8 Function Code Registers RFCR and TFCR 22 16 22 9 Output Delay from RTS Asserted for Synchronous Protocols 22 19 22 10 Output Delay from CTS Asserted for Synchronous Protocols 22...

Page 45: ...sion Line Configuration 24 22 25 1 LocalTalk Frame Format 25 1 25 2 Connecting the MPC860 to LocalTalk 25 3 26 1 Asynchronous HDLC Frame Structure 26 2 26 2 Receive Flowchart 26 4 26 3 TXCTL_TBL RXCTL_TBL 26 6 26 4 Asynchronous HDLC Event Register SCCE Asynchronous HDLC Mask Register SCCM 26 9 26 5 SCC Status Register for Asynchronous HDLC Mode SCCS 26 10 26 6 Asynchronous HDLC Mode Register PSMR ...

Page 46: ...Frame Format 30 10 30 6 SMC UART Receive BD RxBD 30 14 30 7 SMC UART Receiving using RxBDs 30 16 30 8 SMC UART Transmit BD TxBD 30 17 30 9 SMC UART Event Register SMCE Mask Register SMCM 30 18 30 10 SMC UART Interrupts Example 30 19 30 11 Synchronization with SMSYNx 30 23 30 12 Synchronization with the TSA 30 24 30 13 SMC Transparent Receive BD RxBD 30 26 30 14 SMC Transparent Transmit BD TxBD 30 ...

Page 47: ...ol Character Table RCCM and RCCR 33 6 33 5 PIP Configuration Register PIPC 33 8 33 6 PIP Event Register PIPE 33 9 33 7 PIP Timing Parameters Register PTPR 33 10 33 8 Port B General Purpose I O 33 11 33 9 PIP Tx Buffer Descriptor TxBD 33 12 33 10 PIP Rx Buffer Descriptor RxBD 33 13 33 11 Interlocked Handshake Mode Timing 33 15 33 12 Pulsed Handshake Full Cycle 33 16 33 13 Pulsed Handshake BUSY Sign...

Page 48: ... Register CICR 35 7 35 4 CPM Interrupt Pending Mask In Service Registers CIPR CIMR CISR 35 8 35 5 CPM Interrupt Vector Register CIVR 35 10 36 1 DSP Functionality Implementation 36 2 36 2 DSP Function Descriptor FD Chain Structure 36 3 36 3 Function Descriptor FD Structure 36 3 36 4 Real Number Representation 36 4 36 6 Circular Buffer 36 5 36 5 Complex Number Representation 36 5 36 7 DSP Event Mask...

Page 49: ...onous Clocked Serial Communications 37 28 37 10 Synchronous Self Clocked Serial Communications 37 29 37 11 Enabling Clock Mode after Reset 37 30 37 12 Download Procedure Code Example 37 34 37 13 Fast and Slow Download Procedure Loops 37 35 37 14 Comparator AÐD Value Register CMPAÐCMPD 37 37 37 15 Comparator EÐF Value Registers CMPEÐCMPF 37 38 37 16 Comparator GÐH Value Registers CMPGÐCMPH 37 38 37...

Page 50: ...l MPC860 PowerQUICC UserÕs Manual MOTOROLA ILLUSTRATIONS Figure Number Title Page Number A 2 Byte Swapping A 4 A 3 PPC LE Mode Mechanisms A 7 ...

Page 51: ...Value Summary of the DAR BAR and DSISR Registers 5 6 5 8 MSR Field Descriptions 5 7 5 9 MPC860 Specific Supervisor Level SPRs 5 9 5 10 MPC860 Specific Debug Level SPRs 5 10 5 11 Addresses of SPRs Located Outside of the Core 5 11 6 1 Memory Operands 6 2 6 2 Integer Arithmetic Instructions 6 8 6 3 Integer Compare Instructions 6 9 6 4 Integer Logical Instructions 6 10 6 5 Integer Rotate Instructions ...

Page 52: ...m Call Exception 7 11 7 11 Register Settings after a Trace Exception 7 11 7 12 Register Settings after a Software Emulation Exception 7 12 7 13 Register Settings after an Instruction TLB Miss Exception 7 13 7 14 Register Settings after a Data TLB Miss Exception 7 13 7 15 Register Settings after an Instruction TLB Error Exception 7 14 7 16 Register Settings after a Data TLB Error Exception 7 14 7 1...

Page 53: ... 9 22 MPC860 Specific MMU Exceptions 9 32 10 1 Instruction Execution Timing 10 6 10 2 Load Store Instructions Timing 10 7 11 1 Multiplexing Control 11 4 11 2 IMMR Field Descriptions 11 5 11 3 SIUMCR Field Descriptions 11 6 11 4 SYPCR Field Descriptions 11 9 11 5 TESR Field Descriptions 11 10 11 6 Key Registers 11 11 11 7 Priority of SIU Interrupt Sources 11 14 11 8 IRQ0 Versus IRQx Operation 11 16...

Page 54: ...or Values Based on the MF Field 15 8 15 3 Functionality Summary of the Clocks 15 9 15 4 PITRTCLK Configuration at PORESET 15 16 15 5 TMBCLK Configuration 15 16 15 6 MPC860 Modules vs Power Rails 15 17 15 7 MPC860 Low Power Modes 15 19 15 8 SCCR Field Descriptions 15 27 15 9 PLPRCR Field Descriptions 15 30 15 10 PLPRCR CSR and DER CHSTPE Bit Combinations 15 31 16 1 Memory Controller Register Usage ...

Page 55: ... Descriptions 18 11 19 1 Peripheral Prioritization 19 3 19 2 CP Microcode Revision Number 19 4 19 3 RCCR Field Descriptions 19 5 19 4 CPCR Field Descriptions 19 6 19 5 CP Command Opcodes 19 7 19 6 CP Commands 19 8 19 7 General BD Structure 19 11 19 8 Parameter RAM Memory Map 19 11 19 9 RISC Timer Table Parameter RAM Memory Map 19 13 19 10 TM_CMD Field Descriptions 19 14 19 11 PWM Channel Pin Assig...

Page 56: ... 22 25 23 1 UART Specific SCC Parameter RAM Memory Map 23 4 23 2 Transmit Commands 23 6 23 3 Receive Commands 23 6 23 4 Control Character Table RCCM and RCCR Descriptions 23 8 23 5 TOSEQ Field Descriptions 23 10 23 6 DSR Fields Descriptions 23 11 23 7 Transmission Errors 23 12 23 8 Reception Errors 23 12 23 9 PSMR UART Field Descriptions 23 13 23 10 SCC UART RxBD Status and Control Field Descripti...

Page 57: ...ransmit Errors 27 9 27 9 Receive Errors 27 10 27 10 PSMR Field Descriptions 27 11 27 11 SCC BISYNC RxBD Status and Control Field Descriptions 27 12 27 12 SCC BISYNC TxBD Status and Control Field Descriptions 27 14 27 13 SCCE SCCM Field Descriptions 27 16 27 14 SCCS Field Descriptions 27 17 27 15 Control Characters 27 18 28 1 SCC Ethernet Parameter RAM Memory Map 28 12 28 2 Transmit Commands 28 15 ...

Page 58: ...ent TxBD Field Descriptions 30 28 30 17 SMCE SMCM Field Descriptions 30 29 30 18 SMC GCI Parameter RAM Memory Map 30 32 30 19 SMC GCI Commands 30 33 30 20 SMC Monitor Channel RxBD Field Descriptions 30 34 30 21 SMC Monitor Channel TxBD Field Descriptions 30 34 30 22 SMC C I Channel RxBD Field Descriptions 30 35 30 23 SMC C I Channel TxBD Field Descriptions 30 35 30 24 SMCE SMCM Field Descriptions ...

Page 59: ...1 Port A Pin Assignment 34 2 34 2 PAODR Bit Descriptions 34 4 34 3 PADAT Bit Descriptions 34 4 34 4 PADIR Bit Descriptions 34 5 34 5 PAPAR Bit Descriptions 34 5 34 6 Port B Pin Assignment 34 8 34 7 PBODR Bit Descriptions 34 10 34 8 PBDAT Bit Descriptions 34 10 34 9 PBDIR Bit Descriptions 34 11 34 10 PBPAR Bit Descriptions 34 12 34 11 Port C Pin Assignment 34 12 34 12 PCDAT Bit Descriptions 34 15 3...

Page 60: ...ameter Packet 36 26 36 25 LMS2 Coefficients and Input Buffers 36 27 36 26 LMS2 Parameter Packet 36 28 36 27 WADD Modulation Table and Sample Data Buffers 36 29 36 28 WADD Parameter Packet 36 29 36 29 WADD Applications 36 30 36 30 DSP Function Execution Times 36 33 37 1 Fetch Show Cycles Control 37 3 37 2 Status Pin Groupings 37 3 37 3 VF Pins Encoding Instruction Queue Flushes 37 4 37 4 VF Pins En...

Page 61: ...ser Level PowerPC SPRs C 1 C 3 Supervisor Level PowerPC Registers C 2 C 4 Supervisor Level PowerPC SPRs C 2 C 5 MPC860 Specific Supervisor Level SPRs C 3 C 6 MPC860 Specific Debug Level SPRs C 4 D 1 Complete Instruction List Sorted by Mnemonic D 1 D 2 Complete Instruction List Sorted by Opcode D 9 D 3 Integer Arithmetic Instructions D 17 D 4 Integer Compare Instructions D 18 D 5 Integer Logical In...

Page 62: ...26 Processor Control Instructions D 25 D 27 Cache Management Instructions D 26 D 28 Segment Register Manipulation Instructions D 26 D 29 Lookaside Buffer Management Instructions D 26 D 30 External Control Instructions D 26 D 31 I Form D 27 D 32 B Form D 27 D 33 SC Form D 27 D 34 D Form D 27 D 35 DS Form D 29 D 36 X Form D 29 D 37 XL Form D 33 D 38 XFX Form D 34 D 39 XFL Form D 34 D 40 XS Form D 34...

Page 63: ...in the disclaimers on the title page of this book As with any technical documentation it is the readersÕ responsibility to be sure they are using the most recent version of the documentation For more information contact your sales representative Before Using this Manual Before using this manual determine whether it is the latest revision and if there are errata or addenda To locate any published e...

Page 64: ...opics described in further detail in subsequent chapters in Part II Ñ Chapter 5 ÒPowerPC Core Register Set Ó describes the hardware registers accessible to the MPC860 core These include both architecturally deÞned and MPC860 speciÞc registers Ñ Chapter 6 ÒMPC860 Instruction Set Ó describes the PowerPC instructions implemented on the MPC860 including MPC860 speciÞc features Ñ Chapter 7 ÒExceptions ...

Page 65: ...y Controller Ó describes the memory controller which controlling a maximum of eight memory banks shared between a general purpose chip select machine GPCM and a pair of user programmable machines UPMs Ñ Chapter 17 ÒPCMCIA Interface Ó describes the PCMCIA host adapter module which provides all control logic for a PCMCIA socket interface and requires only additional external analog power switching l...

Page 66: ...tocol Ñ Chapter 29 ÒSCCTransparent Mode Ó describes the MPC860 implementation of transparent mode also called totally transparent mode which provides a clear channel on which the SCC can send or receive serial data without bit level manipulation Ñ Chapter 30 ÒSerial Management Controllers Ó describes two serial management controllers full duplex ports that can be conÞgured independently to support...

Page 67: ...es for debugging and system testing Ñ Chapter 37 ÒSystem Development and Debugging Ó describes support provided for program ßow tracking internal watchpoint and breakpoint generation and emulation systems control Ñ Chapter 38 ÒIEEE 1149 1 Test Access Port Ó describes the dedicated user accessible test access port TAP which is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boun...

Page 68: ...re that are common to PowerPC processors There are two versions one that describes the functionality of the combined 32 and 64 bit architecture models and one that describes only the 32 bit model Ñ PowerPC Microprocessor Family The Programming Environments Rev 1 Motorola order MPCFPE AD Ñ PowerPC Microprocessor Family The Programming Environments for 32 Bit Microprocessors Rev 1 Motorola order MPC...

Page 69: ...talics indicate variable command parameters for example bcctrx Book titles in text are set in italics 0x0 PreÞx to denote hexadecimal number 0b0 PreÞx to denote binary number rA rB Instruction syntax used to identify a source GPR rD Instruction syntax used to identify a destination GPR REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text SpeciÞc bits ...

Page 70: ... memory CEPT Conference des administrations Europeanes des Postes et Telecommunications European Conference of Postal and Telecommunications Administrations CPM Communication processor module CR Condition register CRC Cyclic redundancy check CTR Count register DABR Data address breakpoint register DAR Data address register DEC Decrementer register DMA Direct memory access DPLL Digital phase locked...

Page 71: ...tion lookaside buffer IU Integer unit JTAG Joint Test Action Group LIFO Last in Þrst out LR Link register LRU Least recently used LSB Least signiÞcant byte lsb Least signiÞcant bit LSU Load store unit MAC Multiply accumulate MESI ModiÞed exclusive shared invalidÑcache coherency protocol MMU Memory management unit MSB Most signiÞcant byte msb Most signiÞcant bit MSR Machine state register NaN Not a...

Page 72: ...erial DMA SI Serial interface SIMM Signed immediate value SIU System interface unit SMC Serial management controller SNA Systems network architecture SPI Serial peripheral interface SPR Special purpose register SPRGn Registers available for general purposes SRAM Static random access memory SRR0 Machine status save restore register 0 SRR1 Machine status save restore register 1 TAP Test access port ...

Page 73: ...primarily for indicating conditions such as carries and overßows for integer operations Table ii Terminology Conventions The Architecture SpeciÞcation This Manual Data storage interrupt DSI DSI exception Extended mnemonics SimpliÞed mnemonics Instruction storage interrupt ISI ISI exception Interrupt Exception Privileged mode or privileged state Supervisor level privilege Problem mode or problem st...

Page 74: ...notation conventions used in this manual Table iii Instruction Field Conventions The Architecture SpeciÞcation Equivalent to BA BB BT crbA crbB crbD respectively BF BFA crfD crfS respectively D d DS ds FLM FM FXM CRM RA RB RT RS rA rB rD rS respectively SI SIMM U IMM UI UIMM 0 0 shaded ...

Page 75: ...formation Chapter 2 ÒMemory Map Ó presents a table showing where MPC860 registers are mapped in memory It includes cross references that indicate where the registers are described in detail Chapter 3 ÒHardware Interface Overview Ó provides an MPC860 pinout diagram and signal listing Conventions Part I uses the following notational conventions mnemonics Instruction mnemonics are shown in lowercase ...

Page 76: ...breviated Terms Term Meaning BD Buffer descriptor BPU Branch processing unit CPM Communications processor module DMA Direct memory access DPLL Digital phase locked loop DRAM Dynamic random access memory DSP Digital signal processing DTLB Data translation lookaside buffer EA Effective address GPCM General purpose chip select machine GPR General purpose register HDLC High level data link control I2C...

Page 77: ...troller SDLC Synchronous Data Link Control SDMA Serial DMA SI Serial interface SIU System interface unit SMC Serial management controller SPI Serial peripheral interface SPR Special purpose register SRAM Static random access memory TB Time base register TDM Time division multiplexed TLB Translation lookaside buffer TSA Time slot assigner Tx Transmit UART Universal asynchronous receiver transmitter...

Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...

Page 79: ...onality has been added to the CPM The memory controller has been enhanced enabling the MPC860 to support any type of memory including high performance memories and new types of DRAMs A PCMCIA socket controller supports up to two sockets A real time clock has also been integrated The purpose of this manual is to describe the operation of all the MPC860 functionality with concentration on the I O fu...

Page 80: ... EPROMs ßash EPROMs and other memory devices Ñ DRAM controller programmable to support most size and speed memory interfaces Ñ Four CAS lines four WE lines one OE line Ñ Boot chip select available at reset options for 8 16 or 32 bit memory Ñ Variable block sizes 32 KbyteÐ256 Mbyte Ñ Selectable write protection Ñ On chip bus arbitration logic General purpose timers Ñ Four 16 bit timers or two 32 bi...

Page 81: ...tiply accumulate controller MAC Ñ One operation per clock two clock latency one clock blockage Ñ MAC operates concurrently with other instructions Ñ FIR loop four clocks per four multiplies Four baud rate generators Ñ Independent can be connected to any SCC or SMC Ñ Allow changes during operation Ñ Autobaud support option Four SCCs serial communication controllers Ñ Ethernet IEEE 802 3 optional on...

Page 82: ...ansmit and receive routing frame synchronization clocking Ñ Allows dynamic changes Ñ Can be internally connected to six serial channels four SCCs and two SMCs Parallel interface port PIP Ñ Centronics interface support Ñ Supports fast connection between compatible ports on MPC860 or MC68360 PCMCIA interface Ñ Master socket interface release 2 1 compliant Ñ Supports two independent PCMCIA sockets Ñ ...

Page 83: ...PC860 is comprised of three modules that each use the 32 bit internal bus the PowerPC core the system integration unit SIU and the communication processor module CPM The MPC860 block diagram is shown in Figure 1 1 System Interface Unit SIU PowerPC Processor Core Parallel I O Memory Controller 4 Timers Interrupt Controllers 5 K Dual Port RAM 1 16 Virtual Serial and 2 Independent DMA Channels System...

Page 84: ...ion cache is 4 Kbytes two way set associative with physical addressing It allows single cycle access on hits with no added latency for misses It has four words per block supporting a four beat burst line Þll using an LRU least recently used replacement algorithm The cache can be locked on a per cache block basis for application critical routines The data cache is 4 Kbytes two way set associative w...

Page 85: ...deÞned as 64 Kbytes and 128 Kbytes for 8 bit memory or 128 Mbytes and 256 Mbytes for 32 bit memory The DRAM controller supports page mode access for successive transfers within bursts The MPC860 supports a glueless interface to one bank of DRAM while external buffers are required for additional memory banks The refresh unit provides CAS before RAS a programmable refresh timer refresh active during...

Page 86: ...se timers The CP provides the communication features of the MPC860 Included are a RISC processor two serial communication controllers SCC four serial management controllers SMC one serial peripheral interface SPI one I2C interface 5 Kbytes of dual port RAM an interrupt controller a time slot assigner three parallel ports a parallel interface port four independent baud rate generators and sixteen s...

Page 87: ...U must be rewritten Many developers of 68K compilers now provide compilers that also support the PowerPC architecture The addition of the MAC function to the MPC860 CPM block to support the needs of higher performance communication software is the only major difference between the CPM on the MC68360 and that on the MPC860 Therefore the registers used to initialize the QUICC CPM are similar to the ...

Page 88: ...1 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...

Page 89: ...nterrupt pending register 32 bits 11 5 4 1 11 16 014 SIMASKÑSIU interrupt mask register 32 bits 11 5 4 2 11 17 018 SIELÑSIU interrupt edge level register 32 bits 11 5 4 3 11 18 01C SIVECÑSIU interrupt vector register 32 bits 11 5 4 4 11 19 020 TESRÑTransfer error status register 32 bits 11 4 4 11 10 024Ð02F Reserved 12 bytes Ñ 030 SDCRÑSDMA conÞguration register 32 bits 20 2 1 20 3 034Ð07F Reserve...

Page 90: ...e enable register 32 bits 17 4 3 17 10 0FCÐ0FF Reserved 4 bytes Ñ Memory Controller 100 BR0ÑBase register bank 0 32 bits 16 4 1 16 8 104 OR0ÑOption register bank 0 32 bits 16 4 2 16 10 108 BR1ÑBase register bank 1 32 bits 16 4 1 16 8 10C OR1ÑOption register bank 1 32 bits 16 4 2 16 10 110 BR2ÑBase register bank 2 32 bits 16 4 1 16 8 114 OR2ÑOption register bank 2 32 bits 16 4 2 16 10 118 BR3ÑBase ...

Page 91: ...RTSECÑReal time alarm seconds 32 bits 11 10 4 11 29 22C RTCALÑReal time alarm register 32 bits 11 10 3 11 29 230Ð23F Reserved 16 bytes Ñ 240 PISCRÑPeriodic interrupt status and control register 16 bits 11 11 1 11 31 242Ð233 Reserved 2 bytes Ñ 244 PITCÑPeriodic interrupt count register 32 bits 11 11 2 11 32 248 PITRÑPeriodic interrupt timer register 32 bits 11 11 3 11 33 24CÐ27F Reserved 52 bytes Ñ...

Page 92: ...88 RSRKÑReset status register key 32 bits 11 4 5 11 11 38CÐ85F Reserved 1236 bytes Ñ I2C Controller 860 I2MODÑI2C mode register 8 bits 32 4 1 32 6 861Ð863 Reserved 3 bytes Ñ 864 I2ADDÑI2C address register 8 bits 32 4 2 32 7 865Ð867 Reserved 3 bytes Ñ 868 I2BRGÑI2 C BRG register 8 bits 32 4 3 32 7 86C I2COMÑI2C command register 8 bits 32 4 5 32 8 86DÐ86F Reserved 3 bytes Ñ 870 I2CERÑI2C event regis...

Page 93: ...16 bits 34 2 1 2 34 4 958Ð95F Reserved 8 bytes Ñ 960 PCDIRÑPort C data direction register 16 bits 34 4 1 2 34 15 962 PCPARÑPort C pin assignment register 16 bits 34 4 1 3 34 15 964 PCSOÑPort C special options register 16 bits 34 4 1 4 34 16 966 PCDATÑPort C data register 16 bits 34 4 1 1 34 15 968 PCINTÑPort C interrupt control register 16 bits 34 4 1 5 34 17 96AÐ96F Reserved 6 bytes Ñ 970 PDDIRÑP...

Page 94: ...ommunications Processor CP 9C0 CPCRÑCP command register 16 bits 19 5 2 19 6 9C2Ð9C3 Reserved 2 bytes Ñ 9C4 RCCRÑRISC controller conÞguration register 16 bits 19 5 1 19 4 9C6Ð9C8 Reserved 3 bytes Ñ 9CC RCTR1ÑRISC controller trap register 1 16 bits Used only by optional RAM microcode 9CE RCTR2ÑRISC controller trap register 2 16 bits Used only by optional RAM microcode 9D0 RCTR3ÑRISC controller trap ...

Page 95: ...YNC 29 13 29 13 Transparent A18ÐA1F Reserved 8 bytes Ñ Serial Communication Controller 2 SCC2 A20 GSMR_L2ÑSCC2 general mode register 32 bits 22 1 1 22 3 A24 GSMR_H2ÑSCC2 general mode register 32 bits 22 1 1 22 3 A28 PSMR2ÑSCC2 protocol speciÞc mode register 16 bits 22 1 2 22 10 23 16 23 13 UART 26 13 3 26 11 Asynchronous HDLC 27 11 27 10 BISYNC 28 18 28 19 Ethernet 29 9 29 8 Transparent A2A Reserv...

Page 96: ... BISYNC 29 13 29 13 Transparent A52ÐA53 Reserved 2 bytes A54 SCCM3ÑSCC3 mask register 16 bits A56 Reserved 1 byte Ñ A57 SCCS3ÑSCC3 status register 8 bits 23 20 23 21 UART 24 12 24 14 HDLC 27 15 27 16 BISYNC 29 13 29 13 Transparent A58ÐA5F Reserved 8 bytes Ñ SCC4 A60 GSMR_L4ÑSCC4 general mode register 32 bits 22 1 1 22 3 A64 GSMR_H4ÑSCC4 general mode register 32 bits 22 1 1 22 3 A68 PSMR4ÑSCC4 prot...

Page 97: ...ent register 8 bits 30 3 12 30 18 UART 30 4 11 30 29 Transparent 30 5 9 30 36 GCI A97ÐA99 Reserved 3 bytes Ñ A9A SMCM2ÑSMC2 mask register 8 bits 30 3 12 30 18 UART 30 4 11 30 29 Transparent 30 5 9 30 36 GCI A9BÐA9F Reserved 5 bytes Ñ Serial Peripheral Interface SPI AA0 SPMODEÑSPI mode register 16 bits 31 4 1 31 7 AA2ÐAA5 Reserved 16 bits4 bytes Ñ AA6 SPIEÑSPI event register 8 bits 31 4 2 31 10 AA7...

Page 98: ... register 8 bits 21 2 4 5 21 25 AE7 SICMRÑSI command register 8 bits 21 2 4 4 21 24 AE8ÐAEB Reserved 4 bytes Ñ AEC SICRÑSI clock route register 32 bits 21 2 4 3 21 23 AF0 SIRPÑSerial interface RAM pointer register 32 bits 21 2 4 6 21 26 AF4ÐBFF Reserved 268 bytes Ñ Specialized RAM C00ÐDFF SIRAMÑSI routing RAM 512 bytes 21 2 3 7 21 14 E00Ð1FFF Reserved 4 608 bytes Ñ Dual Ported RAM 2000Ð2FFF DPRAMÑ...

Page 99: ...act is provided in Part IV ÒHardware Interface Ó The MPC860 bus interface features are listed as follows 32 bit address bus with transfer size indication 32 bit data bus TTL compatible interface Compatible with PowerPC architecture Easy to interface to slave devices Bus is synchronous all signals are referenced to rising edge of bus clock Contains supports for data parity The MPC860 bus interface ...

Page 100: ... L1TSYNCA PD15 L1RSYNCA PD14 L1TSYNCB PD13 L1RSYNCB PD12 RxD3 PD11 TxD3 PD10 RxD4 PD9 TxD4 PD8 RTS3 PD7 RTS4 PD6 REJECT2 PD5 REJECT3 PD4 REJECT4 PD3 TMS DSDI TDI DSCK TCK TRST DSDO TDO AS MPC860 32 1 1 1 1 1 1 1 1 1 1 1 1 32 4 1 1 1 1 2 1 6 1 1 1 1 1 1 4 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 5 1 1 2 1 1 1 1 1 2 1 1 1 1 1 129 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 101: ...t when an internal master starts a transaction on the external bus The bus is input when an external master starts a transaction on the bus TSIZ0 REG Bidirectional Three state Transfer Size 0ÑWhen accessing a slave in the external bus this signal is used together with TSIZ1 by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle TSIZ0 is an inpu...

Page 102: ... Every slave device should negate TA after a transaction ends and immediately three state it to avoid bus contention if a new transfer is initiated addressing other slave devices TA requires the use of an external pull up resistor TEA Open drain Transfer Error AcknowledgeÑThis signal indicates that a bus error occurred in the current transaction The MPC860 asserts TEA when the bus monitor does not...

Page 103: ...ity function can be deÞned independently for each one of the addressed memory banks if controlled by the memory controller and for the rest of the slaves sitting on the external bus Parity generation and checking is not supported for external masters Interrupt Request 3ÑOne of eight external inputs that can request by means of the internal interrupt controller a service routine from the core Note ...

Page 104: ...erted low by a master to show that it owns the bus The MPC860 asserts BB after the arbiter grants it bus ownership and BB is negated FRZ IRQ6 Bidirectional FreezeÑOutput asserted to indicate that the core is in debug mode Interrupt Request 6ÑOne of eight external inputs that can request by means of the internal interrupt controller a service routine from the core Note that the interrupt request si...

Page 105: ...d only D 16Ð23 contains valid data PCMCIA Output EnableÑOutput asserted when the MPC860 initiates a read access to a memory region under the control of the PCMCIA interface WE3 BS_B3 PCWE Output Write Enable 3ÑOutput asserted when the MPC860 initiates a write access to an external slave controlled by the GPCM WE3 is asserted if D 24Ð31 contains valid data to be stored by the slave device Byte Sele...

Page 106: ...reset state RSTCONF Input Reset ConÞgurationÑThe MPC860 samples this input while HRESET is asserted If RSTCONF is asserted the conÞguration mode is sampled in the form of the hard reset conÞguration word driven on the data bus When RSTCONF is negated the MPC860 uses the default conÞguration mode Note that the initial base address of internal registers is determined in this sequence HRESET Open dra...

Page 107: ...eport the detection of an instruction watchpoint in the program ßow executed by the core Visible History Buffer Flushes StatusÑThe MPC860 outputs VFLS 0Ð1 when program instruction ßow tracking is required They report the number of instructions ßushed from the history buffer in the core IP_B2 IOIS16_B AT2 Bidirectional Three state Input Port B 2ÑThe MPC860 senses this input its value and changes ar...

Page 108: ... data transfer or a program trace indication for an instruction fetch AT3 is not used for transactions initiated by external masters OP 0Ð1 Output Output Port 0Ð1ÑThe MPC860 generates these outputs as a result of a write to the PGCRA register in the PCMCIA interface OP2 MODCK1 STS Bidirectional Output Port 2ÑThis output is generated by the MPC860 as a result of a write to the PGCRB register in the...

Page 109: ...ain General Purpose I O Port A Bit 11ÑBit 11 of the general purpose I O port A L1TXDBÑTransmit data output for the serial interface TDM port B L1TXDB has an open drain capability PA 10 L1RXDB Bidirectional General Purpose I O Port A Bit 10ÑBit 10 of the general purpose I O port A L1RXDBÑReceive data input for the serial interface TDM port B PA 9 L1TXDA Bidirectional Optional Open drain General Pur...

Page 110: ...O Port B Bit 31ÑBit 31 of the general purpose I O port B SPISELÑSPI slave select input REJECT1ÑSCC1 CAM interface reject pin PB 30 SPICLK RSTRT2 Bidirectional Optional Open drain General Purpose I O Port B Bit 30ÑBit 30 of the general purpose I O port B SPICLKÑSPI output clock when it is conÞgured as a master or SPI input clock when it is conÞgured as a slave RSTRT2ÑSCC2 serial CAM interface outpu...

Page 111: ...I O port B RTS2ÑRequest to send modem line for SCC2 L1ST2ÑOne of four output strobes that can be generated by the serial interface PB 17 L1RQB L1ST3 Bidirectional Optional Open drain General Purpose I O Port B Bit 17ÑBit 17 of the general purpose I O port B L1RQBÑD channel request signal for the serial interface TDM port B L1ST3ÑOne of four output strobes that can be generated by the serial interf...

Page 112: ...ort B PC 5 CTS4 L1TSYNCA SDACK1 Bidirectional General Purpose I O Port C Bit 5ÑBit 5 of the general purpose I O port C CTS4ÑClear to send modem line for SCC4 L1TSYNCAÑTransmit sync input for the serial interface TDM port A SDACK1ÑSDMA acknowledge 1output that is used as a peripheral interface signal for IDMA emulation or as a CAM interface signal for Ethernet PC 4 CD4 L1RSYNCA Bidirectional Genera...

Page 113: ... the frame address did not match PD 3 REJECT4 Bidirectional General purpose I O Port D Bit 3ÑBit 3 of the general purpose I O port D REJECT4ÑThis input to SCC4 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match TCK DSCK Input Provides clock to scan chain logic or for the development port logic TMS Input Controls the scan chain test mode operations...

Page 114: ...3 16 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...

Page 115: ... II Chapter 5 ÒPowerPC Core Register Set Ó describes the hardware registers accessible to the MPC860 core These include both architecturally deÞned and MPC860 speciÞc registers Chapter 6 ÒMPC860 Instruction Set Ó describes the PowerPC instructions implemented on the MPC860 including MPC860 speciÞc features Chapter 7 ÒExceptions Ó describes the PowerPC exception model as it is implemented on the MP...

Page 116: ...bined 32 and 64 bit architecture models and one that describes only the 32 bit model Ñ PowerPC Microprocessor Family The Programming Environments Rev 1 Motorola order MPCFPE AD Ñ PowerPC Microprocessor Family The Programming Environments for 32 Bit Microprocessors Rev 1 Motorola order MPCFPE32B AD PowerPC Microprocessor Family The Bus Interface for 32 Bit Microprocessors Motorola order MPCBUSIF AD...

Page 117: ...urce GPR rD Instruction syntax used to identify a destination GPR REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text SpeciÞc bits Þelds or numerical ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit Þeld indicates a donÕt ...

Page 118: ... register FPSCR Floating point status and control register GPR General purpose register IEEE Institute of Electrical and Electronics Engineers ITLB Instruction translation lookaside buffer IU Integer unit LIFO Last in Þrst out LR Link register LRU Least recently used LSB Least signiÞcant byte lsb Least signiÞcant bit LSU Load store unit MMU Memory management unit MSB Most signiÞcant byte msb Most ...

Page 119: ...ve restore register 1 TB Time base register TLB Translation lookaside buffer Tx Transmit UIMM Unsigned immediate value UISA User instruction set architecture VA Virtual address VEA Virtual environment architecture XER Register used primarily for indicating conditions such as carries and overßows for integer operations Table vi Terminology Conventions The Architecture SpeciÞcation This Manual Data ...

Page 120: ...on Storage locations Memory Storage the act of Access Table vii Instruction Field Conventions The Architecture SpeciÞcation Equivalent to BA BB BT crbA crbB crbD respectively BF BFA crfD crfS respectively D d DS ds FLM FM FXM CRM RA RB RT RS rA rB rD rS respectively SI SIMM U IMM UI UIMM 0 0 shaded Table vi Terminology Conventions Continued The Architecture SpeciÞcation This Manual ...

Page 121: ...int arithmetic and some memory management features The core also implements MPC860 speciÞc development support features such as breakpoint and watchpoint mechanisms program ßow tracking data generation and debug mode operation This chapter describes the functional speciÞcations of the core It is based on the PowerPC Microprocessor Family The Programming Environments for 32 Bit Microprocessors whic...

Page 122: ...echanisms Nondestructive use of registers for arithmetic instructions in which the second third and sometimes the fourth operand typically specify source registers for calculations whose results are typically stored in the target register speciÞed by the Þrst operand A precise exception model A ßexible architecture deÞnition that allows certain features to be performed in either hardware or with a...

Page 123: ...ribes the memory model for an environment in which multiple devices can access memory deÞnes aspects of the cache model deÞnes cache control instructions and deÞnes the time base facility from a user level perspective Implementations that conform to the PowerPC VEA also adhere to the UISA but may not necessarily adhere to the OEA PowerPC operating environment architecture OEA ÑThe OEA deÞnes super...

Page 124: ...ction Queue CTR CR LR Branch Processing Unit Integer Unit XER GPR File 32 Entry Load Store Unit LSU Data MMU Tags U Bus Interface Instruction MMU Tags Fetcher 32 Bit 32 Bit One Instruction Retired per Clock 32 Bit One Instruction 32 Bit 32 Bit ALU Performs EA Calculation 32 Bit 32 Bit L Bus Power Dissipation Control Time Base Counter Decrementer JTAG Additional Features INSTRUCTION UNIT Ú BDM inte...

Page 125: ...n set and memory management The MPC860 implements all PowerPC asynchronous exceptions interrupts Ñsystem reset machine check decrementer and external interrupts MPC860 speciÞc exceptions are PowerPC compliant Ñ Separate 32 entry instruction and data translation lookaside buffers TLBs Core speciÞc features Ñ Fully static design Ñ Additional registers that support the MPC860 speciÞc features Ñ The a...

Page 126: ... as breakpoints All instructions enter the CQ along with processor state information that can be affected by the instructionÕs execution Executed arithmetic instructions pass their results both to rename buffers and to the architected registers typically GPRs but to ensure program order instructions remain in the CQ until they can be retired If an exception occurs before the instruction can be ret...

Page 127: ...nch processor instructions including ßow control and CR instructions Table 10 1 describes instruction latencies 4 3 3 1 Branch Operations Because branch instructions can change program ßow and because most branches cannot be resolved at the same time they are fetched program branching can keep a processor from operating at maximum instruction throughput If a branch is mispredicted additional time ...

Page 128: ...issue of nonbranch instructions unless they come in pairs the performance impact of entering branches in the IQ is negligible The core also implements a branch reservation station and static branch prediction so branches can be resolved as early as possible The reservation station allows a branch instruction to pass from the IQ before its condition is ready With the branch out of the way fetching ...

Page 129: ...operands are free and inform the sequencer whether instructions can be dispatched 4 4 Register Set Registers implemented in the MPC860 core can be grouped as follows PowerPC registers The MPC860 implements the user registers deÞned by the UISA and VEA portions of the architecture except for those that support ßoating point operations PowerPC registers implemented on the MPC860 are described in Sec...

Page 130: ...uctions see Table 4 1 of this manual Note the following special cases If an mtspr or mfspr instruction speciÞes an invalid SPR in which spr 0 1 a program exception occurs if the processor is in user mode Valid SPRs are listed in Chapter 5 ÒPowerPC Core Register Set Ó If divw o is used to perform either 0x80000000 1 or anything 0 the contents of rD are 0x8000_0000 and if Rc 1 the contents of the bi...

Page 131: ...its two queues The address queue is a 2 entry queue shared by all load store instructions and the integer data queue is a 2 entry 32 bit queue that holds integer data The LSU has a dedicated writeback bus so that loaded data received from the internal bus is written directly back to the GPRs Figure 4 5 LSU Functional Block Diagram To execute multiple string instructions and unaligned accesses the ...

Page 132: ...ith update instructions the destination address register is written back on the following clock cycle regardless of the address queueÕs state 4 5 3 2 Serializing Load Store Instructions The following load store instructions are not executed until all previous instructions have Þnished Load store multiple instructionsÑlmw stmw Memory synchronization instructionsÑlwarx stwcx sync String instructions...

Page 133: ... single register load store accesses 4 5 3 6 Atomic Update Primitives The lwarx and stwcx instructions are atomic update primitives and are used to set and clear memory reservations Reservation accesses made by the same processor are implemented by the LSU The external bus interface implements memory reservations as they relate to accesses made by external bus devices Accesses made by other intern...

Page 134: ...c notiÞes the LSU of any internal master store access and resets the reservation If a new lwarx instruction address tenure executes successfully it replaces any previous reservation address at the appropriate snoop logic However executing an stwcx instruction cancels the reservation unless an alignment exception is detected 4 6 The MPC860 and the PowerPC Architecture This section describes the rel...

Page 135: ...nges before execution Branch instructions The core implements all UISA instructions deÞned for the branch processor in hardware For details about the performance of various instructions see Table 4 1 Invalid branch instruction forms Bits marked with z in the BO encoding deÞnition default to z 0 and are discarded by the core decoding Thus these instructions yield results of deÞned instructions for ...

Page 136: ...e lwarx and stwcx instructions are implemented according to the PowerPC architecture requirements When memory accessed by the lwarx and stwcx instructions is in the cache allowed mode it is assumed that the system works with the single master in this memory region Therefore if a data cache miss occurs the access on the internal and external buses does not have a reservation attribute The MPC860 do...

Page 137: ...the eieio instruction Time base The time base functions as deÞned by the VEA and supports an additional implementation speciÞc exception The time base is described in Chapter 11 ÒSystem Interface Unit Ó and in Chapter 15 ÒClocks and Power Control Ó Table 4 5 OEA Level Features Functionality Description Machine state register The ßoating point exception mode bits FE0 and FE1 is ignored by the MPC86...

Page 138: ...tures of the MMU hardware are as follows 32 entry fully associative ITLB 32 entry fully associative DTLB Supports up to 16 virtual address spaces Supports 16 access protection groups Supports fast software table search mechanism The MPC860 MMU is described in detail in Chapter 9 ÒMemory Management Unit MMU Ó Reference and change bits No reference bit is supported by the MPC860 However the change b...

Page 139: ...ure UISA except for the time base registers which can be read by user level software and are deÞned by the virtual environment architecture VEA User registers are described in Section 5 1 1 ÒPowerPC RegistersÑUser Registers Ó Ñ Supervisor registers which can be accessed by supervisor software and in some cases are the automatic result of hardware activity such as when an exception is taken and whe...

Page 140: ...d provides a mechanism for testing and branching The bits in the CR are grouped into eight 4 bit Þelds CR0ÐCR7 as shown in Figure 5 1 Figure 5 1 Condition Register CR 1 Extended opcode for mftb 371 rather than 339 2 Any write mtspr to this address causes an implementation dependent software emulation exception Table 5 1 User Level PowerPC Registers Description Name Comments Access Level Serialize ...

Page 141: ...0 0Ð2 are set by an algebraic comparison of the result to zero CR0 3 is copied from XER SO For integer instructions CR 0Ð3 reßects the result as a signed quantity The CR bits are interpreted as shown in Table 5 3 If any portion of the result is undeÞned the value placed into CR0 0Ð3 is undeÞned Note that CR0 may not reßect the true that is inÞnitely precise result if overßow occurs 5 1 1 1 3 XER F...

Page 142: ...mcrxr that cannot overßow 1 OV Overßow Set to indicate that an overßow occurred during execution of an instruction Add subtract from and negate instructions with OE 1 set OV if the carry out of the msb is not equal to the carry out of the msb 1 and clear it otherwise Multiply low and divide instructions with OE 1 set OV if the result cannot be represented in 32 bits mullw divw divwu and clear it o...

Page 143: ...umber Name Comments Serialize Access Decimal SPR 5Ð9 SPR 0Ð4 18 00000 10010 DSISR See the Programming Environments Manual and Section 5 1 2 1 ÒDAR DSISR and BAR Operation Ó Write Full sync Read Sync relative to load store operations 19 00000 10011 DAR See the Programming Environments Manual and Section 5 1 2 1 ÒDAR DSISR and BAR Operation Ó Write Full sync Read Sync relative to load store operatio...

Page 144: ...ments Segment registersÑThe MPC860 does not support memory segments 5 1 2 3 PowerPC Supervisor Level Register Bit Assignments This section describes bit assignments of supervisor level PowerPC registers implemented by the MPC860 For more details see the Programming Environments Manual for 32 Bit Processors 5 1 2 3 1 Machine State Register MSR The 32 bit machine state register MSR is used to conÞgu...

Page 145: ...ement enabled normal operation mode 1 Power management disabled reduced power mode Note Power management functions are implementation dependent If the function is not implemented this bit is reserved 14 Ñ Reserved 15 ILE Exception little endian mode When an exception occurs this bit is copied into MSR LE to select the endian mode for the context established by the exception 16 EE1 External interru...

Page 146: ... 23Ð24 Ñ Reserved 25 IP Exception preÞx The setting of IP speciÞes whether an exception vector offset is prepended with Fs or 0s In the following description nnnnn is the offset of the exception vector See Table 7 1 0 Exceptions are vectored to the physical address 0x000n_nnnn 1 Exceptions are vectored to the physical address 0xFFFn_nnnn The reset value of IP is determined by the IIP bit bit 2 in ...

Page 147: ...rite as a store 569 10001 11001 DC_ADR Section 8 3 2 ÒData Cache Control RegistersÓ Write as a store 570 10001 11010 DC_DAT Section 8 3 2 ÒData Cache Control RegistersÓ Write as a store 784 11000 10000 MI_CTR Section 9 8 1 ÒIMMU Control Register MI_CTR Ó Write as a store 786 11000 10010 MI_AP Section 9 8 10 ÒMMU Access Protection Registers MI_AP MD_AP Ó Write as a store 787 11000 10011 MI_EPN Sect...

Page 148: ...RPN Section 9 8 7 ÒDMMU Real Page Number Register MD_RPN Ó Write as a store 799 11000 11111 M_TW M_SAVE Section 9 8 11 ÒMMU Tablewalk Special Register M_TW Ó Write as a store 824 11001 11000 MD_CAM Section 9 8 12 4 ÒDMMU CAM Entry Read Register MD_CAM Ó Write as a store 825 11001 11001 MD_RAM0 Section 9 8 12 5 ÒDMMU RAM Entry Read Register 0 MD_RAM0 Ó Write as a store 826 11001 11010 MD_RAM1 Secti...

Page 149: ...system reset interrupt are MSR SRR0 and SRR1 no other reset activity occurs Section 7 1 2 1 152 00100 11000 CMPE Write Fetch sync Read Sync relative to load store operations 153 00100 11001 CMPF Write Fetch sync Read Sync relative to load store operations 154 00100 11010 CMPG Write Fetch sync Read Sync relative to load store operations 155 00100 11011 CMPH Write Fetch sync Read Sync relative to lo...

Page 150: ... follows SRR0 SRR1ÑSet to an undeÞned value MSR IP ÑProgrammable through the IIP bit in the hard reset conÞguration word MSR ME ÑCleared ICTRLÑCleared LCTRL1ÑCleared LCTRL2ÑCleared COUNTA 16Ð31 ÑCleared COUNTB 16Ð31 ÑCleared ICRÑCleared no exception occurred DER 2 14 28Ð31 ÑSet all debug speciÞc exceptions cause debug mode entry Reset values for memory mapped registers are provided with individual...

Page 151: ... are numbered consecutively starting with 0 Each number is the address of the corresponding byte Memory operands may be bytes half words words or double words or for the load store multiple and move assist instructions a sequence of bytes or words The address of a memory operand is the address of its Þrst byte that is of its lowest numbered byte 6 1 2 Aligned and Misaligned Accesses The operand of...

Page 152: ...ructions and addressing modes deÞned for the MPC860 These instructions are divided into the following functional categories Integer instructionsÑThese include arithmetic and logical instructions For more information see Section 6 2 4 1 ÒInteger Instructions Ó Load and store instructionsÑThese include integer load and store instructions only For more information see Section 6 2 4 2 ÒLoad and Store ...

Page 153: ...ion the memory contents must be loaded into a register modiÞed and then written to the target location using load and store instructions The description of each instruction includes the mnemonic and a formatted list of operands To simplify assembly language programming a set of simpliÞed mnemonics extended mnemonics in the architecture speciÞcation and symbols is provided for some of the frequentl...

Page 154: ... instructions are encountered so they may be emulated in software as required A deÞned instruction can have invalid forms as described in the following section 6 2 1 3 Illegal Instruction Class Illegal instructions can be grouped into the following categories Instructions that are not implemented in the PowerPC architecture These opcodes are available for future extensions of the PowerPC architect...

Page 155: ...urther additions to the PowerPC architecture 6 2 1 4 Reserved Instruction Class Reserved instructions are allocated to speciÞc implementation dependent purposes not deÞned by the PowerPC architecture An attempt to execute an unimplemented reserved instruction invokes the illegal instruction error handler a program exception See Section 7 1 2 7 ÒProgram Exception 0x00700 Ó for additional informatio...

Page 156: ... Ó for further discussion of effective address generation for load and store operations Branch instructions have three categories of effective address generation Immediate Link register indirect Count register indirect Refer to Section 6 2 4 3 1 ÒBranch InstructionAddress Calculation Ó for further discussion of branch instruction effective address generation 6 2 2 3 Synchronization The synchroniza...

Page 157: ...he illegal instruction program exception handler to be invoked An attempt by a user level program to execute the supervisor level instructions listed below causes the privileged instruction program exception handler to be invoked The MPC860 provides the following supervisor level instructionsÑdcbi mfmsr mfspr mtmsr mtspr rÞ tlbie and tlbsync Note that the privilege level of the mfspr and mtspr ins...

Page 158: ...sist of the following Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate and shift instructions Integer instructions use the content of the GPRs as source operands and place results into GPRs into the XER and into condition register CR Þelds 6 2 4 1 1 Integer Arithmetic Instructions Table 6 2 lists the integer arithmetic instructions for the MP...

Page 159: ...crfD field 1 Implementation Note Attempting to use divw to perform either 0x80000000 1 or anything 0 sets the contents of rD to 0x80000000 and if Rc 1 the contents CR0 are LT 1 GT 0 and EQ 0 SO is set to the correct value 1 Implementation Note In these instructions the L bit is applicable for 64 bit implementations For the MPC860 if L 1 the instruction form is invalid The core ignores this bit and...

Page 160: ...ied Mnemonics Ó in The Programming Environments Manual 6 2 4 1 4 Integer Rotate and Shift Instructions Rotation operations are performed on data from a GPR and the result or a portion of the result is returned to a GPR See Appendix F ÒSimplified Mnemonics Ó in The Programming Environments Manual for a complete list of simpliÞed mnemonics that allows simpler coding of often used functions such as c...

Page 161: ...uctions Load and store instructions are issued and translated in program order however the accesses can occur out of order Synchronizing instructions are provided to enforce strict ordering This section describes the load and store instructions of the MPC860 which consist of the following Integer load instructions Integer store instructions Integer load and store with byte reverse instructions Int...

Page 162: ...ress For these forms the EA is placed into rA and the memory element byte half word word or double word addressed by EA is loaded into rD Table 6 7 lists the integer load instructions Table 6 7 Integer Load Instructions Name Mnemonic Syntax Load Byte and Zero lbz rD d rA Load Byte and Zero Indexed lbzx rD rA rB Load Byte and Zero with Update lbzu rD d rA Load Byte and Zero with Update Indexed lbzu...

Page 163: ...integer load and store with byte reverse instructions When used in a PowerPC system operating with the default big endian byte order these instructions have the effect of loading and storing data in little endian order Likewise when used in a PowerPC system operating with little endian byte order these instructions have the effect of loading and storing data in big endian order For more informatio...

Page 164: ...emory without concern for alignment These instructions can be used for a short move between arbitrary memory locations or to initiate a long move between misaligned memory Þelds When the MPC860 is operating with little endian byte order execution of a load or store string instruction causes the system alignment error handler to be invoked see ÒByte OrderingÓ in Chapter 3 ÒOperand Conventions Ó in ...

Page 165: ...an redirect instruction execution conditionally based on the value of bits in the CR When the branch processor encounters one of these instructions it scans the execution pipelines to determine whether an instruction in progress may affect the particular CR bit If no interlock is found the branch can be resolved immediately by checking the bit in the CR and taking the action deÞned for the branch ...

Page 166: ... for a list of simpliÞed mnemonics 6 2 4 3 3 Condition Register Logical Instructions Condition register logical instructions shown in Table 6 13 and the Move Condition Register Field mcrf instruction are also deÞned as ßow control instructions Table 6 12 Branch Instructions Name Mnemonic Syntax Branch b ba bl bla target_addr Branch Conditional bc bca bcl bcla BO BI target_addr Branch Conditional t...

Page 167: ...PRs and to read from the time base register TBU or TBL 6 2 4 5 1 Move to from Condition Register Instructions Table 6 15 lists the instructions provided by the MPC860 for reading from or writing to the CR 6 2 4 6 Memory Synchronization InstructionsÑUISA Memory synchronization instructions control the order in which memory operations are completed with respect to asynchronous events and the order i...

Page 168: ...dress used for both instructions of the pair Note that the reservation granularity is 16 bytes The lwarx and stwcx instructions are implemented according to the PowerPC architecture requirements The concept behind the use of the lwarx and stwcx instructions is that a processor may load a semaphore from memory compute a result based on the value of the semaphore and conditionally store it back to t...

Page 169: ...quent instructions are dispatched to the execution units It does not affect fetching instructions continue to be fetched up to the instruction queue limit but dispatch stalls until the sync Þnishes The original purpose of the sync instruction was to synchronize coherent memory with other processors in a multiprocessor system it makes sure that memory as seen by one processor is the same as memory ...

Page 170: ...memory operations are completed with respect to asynchronous events and the order in which memory operations are seen by other processors or memory access mechanisms See Chapter 8 ÒInstruction and Data Caches Ó for additional information about these instructions and about related aspects of memory synchronization Table 6 18 lists the VEA memory synchronization instructions for the MPC860 6 2 5 2 1...

Page 171: ...instructions include the following types Cache management instructions Translation lookaside buffer TLB management instructions This section describes the user level cache management instructions deÞned by the VEA See Section 6 2 6 3 ÒMemory Control InstructionsÑOEA Ó for information about supervisor level cache and translation lookaside buffer management instructions The instructions listed in Ta...

Page 172: ... base register TBU or TBL 6 2 6 2 1 Move to from Machine State Register Instructions Table 6 15 lists the instructions provided by the MPC860 for reading from or writing to the MSR Table 6 19 User Level Cache Instructions Name Mnemonic Syntax MPC860 Notes Data Cache Block Touch dcbt rA rB The appropriate cache block is checked for a hit If it is a miss the instruction is treated as a regular miss ...

Page 173: ...m exception handler is invoked or results are boundedly undeÞned 6 2 6 3 Memory Control InstructionsÑOEA This section describes memory control instructions which include the following types Cache management instructions TLB management instructions 6 2 6 3 1 Supervisor Level Cache Management Instruction Table 6 23 describes the only supervisor level cache management instruction See Section 6 2 5 3 ...

Page 174: ...nt register PowerPC compliant assemblers provide the simplified mnemonics listed in ÒRecommended Simplified MnemonicsÓ in Appendix F ÒSimplified Mnemonics Ó in The Programming Environments Manual and listed with some of the instruction descriptions in this chapter Programs written to be portable across the various assemblers for the PowerPC architecture should not assume the existence of mnemonics...

Page 175: ...ss for the vector table resides at 0x000n_nnnn IP 0 or 0xFFFn_nnnn IP 1 Exceptions are handled in supervisor mode After the exception has been handled the handler returns control to the interrupting program As speciÞed in the PowerPC Family The Programming Environments for 32 Bit Implementations the core implements a precise exception model This means that when an exception is taken the following ...

Page 176: ...7 1 2 1 ÒSystem Reset Interrupt 0x00100 Ó 0x00200 Machine check interrupt See Section 7 1 2 2 ÒMachine Check Interrupt 0x00200 Ó 0x00300 DSI A DSI exception is never generated by hardware but software may branch to this location because of an data TLB error or miss exception See Section 7 1 2 3 ÒDSI Exception 0x00300 Ó 0x00400 ISI An ISI exception is never generated by the hardware but software ma...

Page 177: ...nt exception Attempting to execute a ßoating point instruction causes an implementation speciÞc software emulation exception see Section 7 1 3 1 ÒSoftware Emulation Exception 0x01000 Ó regardless of the setting of MSR FP 0x00900 Decrementer See Section 7 1 2 8 ÒDecrementer Exception 0x00900 Ó 0x00A00Ð 0x00B00 Reserved Ñ 0x00C00 System call See Section 7 1 2 9 ÒSystem Call Exception 0x00C00 Ó 0x00D...

Page 178: ...rotection translation error 4 Machine check Fetch error 5 Debug instruction breakpoint 2 Match detection 6 Software emulation exception 2 Attempt to invoke unimplemented feature 73 Privileged instruction Attempt to execute privileged instruction in user mode Alignment Load store checking System call sc instruction Trap Trap instruction 8 DTLB miss 2 Data TLB miss 9 DTLB error 2 Data TLB protection...

Page 179: ...ode as deÞned in Section 37 3 1 1 ÒDebug Mode Enable vs Debug Mode Disable Ó When debug mode is enabled debug mode is entered instead of checkstop state When debug mode is disabled instruction processing is suspended and cannot be restarted without resetting the core An indication that can generate an automatic reset in this condition is sent to the system interface unit See Chapter 11 ÒSystem Int...

Page 180: ...mpleted without exception The instruction must either be a mtspr mtmsr rÞ a memory reference or a memory or cache control instruction Instructions not Þtting these criteria are discarded along with any execution results After the exception handler completes execution resumes with the Þrst instruction that was discarded If all the instructions in the completion queue were allowed to complete execut...

Page 181: ...SRR1 to save the machine state and DSISR to determine the source of the exception An alignment exception occurs when no higher priority exception exists and the implementation cannot perform a memory access for one of the following reasons The operand of lmw stmw lwarx or stwcx is not aligned The instruction is lmw stmw lswi lswx stswi or stswx and the processor is in little endian mode An unalign...

Page 182: ...d with equivalent bits from the MSR Note that depending on the implementation reserved bits in the MSR may not be copied to SRR1 MSR POW 0 ILE Ñ EE 0 PR 0 FP 0 ME Ñ SE 0 BE 0 IP Ñ IR 0 DR 0 RI 0 LE Set to value of ILE DSISR 0Ð14 Cleared 15Ð16 For instructions that use register indirect with index addressingÑset to bits 29Ð30 of the instruction encoding For instructions that use register indirect w...

Page 183: ...a privileged instruction program exception or an illegal instruction program exception may occur instead TrapÑA trap program exception is generated when any of the conditions speciÞed in a trap instruction is met Trap instructions are described in Section 6 2 4 4 ÒTrap Instructions Ó The register settings when a program exception is taken are shown in Table 7 8 When a program exception is taken in...

Page 184: ...e exception is reported If the decrementer is altered by software and if bit 0 is changed from 0 to 1 an exception request is signaled The register settings for the decrementer exception are shown in Table 7 9 When a decrementer exception is taken instruction execution resumes at offset 0x00900 from the physical base address indicated by MSR IP 7 1 2 9 System Call Exception 0x00C00 A system call e...

Page 185: ...ctions If this is unacceptable other debug features can be used See Chapter 37 ÒSystem Development and Debugging Ó for more information Table 7 11 shows register settings for trace exceptions Execution resumes at offset 0x00D00 from the base address indicated by MSR IP Table 7 10 Register Settings after a System Call Exception Register Setting Description SRR0 Set to the effective address of the i...

Page 186: ...r that speciÞes an on core unimplemented register regardless of SPR 0 When executing a mtspr or mfspr that speciÞes an off core unimplemented register and SPR 0 0 or MSR PR 0 no program exception condition In addition the following registers are set Execution resumes at offset 0x01000 from the base address indicated by MSR IP 7 1 3 2 Instruction TLB Miss Exception 0x01100 This type of exception oc...

Page 187: ...page valid bit of this page is cleared in the translation table Note that although the MPC860 does not implement segment registers as they are deÞned by the OEA the concept of segment is retained as the memory space accessible to the level one table descriptors The fetch access violates memory protection The fetch access is to guarded memory Table 7 13 Register Settings after an Instruction TLB Mi...

Page 188: ... after an Instruction TLB Error Exception Register Setting SRR0 Set to the EA of the instruction that caused the exception SRR1 Note that only one of bits 1 3 and 4 will be set 1 1 if the translation of an attempted access is not in the translation tables Otherwise 0 2 0 3 1 if the fetch access was to guarded memory when MSR IR 1 Otherwise 0 4 1 if the access is not permitted by the protection mec...

Page 189: ... EA of the data access that caused the exception Table 7 17 Register Settings after a Debug Exception Register Setting SRR0 For I breakpoints set to the EA of the instruction that caused the exception For L breakpoint set to the EA of the instruction after the one that caused the exception For development port maskable request or a peripheral breakpoint set to the EA of the instruction that the pr...

Page 190: ...umes at the appropriate exception vector Before control passes to the exception handler machine state is saved in SRR0 and SRR1 After an exception handler executes the machine state of the interrupted process is restored typically by executing the rÞ instruction which writes bits from SRR1 to the MSR SRR0 contains the instruction address at which fetching should resume To correctly restore the arc...

Page 191: ...n is restartable This bit does not need to be checked on exception types that are restartable by convention except those previously mentioned When an exception occurs MSR RI is copied to the equivalent bit in SRR1 and cleared When an rÞ instruction is executed MSR RI is copied from SRR1 or software can change the bit by using it the mtmsr instruction The MSR RI bit is intended to be set by the exc...

Page 192: ... 11 1 2 3 4 5 6 7 8 0 Fetch in IQ In dispatch entry IQ0 Execute 5 9 Complete In CQ 6 5 4 3 IH2 IH1 IH4 IH3 IH2 IH1 IH4 IH3 IH2 IH1 7 6 5 4 2 1 3 3 2 Instruction Queue Completion Queue In retirement entry CQ0 2 1 6 IH1 IH2 IH3 IH4 12 IH4 IH3 IH2 IH1 16 17 13 14 15 18 IH4 IH3 IH2 IH1 IH4 IH3 IH2 IH1 IH5 IH4 IH3 IH2 IH6 IH5 IH4 IH3 IH1 IH2 IH1 IH7 IH6 IH5 IH4 IH8 IH7 IH6 IH5 IH3 IH2 IH4 IH3 A B C D I...

Page 193: ...and fetching instructions of the exception handler The interval between D and E requires at least one clock The time between C and E depends on the memory system and the time it takes to fetch the Þrst instruction of the exception handler For full completion queue restore time it is no less then two clocks E The MSR and instruction pointer of the executing process have been saved and control has b...

Page 194: ...error 1 Any Before Faulting fetch or load store Other noninstruction related exceptions Any Before Next instruction to execute Alignment Load store Before Faulting instruction Privileged instruction Any privileged instruction Before Faulting instruction Trap tw twi Before Faulting instruction System call sc After Next instruction to execute Trace Any After Next instruction to execute Debug I break...

Page 195: ...re physically addressed The physical real address tag is stored in the cache directory Both the instruction and data caches have 16 byte cache blocks A cache block is the block of memory that a coherency state describes also referred to as a cache line Two state bits for each data cache block allow encoding for three states Ñ ModiÞed valid sometimes called ÔmodiÞedÕ Ñ UnmodiÞed valid sometimes cal...

Page 196: ...supplies data to the GPRs by means of a 32 bit interface to the load store unit The LSU is directly coupled to the data cache to allow efÞcient movement of data to and from the general purpose registers The load store unit provides all logic required to calculate effective addresses handles data alignment to and from the data cache and provides sequencing for load and store string and multiple ope...

Page 197: ... to select a set and bits A 28Ð29 select a word within a block The tags consist of the high order physical address bits PA 0Ð20 Address translation occurs in parallel with set selection from A 21Ð27 COMP way0 28 29 27 21 20 0 Word select Bidirectional multiplexer 2 1 hit0 HIT Instruction effective address set0 set1 set127 set126 COMP tag0 w0 w1 w2 w3 Valid bit Lock bit tag1 w0 w1 w2 w3 tag127 w0 w...

Page 198: ...Therefore software must maintain instruction cache coherency The MPC860 supports a fast instruction cache invalidate capability as described in Section 8 3 1 2 5 ÒInstruction Cache Invalidate All Command Ó The instruction cache also implements a lock bit for each cache block that allows instructions to be loaded into the instruction cache and lockedÑproviding fast and deterministic execution time ...

Page 199: ...d boundary that is bits A 28Ð31 of the logical effective addresses are zero as a result cache blocks are aligned with page boundaries Note that address bits A 21Ð27 COMP way0 28 31 27 21 20 0 Byte select Bidirectional multiplexer 2 1 hit0 HIT Data effective address set0 set1 set127 set126 COMP tag0 w0 w1 w2 w3 Valid bit Lock bit tag1 w0 w1 w2 w3 tag127 w0 w1 w2 w3 tag126 w0 w1 w2 w3 L R U A r r a ...

Page 200: ...edicated PowerPC cache control instructions This section describes control of the instruction and data caches by the cache control registers Section 8 4 ÒPowerPC Cache Control Instructions Ó describes the PowerPC cache control instructions 8 3 1 Instruction Cache Control Registers The MPC860 implements three special purpose registers SPRs to control the instruction cacheÑthe instruction cache cont...

Page 201: ...rite to it is ignored 1Ð3 Ñ Reserved 4Ð6 CMD Instruction cache command 000 Reserved 001 Cache enable 010 Cache disable 011 Load lock cache block 100 Unlock cache block 101 Unlock all 110 Invalidate all 111 Reserved Note that reading these bits always returns 0b000 7Ð9 Ñ Reserved 10 CCER1 Instruction cache error type 1Ñbus error during an IC_CST load load cache block command 0 No error detected 1 E...

Page 202: ... 4 Instruction Cache Address Register IC_ADR Table 8 2 Instruction Cache Address RegisterÑIC_ADR Bits Name Description 0Ð31 ADR Instruction cache command address When programming the IC_CST CMD load lock cache block and unlock cache block commands IC_ADR contains the physical address in external memory of the desired cache block element When reading the data tags and status contained within the in...

Page 203: ...ogram order In addition correct operation of the instruction cache relies on software following the procedures described in Section 8 5 5 ÒUpdating Code And Memory Region Attributes Ó Note that when the instruction cache is executing a command it stops handling CPU requests which can result in machine stalls 8 3 1 2 1 Instruction Cache Enable Disable Commands The instruction cache enable command I...

Page 204: ... completed without errors After the load lock cache block command is written to the IC_CST register the cache checks if the block containing the byte addressed by IC_ADR ADR is in the cache hit If it is in the cache the block is locked If the block is not in the cache a normal miss sequence is initiated see Section 8 5 2 ÒInstruction Cache Miss Ó for more information After the addressed block is p...

Page 205: ...s the unlock all command in one clock cycle 8 3 1 2 5 Instruction Cache Invalidate All Command The instruction cache invalidate all command IC_CST CMD 0b110 causes all unlocked valid blocks in the instruction cache to be marked invalid As a result of the invalidate all command the LRU bits of all cache blocks point to either the unlocked way or to way 0 if both ways are unlocked There are no error...

Page 206: ...iate command in DC_CST CMD 1 DFWT Data cache forced write through 0 The write through behavior of the data cache is determined by the write through memory cache access attribute the W bit in the MMU 1 Writes to the data cache are forced to write through to memory Note that this is a read only bit Any attempt to write to it is ignored This bit is programmed by issuing the appropriate command in DC_...

Page 207: ...achine check exception is generated when this bit is set 0 No error detected 1 Error detected Note that this is a read only sticky bit set only by the MPC860 when an error is detected Reading this bit clears it 11 CCER2 Data cache error type 2 This bit indicates one of two possible errorsÑeither a bus error during DC_CST load load cache block or ßush cache block command or there is no unlocked way...

Page 208: ...he block unlock cache block and ßush cache block commands DC_ADR contains the physical address of the desired cache block element in external memory When reading the data tags and status contained within the data cache DC_ADR is used to qualify what is to be read according to Table 8 7 See Section 8 3 2 1 ÒReading Data Cache Tags and Copyback Buffer Ó for more information BIT 0 1 2 3 4 5 6 7 8 9 1...

Page 209: ... Þeld DC_ADR 21Ð27 shown in Table 8 11 determines which word of the cache block in the copyback buffer is read 8 3 2 2 DC_CST Commands All DC_CST commands except the load lock cache block and ßush cache block commands are executed immediately after writing to the DC_CST register and do not generate any errors Therefore there is no need to check the error type bits in the DC_CST register except whe...

Page 210: ...ot affected by invalidate commands To load lock one or more cache blocks 1 Read the DC_CST error type bits to clear them 2 Write the address of the cache block to be locked to the DC_ADR register 3 Write the load lock cache block command DC_CST CMD 0b0110 to the DC_CST register 4 Repeat steps 2 and 3 to load lock another cache block 5 Read DC_CST CCER2 to determine if the sequence completed withou...

Page 211: ...ck cycle 8 3 2 2 5 Data Cache Invalidate All Command The data cache invalidate all command DC_CST CMD 0b1100 causes all unlocked valid blocks in the data cache to be marked invalid regardless of whether the data is modiÞed Therefore this command may effectively destroy modiÞed data To invalidate the entire data cache the invalidate all command should be preceded by an unlock all command Note that ...

Page 212: ... does not broadcast cache control instructions nor does it snoop such broadcasts A TLB miss exception is generated if the effective address of one of these instructions cannot be translated and data address relocation is enabled A TLB error exception is generated if these instructions encounter a TLB protection violation 8 4 1 Instruction Cache Block Invalidate icbi The effective address is comput...

Page 213: ...y and all bytes of the block are cleared and the tag is marked as modiÞed valid The dcbz instruction executes regardless of whether the cache block is locked but if the cache is disabled an alignment exception is generated If the page containing the byte addressed by the EA is caching inhibited or write through then the system alignment exception handler is invoked 8 4 4 Data Cache Block Store dcb...

Page 214: ...Þned in the PowerPC architecture This instruction is treated as a store with respect to address translation and memory protection If the address hits in the cache the cache block is placed in the invalid state regardless of whether the data is modiÞed If the address misses in the cache no action is taken Because this instruction may effectively destroy modiÞed data it is privileged that is dcbi is...

Page 215: ...miss the 4 word block buffer holds the last block retrieved from the instruction cache the last hit Note that if one of these buffers contains the requested instruction it is also considered a cache hit To minimize power consumption the MPC860 can detect that one of the buffers contains the requested instruction and service the instruction request from the buffers without activating the instructio...

Page 216: ...ultiplexer and word select multiplexer As shown in Figure 8 2 bits 28Ð29 of the instruction address are used to select one word of the cache block which is transferred to the instruction sequencer in the core 8 5 2 Instruction Cache Miss On an instruction cache miss the address of the missed instruction is driven on the internal bus with a 4 word burst transfer read request The transfer begins wit...

Page 217: ...er if it is a cache miss the miss sequence is not initiated in most cases until the core Þnishes the branch evaluation 8 5 4 Fetching Instructions from Caching Inhibited Regions The caching inhibited caching allowed attributes of a memory region are programmed in the memory management unit MMU To improve performance when fetching instructions from caching inhibited regions the MPC860 loads the bur...

Page 218: ...aults to the guarded attribute See Chapter 9 ÒMemory Management Unit MMU Ó for more information A data cache access begins with a load or store request from the load store unit LSU in the core The data cache has a 32 bit data path to and from the load store unit allowing for a 4 byte transfer per cycle As shown in Figure 8 2 bits 21Ð27 of the data address provide the index to select a set 0Ð127 wi...

Page 219: ...rst priority to invalid blocks If both blocks in the set are marked invalid the block in way 0 is selected If neither of the two blocks in the selected set are invalid then the least recently used block is selected for replacement If the replacement block is marked modiÞed valid then it is temporarily stored in a copyback buffer to be written to memory later Locked cache blocks are never replaced ...

Page 220: ...remain unchanged If a bus error is encountered during the write operation to memory the cache block is still updated but a machine check exception is generated 8 6 3 2 Data Cache Store Miss in Write Through Mode In the case of a store miss in write through mode the data is only written to memory not to the data cache This is sometimes referred to as aÔno allocateÕstore miss because the data cache ...

Page 221: ... marked modiÞed valid The data cache does not support further requests until the entire block is written to the cache array If the machine has stalled waiting for the store to complete execution is allowed to resume when the cache block is written into the cache array If a bus error is encountered while loading the target data cache block even on a word not accessed by the load store unit then the...

Page 222: ...other processor to an address that matches the reservation address will cancel the reservation The stwcx instruction does not check the reservation for a matching address The stwcx instruction is only required to determine whether a reservation exists The stwcx instruction performs a store word operation only if the reservation exists If the reservation has been cancelled for any reason then the s...

Page 223: ...ation after reset initialize the instruction cache by performing the following 1 Write the unlock all command IC_CST CMD 0b101 to the IC_CST register 2 Write the invalidate all command IC_CST CMD 0b110 to the IC_CST register 3 Write the cache enable command IC_CST CMD 0b001 to the IC_CST register Similarly to ensure proper operation after reset initialize the data cache by performing the following...

Page 224: ... regions Misses are loaded only into the burst buffer hits are loaded from the cache array and the LRU bits are updated If the debug routine is not in the instruction cache it is loaded from memory like any other miss and the cache state remains the same as before the freeze signal was asserted For performance reasons it may be preferable to run the debug routine from the cache To load the debug r...

Page 225: ...erviced from the cache array but the cache LRU and state bits are unchanged When the internal freeze signal is asserted store hits and misses are treated as write through accesses but the LRU bits in the data cache array are not updated For the dcbz instruction data is written both into data cache and memory but the LRU bits in the data cache array are not updated For the dcbst dcbf dcbi instructi...

Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...

Page 227: ... and data MMUs The preÞx Mx_ indicates a reference to both the instruction and data MI_ and MD_ versions of the register The MMU supports two protection modesÑPowerPC mode with extended encoding and domain manager mode which provides programmable overrides to page protection settings 9 1 Features The following is a list of the MMUÕs important features Multiple page sizesÑ4 16 512 Kbyte or 8 Mbyte ...

Page 228: ...nce Ñ 1 clock zero wait state access for a data cache hit and for an instruction cache hit when the access is from the same page as the previous access Ñ 1 clock penalty for other TLB hit instruction accesses Low power consumption 9 2 PowerPC Architecture Compliance The MPC860 core complies largely with the MMU as it is deÞned by the OEA with the following differences The MPC860 does not implement...

Page 229: ...e block The default is conÞgured by MD_CTR WTDEF Also when translation is disabled real mode the entire memory space is treated as guarded by default The implications of this are 1 Speculative load store accesses are stalled until they are no longer speculative 2 Speculative instruction fetches outside of the current real mode page are stalled until they are no longer speculative The size of real ...

Page 230: ...n is enabled Because data transfers have less locality than instruction fetches the DMMU does not implement a fast TLB mechanism The DTLB is accessed for each transfer simultaneously with the data cache tag read hence there is no time penalty Data Instruction Fetch Same page Fast TLB Hit TLB Hit TLB reload read page description from external memory to TLB Use current page description Yes No Yes No...

Page 231: ... is a programming error Subpage validity ßags can be manipulated to implement 1Ð4 Kbyte pages or any other combination of 1 Kbyte subpages However all subpages of an effective page frame must map to the same physical page During translation the EA the privilege level MSR PR and CASID are provided to the TLB as shown in Figure 9 3 In the TLB the EA and CASID are compared with each entryÕs EPN and A...

Page 232: ...ontains 16 Þelds The Þeld content is used according to the group protection mode To be consistent with the PowerPC OEA the APG value should match the four msbs of the effective page number To override protection using APG use it on blocks of addresses which are deÞned by the 4 msbs of the effective page number If APG is not to be used for a particular block set the GP for that block to ÔclientÕ in...

Page 233: ...MD_CTR TWAM 1 Ñ Mx_CTR PPM 1 For pages larger than 4 Kbytes bits 20Ð27 of the level two descriptor take on the meaning described in the right side of Table 9 4 For 4 Kbyte pages set the subpage validity ßags bits 20Ð27 to subpage protection mode for 4 subpages see Table 9 4 In this mode the MMU page tables deÞned for the software tablewalk resolve to a single level two descriptor entry for a 4 Kby...

Page 234: ...the level two descriptor can be set differently for each of these entries Ñ To deÞne two different 2 Kbyte pages create four level two descriptors but set the subpage validity ßags in pairs such that entry one 0b1100 entry two 0b1100 entry three 0b0011 entry four 0b0011 The other Þelds of the ÔpairedÕ level two descriptors must be the same for each of the pairs Other combinations are also possible...

Page 235: ...e effects of CI and WT attributes in the MPC860 The G attribute is used to map I O devices that are sensitive to speculative out of order accesses An attempted speculative access to a page marked guarded G 1 stalls until either the access is nonspeculative or is canceled by the core Attempting to fetch from guarded memory causes an implementation speciÞc instruction TLB error interrupt 9 7 Transla...

Page 236: ...ble Base Level 1 Index 00 Level 1 Index 0 19 20 31 9 10 Level 2 Index Page Offset 0 19 Level 1 Table Pointer M_TWB Level 1 Descriptor 0 Level 1 Descriptor 1 Level 1 Descriptor N Level 1 Descriptor 1023 Level 2 Table Base Level 2 Index 20 Bit 10 Bit 00 10 Bit Level 2 Descriptor 0 Level 2 Descriptor 1 Level 2 Descriptor N Level 2 Descriptor 1023 Physical Page Address Page Offset 20 Bit 20 Bit 20 for...

Page 237: ...to Þnd the level two page descriptor For pages larger than 4 Kbytes the entry in the level two table must be duplicated according to page size as shown in Table 9 1 Table 9 1 Identical Entries Required in Level One Level Two Tables Page Size Identical Entries Required in Level One Table Identical Entries Required in Level Two Table MD_CTR TWAM 0 MD_CTR TWAM 1 MD_CTR TWAM 0 MD_CTR TWAM 1 1 Kbyte 1 ...

Page 238: ...o get the level one page descriptor For 8 Mbyte pages there must be eight identical entries in the level one table for EA 9Ð11 20 for 1 Kbyte 20 for 4 Kbyte 18 for 16 Kbyte 13 for 512 Kbyte 9 for 8 Mbyte Level 1 Table Base Level 1 Index 00 Level 1 Index 0 21 31 11 Level 2 Index Page Offset 0 Level 1 Table Pointer M_TWB Level 1 Descriptor 0 Level 1 Descriptor 1 Level 1 Descriptor N Level 1 Descript...

Page 239: ... Descriptor Table 9 3 describes the level one descriptor format supported by the hardware to minimize the software tablewalk routine Table 9 2 Number of Replaced EA Bits per Page Size Page Size Number of Replaced EA Bits 1 Kbyte 20 4 Kbyte 20 16 Kbyte 18 512 Kbyte 13 8 Mbyte 9 Table 9 3 Level One Segment Descriptor Format Bits Name Description 0Ð19 L2BA Level 2 table base address Bits 18Ð19 should...

Page 240: ...ion Pages Supervisor User Extended encoding 00 No access No access 01 Executable No access 1x Reserved PowerPC encoding 00 Executable No access 01 Executable Executable 1x Executable Executable For Data Pages Supervisor User Extended encoding 00 No access No access 01 R O No access 1x Reserved PowerPC encoding 00 R W No access 01 R W R O 10 R W R W 11 R O R O 22 PP 2nd 1 Kbyte subpage 0 Bits 20Ð21...

Page 241: ...register 789 9 8 4 MD_TWC DMMU tablewalk control register 797 9 8 5 MI_RPN IMMU real physical page number port 790 9 8 6 MD_RPN DMMU real physical page number register 798 9 8 7 Tablewalk Assist Registers M_TWB MMU tablewalk base register 796 9 8 8 Protection Registers M_CASID CASID register 793 9 8 9 MI_AP IMMU access protection register 786 9 8 10 MD_AP DMMU access protection register 794 Scratc...

Page 242: ...ranslation is enabled PPM determines how Mx_RPN is interpreted See Table 9 11 and Table 9 12 0 Page resolution of protection 1 1 Kbyte resolution of protection for 4 Kbyte pages 2 CIDEF Default value for instruction cache inhibit attribute when the IMMU is disabled MSR IR 0 3 Ñ Reserved Ignored on write Returns 0 on read 4 RSV4I Reserve 4 ITLB entries See Section 9 10 2 ÒLocking TLB Entries Ó 0 IT...

Page 243: ...de 1 PPM Page protection mode 0 Page resolution of protection 1 1 Kbyte resolution of protection for 4 Kbyte pages 2 CIDEF CI default when the DMMU is disabled MSR DR 0 3 WTDEF WT default when the DMMU is disabled MSR DR 0 4 RSV4D Reserve four DTLB entries See Section 9 10 2 ÒLocking TLB Entries Ó 0 DTLB_INDX decremented modulo 32 1 DTLB_INDX decremented modulo 28 5 TWAM Tablewalk assist mode 0 1 ...

Page 244: ...1 12 13 14 15 Field EPN Reset 0000_0000_0000_0000 R W R W Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field EPN Ñ EV Ñ ASID Reset Ñ 0 0 0 0 R W R W R R W R R W SPR 787 Figure 9 8 IMMU DMMU Effective Page Number Register Mx_EPN Table 9 8 Mx_EPN Field Descriptions Bits Name Description 0Ð19 EPN Effective page number for TLB entry Default value is the EA of the last ITLB DTLB miss 20Ð21 Ñ Res...

Page 245: ...G PS Ñ V Reset 0 Ñ Ñ Ñ 0 Ñ R W R W R W R W R W R W R W SPR 789 Figure 9 9 IMMU Tablewalk Control Register MI_TWC Table 9 9 MI_TWC Field Descriptions Bits Name Description 0Ð22 Ñ Reserved Ignored on write Returns 0 on read 23Ð26 APG Access protection group Up to 16 protection groups supported Default for ITLB miss is 0 27 G Guarded memory attribute for entry 0 Nonguarded memory default for ITLB mis...

Page 246: ...9 10 MD_TWC Field Descriptions Bits Name Description Write Read Write Read 0Ð19 L2TB L2TB Tablewalk level two table base value 20Ð22 Ñ L2INDX Ignore Level two table index Returns MD_EPN 10Ð19 when MDCTR TWAM 1 Returns MD_EPN 12Ð21 when MDCTR TWAM 0 23Ð26 APG Access protection group Up to 16 protection groups are supported Set to 0000 on a DTLB miss 27 G Guarded memory attribute of the entry 0 Nong...

Page 247: ...Supervisor User 00 No access No access 01 Executable No access 1x Reserved Reserved PowerPC Encoding Supervisor User 00 Executable No access 01 Executable Executable 1x Executable Executable 22 0 Bits 20Ð21 contain PowerPC encoding 1 Bits 20Ð21 contain extended encoding 23 Reserved 24Ð25 MD_CTR PPCS 0 For 1 Kbyte pages in mode 3 set to the appropriate subpage validity see Section 9 5 ÒProtection R...

Page 248: ...ubpages 1Ð4 in a 4 Kbyte page Supervisor User 00 No access No access 01 R W No access 10 R W R O 11 R W R W Extended Encoding Supervisor User 00 No access No access 01 R O No access 1x Reserved PowerPC Encoding Supervisor User 00 R W No access 01 R W R O 10 R W R W 11 R O R O 22 0 Bits 20Ð21 contain PowerPC encoding 1 Bits 20Ð21 contain extended encoding 23 Change bit for DTLB entry Set to 1 by de...

Page 249: ...ry 30 CI Cache inhibit attribute for the entry 31 V Entry valid indication Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field L1TB L1TB L1INDX Ñ Reset Ñ 00 R W R W SPR 796 Figure 9 13 MMU Tablewalk Base Register M_TWB Table 9 13 M_TWB Field Descriptions Bits Name Description 0Ð19 L1TB Tablewalk level one base value 20Ð29 L1INDX Level one table index Ign...

Page 250: ...D Compared with ASID Þeld of a TLB entry to qualify a match Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 GP8z GP9 GP10 GP11 GP12 GP13 GP14 GP15 Reset Ñ R W R W SPR 786 MI_AP 794 MD_AP Figure 9 15 MMU Access Protection Registers MI_AP MD_AP Table 9 15 MI_AP MD_AP Field Descriptions Bits Name Domain Manager Mode Mx_CT...

Page 251: ...ntent addressable memory of the MI_CAM register is read it contains the effective address and page sizes of an entry indexed by MI_CTR ITLB_INDX MI_CAM is updated only by writing to it Table 9 16 describes the MI_CAM Þelds Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field EPN Reset Ñ R W R Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field EPN PS ASID SH SPV Reset Ñ R W R W SPR 816 Figure 9 1...

Page 252: ...ubpage 2 Address 20Ð21 10 is not valid 1 Subpage 2 Address 20Ð21 10 is valid 31 0 Subpage 3 Address 20Ð21 11 is not valid 1 Subpage 3 Address 20Ð21 11 is valid Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field RPN Reset Ñ R W R Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field RPN PS_B CI APG SFP Reset Ñ R W R SPR 817 Figure 9 18 IMMU RAM Entry Read Register 0 MI_RAM0 Table 9 17 MI_RAM0 Fiel...

Page 253: ...tch is permitted 31 0 Subpage 3 Address 20Ð21 11 Supervisor fetch is not permitted 1 Subpage 3 Address 20Ð21 11 Supervisor fetch is permitted Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ Reset 0 R W R Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Ñ UFP PV G Reset 0 Ñ Ñ Ñ R W R SPR 818 Figure 9 19 IMMU RAM Entry Read Register 1 MI_RAM1 Table 9 18 MI_RAM1 Field Descriptions Bits Nam...

Page 254: ...3 4 5 6 7 8 9 10 11 12 13 14 15 Field EPN Reset Ñ R W R W Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field EPN SPVF PS SH ASID Reset Ñ R W R W SPR 824 Figure 9 20 DMMU CAM Entry Read Register MD_CAM Table 9 19 MD_CAM Field Descriptions Bits Name Description 0Ð19 EPN Effective page number 20 SPVF Subpage validity ßags 0 Subpage 0 address 20Ð21 00 is not valid 1 Subpage 0 address 20Ð21 00 i...

Page 255: ...ASID 1 ASID comparison is disabled for the entry 28Ð31 ASID Address space ID of the DTLB entry to be compared with M_CASID CASID Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field RPN Reset Ñ R W R Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field RPN PS APGI G WT CI Ñ Reset Ñ R W R W SPR 825 Figure 9 21 DMMU RAM Entry Read Register 0 MD_RAM0 Table 9 20 MD_RAM0 Field Descriptions Bits Name De...

Page 256: ...Reserved Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ Reset 0 R W R Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field RES C EVF SA SAT URP0 UWP0 URP1 UWP1 URP2 UWP2 URP3 UWP3 Reset 0 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ R W R SPR 826 Figure 9 22 DMMU RAM Entry Read Register 1 MD_RAM1 Table 9 21 MD_RAM1 Field Descriptions Bits Name Description 0Ð16 Ñ Reserved 17 C Change bit for DTLB entry 0 Unchan...

Page 257: ... 00 User read access is permitted 25 UWP0 User write permission page zero 0 Subpage 0 address 20Ð21 00 User write access is not permitted 1 Subpage 0 address 20Ð21 00 User write access is permitted 26 URP1 0 Subpage 1 address 20Ð21 01 User read access is not permitted 1 Subpage 1 address 20Ð21 01 User read access is permitted 27 UWP1 0 Subpage 1 address 20Ð21 01 User write access is not permitted ...

Page 258: ...U Exceptions Exception Cause ITLB miss MSR IR 1 and an attempt is made to fetch an instruction from a page whose EPN cannot be translated by the ITLB Tablewalk software is responsible for loading information for the missed page from the translation table See Section 9 10 1 1 ÒTranslation Reload Examples Ó and Section 7 1 3 2 ÒInstruction TLB Miss Exception 0x01100 Ó DTLB miss MSR DR 1 and an attem...

Page 259: ...lacement algorithm thus enabling the user to lock translation entries into them by specially conÞguring the TLB replacement counters dtlb_swtw mtspr M_TW R1 Save R1 mfspr R1 M_TWB Load R1 with level 1 pointer lwz R1 R1 Load level 1 page entry mtspr MD_TWC R1 Save level 2 base pointer and level 1 attributes mfspr R1 MD_TWC Load R1 with level 2 pointer while taking page size into account lwz R1 R1 L...

Page 260: ...y in the TLB is as follows 1 Disable the TLB by clearing MSR IR or MSR DR as needed 2 Clear MI_CTR RSV4I MD_CTR RSV4D 3 Invalidate the EA of the reserved page by using tlbia or tlbie 4 Set MI_CTR ITLB_INDX MD_CTR DTLB_INDX to the appropriate value between 27 and 31 5 Load Mx_EPN with the effective page number the ASID of the reserved page and set EV 9 10 4 TLB Invalidation Executing tlbie invalida...

Page 261: ...set the four reserved entries are not invalidated Software can explicitly invalidate one or more of these entries by setting MD_CTR DTLB_INDX or MI_CTR ITLB_INDX negating MD_EPN EV or MI_EPN EV and writing to the appropriate MD_RPN or MI_RPN The TLBs are not invalidated automatically on reset but are disabled However they must be invalidated under program control during initialization ...

Page 262: ...9 36 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...

Page 263: ...a cache load Writeback arbitration Private writeback bus load Fastest external load data cache miss Full completion queue CQ Branch instruction handling Branch prediction All examples assume an instruction cache hit 10 1 1 Data Cache Load with a Data Dependency Figure 10 1 shows a data cache load with zero wait states The sub instruction depends on the value loaded to r12 which causes a bubble in ...

Page 264: ...ÑExample 1 In this example the addic instruction is dependent on sub rather than on mulli Although the writeback of the mulli is delayed two clocks there is no bubble in the execution stream mulli r12 r4 3 sub r3 r15 3 addic r4 r3 1 Figure 10 3 Writeback Arbitration TimingÑExample 2 lwz sub mulli addi addic Fetch Decode Read Execute Writeback L Address Drive L Data Load Write Back lwz sub Bubble a...

Page 265: ...ndent on the value read by the load It causes three bubbles in the execution stream Assuming SCCR EBDF 00 the external clock CLKOUT is shifted 90 from the internal clock GCLK1 lwz r12 64 SP sub r3 r12 3 addic r4 r14 1 Figure 10 5 External Load Timing ori xor load lwz sub and xor cror ori sub and cror ori load sub lwz lwz lwz lwz sub lwz cror and and xor xor ori GCLK1 E Data Fetch Decode Read Execu...

Page 266: ...iming 10 1 6 Branch Instruction Handling In Figure 10 7 the lwz instruction accesses internal memory with one wait state The IQ and parallel operation of the BPU allows the two bubbles caused by the bl issue and execution to overlap the two bubbles caused by the load Issuing bl causes a bubble because it does no work lwz r12 64 SP sub r3 r12 3 addic r4 r14 1 bl func func mulli r5 r3 3 addi r4 3 r0...

Page 267: ...predicted path cannot be dispatched before the condition is resolved while mulli r3 r12 r4 addi r4 3 r0 lwz r12 64 r2 cmpi 0 r12 3 addic r6 r5 1 blt cr0 while Figure 10 8 Branch Prediction Timing addic lwz lwz sub bl Bubble addic mulli sub sub Bubble mulli lwz Bubble lwz lwz bl lwz bl sub addic addic mulli Fetch Decode Read Execute Writeback L Address Drive L Data Load Writeback Branch Decode Bran...

Page 268: ...mttbu See Section 10 2 3 ÒAccessing Off Core SPRs Ó Serialize 11 Serialize 1 LSU Yes Move from SPRs external to core mfspr mftb mftbu Load latency 1 LSU No Move from SPRs internal to core mfspr2 1 Ñ See list 3 Move from mfcr mfmsr Serialize 1 Ñ See list 4 Integer arithmetic addi add addis subf addic subÞc addic addc adde subfc subfe addme addze subfme subfze neg 1 IU No Integer divide divw divwu M...

Page 269: ...d Instructions Ó Section 4 5 3 5 ÒUnaligned Accesses Ó and Section 10 2 1 ÒLoad Store Instruction Timing Ó 1 N denotes the number of registers transferred Memory synchronization lwarx stwcx Serialize 2 LSU Yes Move CR from XER mcrxr Serialize 1 LSU Yes Move to from SPR Debug DAR DSISR mtspr mfspr Serialize 1 LSU Yes String instructions lswi lswx stswi stswx See Section 10 2 2 ÒString Instruction L...

Page 270: ...ccesses to off core SPRs by using a special cycle on the internal bus See Section 5 1 3 1 ÒAccessing SPRs Ó If the access ends in a bus error a software emulation exception is taken All write operations to off core SPRs mtspr are previously synchronized In other words the instruction is not taken until all prior instructions terminate 0x00 00 01 02 03 0x04 04 05 06 07 2 bus cycles 0x08 08 09 0A 0B...

Page 271: ...ls system start up initialization and operation protection as well as the external system bus Chapter 12 ÒReset Ó describes the behavior of the MPC860 at reset and start up Suggested Reading Supporting documentation for the MPC860 can be accessed through the world wide web at http www motorola com SPS RISC netcomm and at http www mot com SPS PowerPC This documentation includes technical speciÞcati...

Page 272: ...nal encoding or a bit Þeld indicates a donÕt care n Indicates an undeÞned numerical value Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document Note that the meanings for some acronyms such as SDR1 and DSISR are historical and the words for which an acronym stands may not be intuitively obvious Table viii Acronyms and Abbreviated Terms Term Meaning B...

Page 273: ...te msb Most signiÞcant bit MSR Machine state register PCI Peripheral component interconnect RISC Reduced instruction set computing RTOS Real time operating system Rx Receive SPR Special purpose register TB Time base register TLB Translation lookaside buffer Tx Transmit Table viii Acronyms and Abbreviated Terms Continued Term Meaning ...

Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...

Page 275: ...ol Ó The external bus interface handles the transfer of information between internal buses and the memory or peripherals in the external address space The MPC860 is designed to allow external bus devices to request and obtain system bus mastership Chapter 3 ÒHardware Interface Overview Ó describes bus operation The memory controller module provides a glueless interface to many types of memory devi...

Page 276: ...rupt that is selected by the system protection control register SYPCR if software fails to service this timer after a certain period After system reset the timer if enabled selects a maximum time out period and asserts SRESET or NMI system reset interrupt if the time out is reached This timer can be disabled or its time out period can be changed in SYPCR Once SYPCR is written it cannot be written ...

Page 277: ... value programmed in the alarm register The RTC is clocked by PITRTCLK Freeze supportÑThe SIU determines whether the software watchdog timer PIT timebase decrementer and real time clock should continue to run in freeze mode Figure 11 1 is a block diagram of the system conÞguration and protection logic Figure 11 1 System Configuration and Protection Logic 11 3 Multiplexing SIU Pins Due to the limit...

Page 278: ...S6 CE1_B is asserted When a transfer matches either memory controller bank 7 or any PCMCIA bank mapped to slot B CS7 CE2_B is asserted WE0 BS_AB0 IORD WE1 BS_AB1 IOWR WE2 BS_AB2 PCOE WE3 BS_AB3 PCWE Dynamically active depending on the machine GPCM UPMB or PCMCIA interface assigned to control the required slave GPL_A0 GPL_B0 Dynamically active depending on the machine UPMA or UPMB assigned to contr...

Page 279: ...se DeÞnes the base address of the internal memory space At reset ISB can be conÞgured to one of four addresses and changed to any value by the software The number of programmable ISB bits and the resolution of the location of internal space depends on the implementationÕs internal memory space In the MPC860 all 16 bits can be programmed Chapter 2 ÒMemory Map Ó describes the internal memory map Sec...

Page 280: ...bitration is performed 1 External arbitration is assumed 1Ð3 EARP External arbitration request priority DeÞnes the priority of the external masterÕs arbitration request relative to requests by internal modules Valid when EARB is cleared 000 lowest priority and 111 highest however the internal UPM based refresh cycles always have a higher priority and will preempt any external master if the interna...

Page 281: ...tions as VFLS 0Ð1 IP_B3 IWP2 VF2 functions as VF2 IP_B4 LWP0 VF0 functions as VF0 IP_B5 LWP1 VF1 functions as VF1 OP2 MODCK1 STS functions as STS ALE_B DSCK AT1 functions as AT1 IP_B2 AT2 functions as AT2 IP_B6 DSDI AT0 functions as AT0 IP_B7 PTR AT3 functions as AT3 OP3 MODCK2 DSDO functions as OP3 11Ð12 DBPC Debug port pins conÞguration Determines the active pins for the development port Setting...

Page 282: ...master enable ConÞgures how the memory controller refers to external asynchronous masters initiating a transaction If AEME 1 the memory controller interprets any assertion of AS as an external asynchronous master initiating a transaction If it is reset the memory controller ignores the value of AS 23 SEME Synchronous external master enable ConÞgures how the memory controller refers to synchronous ...

Page 283: ...t period in 8 system clock resolution for the bus monitor maximum timeout is 2 040 clocks 24 BME Bus monitor enable Controls bus monitor operation during internal to external bus cycles 0 Disable the bus monitor 1 Enable the bus monitor Note If the bus monitor is disabled transfer error conditions do not cause TEA to be asserted 28 SWF Software watchdog freeze 0 The software watchdog timer continu...

Page 284: ... transfer error acknowledge Set if the cycle is terminated by an externally generated TEA when an instruction fetch is initiated 19 ITMT Instruction transfer monitor timeout Set if the cycle is terminated by a bus monitor timeout when an instruction fetch is initiated 20Ð23 IPB 0Ð3 Instruction parity error on bytes 0Ð3 Each byte lane has four parity error status bits one is set for the byte that h...

Page 285: ...lue to a key register will lock its associated SIU register For example writing a 0x55CCAA33 to the RTCK key register allows the RTC register to be written The key registers are write only a read of the Table 11 6 Key Registers Offset Name Size System Integration Timers Keys 0x300 TBSCRKÑTimebase status and control register key 32 bits 0x304 TBREFAKÑTimebase reference register A key 32 bits 0x308 ...

Page 286: ... or unlocked Figure 11 6 Register Lock Mechanism For more information on key registers see Section 15 5 7 3 ÒRegister Lock Mechanism Protecting SIU Registers in Power Down Mode Ó 11 5 System ConÞguration The SIU module conÞguration register SIUMCR is used for conÞguring external bus arbitration logic external master support and pin multiplexing See Section 11 4 2 ÒSIU Module ConÞguration Register ...

Page 287: ... a priority level Each SIU internal interrupt source generated by the CPMÕs interrupt controller CPIC can be assigned by the software to one of eight additional internal interrupt priority levels described in Chapter 35 ÒCPM Interrupt Controller Ó Section 11 5 3 1 ÒNonmaskable InterruptsÑIRQ0 and SWT Ó describes how IRQ0 operates differently from other IRQ signals and how the operation is conÞgura...

Page 288: ...the external interrupt Table 11 7 shows interrupt priorities Table 11 7 Priority of SIU Interrupt Sources Number Priority Level Interrupt Source Interrupt Code SIVEC INTC 0 Highest IRQ0 0000_0000 1 Internal Level 0 0000_0100 2 IRQ1 0000_1000 3 Internal Level 1 0000_1100 4 IRQ2 0001_0000 5 Internal Level 2 0001_0100 6 IRQ3 0001_1000 7 Internal Level 3 0001_1100 8 IRQ4 0010_0000 9 Internal Level 4 0...

Page 289: ...onmaskable InterruptsÑIRQ0 and SWT Figure 11 9 is a logical representation of IRQ0 Figure 11 9 IRQ0 Logical Representation Table 11 8 describes the differences between IRQ0 and other IRQ interrupts Start SIU Interrupt Occurs Set Bit in SIPEND Assert External Interrupt End Bit Set in SIMASK Bit Not Set in SIMASK to Core MUX Level Edge FF Q Q R MUX Level Edge SIEL ED0 SIEL ED0 NMI SIPEND IRQ0 IRQ0 S...

Page 290: ...ervice is requested if they are not masked by the corresponding SIMASK bit These bits reßect the status of the internal requesting device and are cleared when the appropriate actions are software initiated in the device Writing to these bits has no effect Note that IRQ0 can be masked in only a very limited sense If SIEL ED0 1 edge sensitive and SIPEND IRQ0 is not cleared in the ISR further asserti...

Page 291: ...00 0x012 Figure 11 10 SIU Interrupt Pending Register SIPEND Table 11 9 SIPEND Field Descriptions Bits Name Description 0 2 4 6 8 10 12 14 IRQn Interrupt request 0Ð7 Indicate whether an edge triggered interrupt is pending 0 The appropriate interrupt is not pending 1 The appropriate interrupt is pending 1 3 5 7 9 11 13 15 LVLn Level 0Ð7 When set these bits indicate a pending level interrupt of corre...

Page 292: ...st 0 Enables disables updating SIVEC INTC IRQ0 generates an NMI regardless of this bit 1 3 5 7 9 11 13 15 LVMn Level mask 0Ð7 When set these bits enable an internal interrupt request to be generated 0 Disable generation of an interrupt request bit in SIPEND 1 Enable generation of an interrupt request bit in SIPEND 2 4 6 8 10 12 14 IRMn Interrupt request mask 1Ð7 When set these bits enable an IRQ i...

Page 293: ...tion 0 2 4 6 8 10 12 14 EDn Edge detect 0Ð7 0 A low logical level in the IRQ signal indicates an interrupt request 1 A falling edge in the corresponding IRQ signal indicates interrupt request 1 3 5 7 9 11 13 15 WMn Wake up mask 0Ð7 0 Not allowed to exit from low power mode 1 Low level detection in IRQn allows the MPC860 to exit or wake up from low power mode 16Ð31 Ñ Reserved should be cleared Bit ...

Page 294: ...rogrammed to interrupt at level 7 11 6 The Bus Monitor Control of the bus monitor is provided in the SYPCR The bus monitor ensures that each bus cycle initiated by the MPC860terminates within a reasonable time The MPC860Õs bus monitor does not monitor accesses initiated by external masters At the start of the transfer start signal TS the monitor begins counting and stops when transfer acknowledge ...

Page 295: ...nd issues a reset or an NMI which is programmed by SYPCR SWRI Once SYPCR is written by the software SYPCR SWE cannot be changed See Section 11 4 3 ÒSystem Protection Control Register SYPCR Ó To service the software watchdog timer follow these steps 1 Write 0x556C to the software service register SWSR 2 Write 0xAA39 to the SWSR This sequence clears the watchdog timer and the timing process repeats ...

Page 296: ...ng sequence is written to SWSR If the SWE bit is loaded with a zero the modulus counter will not count Figure 11 16 Software Watchdog Timer Block Diagram 11 7 1 Software Service Register SWSR The software service register SWSR is the location that the software watchdog timer servicing sequence writes to To prevent a SWT timeout a write of 0x556C followed by 0xAA39 should be written to this registe...

Page 297: ...upt request A decrementer interrupt is also sent to the power down wake up logic so the core can waken from power down mode A decrementer exception causes a pending interrupt request in the core which is cleared automatically when the decrementer interrupt is taken Table 11 14 shows some decrementer periods available assuming a 4 MHz oscillator 11 8 1 Decrementer Register DEC The decrementer regis...

Page 298: ...t 11 9 1 Timebase Register TBU and TBL The timebase register TB holds a 64 bit integer that is incremented periodically It is implemented in two parts time base upper and time base lower TBU and TBL There is no automatic initialization of TB therefore system software must perform this initialization The contents of TB can be written by mtspr and read by mftb or mftbu instruction Figure 11 19 shows...

Page 299: ...ld Descriptions Bits Name Description 0Ð31 TBU Timebase upper The value in this Þeld is used as an upper part of the timebase counter Bit 0 1 2 3 4 5 6 7 8 9 É 30 31 Field TBL Reset Ñ R W R W SPR 268 Read 284 Write Figure 11 20 Timebase Lower Register TBL Table 11 17 TBL Field Descriptions Bits Name Description 0Ð31 TBL Timebase lower The value in this Þeld is used as the lower part of the timebas...

Page 300: ...ddr IMMR 0xFFFF0000 0x200 Figure 11 22 Timebase Status and Control Register TBSCR Table 11 19 TBSCR Field Descriptions Bits Name Description 0Ð7 TBIRQ Timebase interrupt request Determines interrupt priority level of the timebase To specify a certain level the appropriate bit should be set 8 REFA Reference interrupt status If set REFA indicates that a match was detected between the corresponding r...

Page 301: ...described in Section 11 4 5 ÒRegister Lock Mechanism Ó To unlock a register write the key word 0x55CC_AA33 to the key registers Note that the real time clock will count in seconds only if PITRTCLK is supplied by a 32 768 kHz or 38 4 kHz source Figure 11 23 Real Time Clock Block Diagram 11 10 1 Real Time Clock Status and Control Register RTCSC The real time clock status and control register RTCSC i...

Page 302: ...source select Software must set 38K for the proper timing of a second 0 Assumes that PITRTCLK is driven by a 32 768 KHz crystal 1 Assumes that PITRTCLK is driven by a 38 4 KHz crystal 12 SIE Seconds interrupt enable If set the real time clock generates an interrupt when SEC is set 13 ALE Alarm interrupt enable If set the real time clock generates an interrupt when ALR is set 14 RTF Real time clock...

Page 303: ...can be written Under normal conditions RTCSC 38K 0 PITRTCLK is assumed to be 8192 Hz 4 192 MHz 512 or 32 768 KHz 4 RTSEC resets at 8192 and increments RTC Thus RTC contains the time in seconds and RTSEC functions as a divider For a 38 4 KHz crystal instead of 32 768 KHz RTCSC 38K should be set to make RTSEC reset at 9600 instead of 8192 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field ALARM Reset Ñ...

Page 304: ...S bit is set an interrupt is generated at the interrupt controller that remains pending until PS is cleared If PS is set again before being cleared the interrupt remains pending until PS is cleared Any write to PITC stops the current countdown and the count resumes with a new value in the PITC If the PTE bit is not set the PIT is unable to count and retains the old count value Reading the PIT does...

Page 305: ... control register PISCR contains the interrupt request level and status bits It also controls the 16 bits to be loaded in a modulus counter Note that PISCR is a keyed register It must be unlocked in PISCRK before it can be written Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field PIRQ PS Ñ PIE PITF PTE Reset 0000_0000_0000_0000 R W R W Addr IMMR 0xFFFF0000 0x240 Figure 11 29 Periodic Interrupt Statu...

Page 306: ...ro has no effect 0 The PIT is unaffected 1 The PIT has issued an interrupt 9Ð12 Ñ Reserved should be cleared 13 PIE Periodic interrupt enable 0 Disables the PS bit 1 Enables the PS bit to generate an interrupt 14 PITF PIT freeze enable 0 The PIT is unaffected by the FRZ signal 1 The FRZ signal stops the PIT 15 PTE Periodic timer enable 0 The PIT is disabled 1 The PIT is enabled Bit 0 1 2 3 4 5 6 7...

Page 307: ...ebase counter and decrementer can be disabled This is controlled by the associated bits in the control register of each timer If they are programmed to stop counting when FRZ is asserted the counters maintain their values until FRZ is negated The bus monitor however will be enabled regardless of this signalÕs state 16Ð31 Ñ Reserved should be cleared Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field ...

Page 308: ... the software watchdog timer is frozen It remains frozen and maintains its count value until the core exits this mode and continues to execute instructions The PIT decrementer and timebase are not inßuenced by these low power modes and they continue to run at their respective frequencies These timers can generate an interrupt to bring the MPC860 out of the low power modes ...

Page 309: ...n by the source Ñ indicates that the logic circuitry is not affected 12 1 Types of Reset The MPC860 has several sources of input to the reset logic Power on reset External hard reset Internal hard reset Ñ Loss of lock Ñ Software watchdog reset Ñ Checkstop reset Ñ Debug port hard reset JTAG reset Table 12 1 MPC860 Reset Responses Reset Source Reset Effect Reset Logic and PLL States Reset System Con...

Page 310: ...ck is active The PORESET signal is negated After the negation of PORESET or PLL lock the core enters the state of internal initiated HRESET and continues driving the HRESET and SRESET signals for 512 clock cycles After 512 cycles elapse the 860Õs conÞguration is sampled from the data signals and the core stops internally asserting the HRESET and SRESET signals To ensure prompt negation external pu...

Page 311: ...ock event occurs an internal hard reset sequence is generated 12 1 3 2 Software Watchdog Reset When SRS SWRS 1 and the core watchdog counter decrements to zero a software watchdog reset is asserted generating an internal hard reset sequence 12 1 3 3 Checkstop Reset If the core enters a checkstop state and PLPRCR CSR 1 the checkstop reset is asserted generating an internal hard reset sequence 12 1 ...

Page 312: ...SET only if it occurs while the MPC860 is not internally asserting HRESET or SRESET 12 1 8 Internal Soft Reset The JTAG and debug ports can initiate an internal soft reset resulting in the assertion of the SRESET signal After 512 cycles the core negates the SRESET signal and the debug port conÞguration is sampled from the DSDI and DSCK signals Once the core negates SRESET 16 clock cycles must elap...

Page 313: ...ing 1 writing 0 has no effect Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS JTRS Ñ Reset 0000_0000_0000_0000 R W R W Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Ñ reset 0000_0000_0000_0000 r w R W Figure 12 3 Reset Status Register RSR Test for HRESET or SRESET Internal or External SRESET Asserted DSDI is sampled to determine clocked or self cloc...

Page 314: ...s detected LLRS is set and remains set until software clears it 0 No enabled loss of lock reset event occurred 1 An enabled loss of lock reset event occurred 3 SWRS Software watchdog reset status Cleared by a power on reset When a software watchdog expire event occurs SWRS is set and remains set until software clears it 0 No software watchdog reset event occurred 1 A software watchdog reset event ...

Page 315: ...nput signal is being asserted the core assumes the default reset conÞguration 0x0000 0000 This changes when PORESET is negated or the CLKOUT signal begins oscillation and the desired hardware conÞguration is sampled from the data bus every nine clock cycles on the rising edge of CLKOUT The setup time required for the data bus is 15 cycles and the maximum rise time of HRESET should be less than six...

Page 316: ...t PORESET Assertion Figure 12 6 shows a reset operation with a long PORESET signal assertion Figure 12 6 Reset Configuration Sampling for Long PORESET Assertion CLKOUT PORESET INTPORESET HRESET D 0 31 TSUP Default RSTCONF RSTCONF Controlled CLKOUT PORESET INTPORESET HRESET D 0 31 TSUP Default RSTCONF RSTCONF Controlled ...

Page 317: ... resistor on the data bus Figure 12 8 Hard Reset Configuration Word Table 12 3 Hard Reset Configuration Word Field Descriptions Bits Name Description 0 EARB External arbitration If this bit is set external arbitration is assumed If it is cleared then internal arbitration is performed See Section 11 4 2 ÒSIU Module ConÞguration Register SIUMCR Ó 1 IIP Initial interrupt preÞx DeÞnes the initial valu...

Page 318: ...functions as OP2 ALE_B DSCK AT1 functions as ALE_B IP_B2 AT2 functions as IP_B2 IP_B6 DSDI AT0 functions as IP_B6 IP_B7 PTR AT3 functions as IP_B7 OP3 MODCK2 DSDO functions as OP3 01 IP_B 0Ð1 IWP 0Ð1 VFLS 0Ð1 functions as WP 0Ð1 IP_B3 IWP2 VF2 functions as IWP2 IP_B4 LWP0 VF0 functions as LWP0 IP_B5 LWP1 VF1 functions as LWP1 OP2 MODCK1 STS functions as STS ALE_B DSCK AT1 functions as AT1 IP_B2 AT...

Page 319: ...DI DSDI functions as TDI TDO DSDO functions as TDO 10 Reserved 11 ALE_B DSCK AT1 functions as DSCK IP_B6 DSDI AT0 functions as DSDI OP3 MODCK2 DSDO functions as DSDO IP_B7 PTR AT3 functions as PTR TCK DSCK functions as TCK TDI DSDI functions as TDI TDO DSDO functions as TDO 13Ð1 4 EBDF External bus division factor DeÞnes the frequency division factor between GCLK1 GCLK2 and GCLK1_50 GCLK2_50 CLKOU...

Page 320: ...12 12 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...

Page 321: ...scribed in the previous chapter including numerous examples and timing diagrams Chapter 15 ÒClocks and Power Control Ó describes on chip and external devices including the phase locked loop circuitry and frequency dividers that generate programmable clock timing for baud rate generators timers and a variety of low power mode options Chapter 16 ÒMemory Controller Ó describes the memory controller w...

Page 322: ...source to identify the bus interface presented by the 60x family of PowerPC microprocessors Application notesÑThese short documents contain useful information about speciÞc design issues useful to programmers and engineers working with PowerPC processors For a current list of PowerPC documentation refer to the world wide web at http www mot com powerpc Conventions This document uses the following ...

Page 323: ... unit ID CAM Content addressable memory CPM Communication processor module CRC Cyclic redundancy check DMA Direct memory access DPLL Digital phase locked loop DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception EA Effective address EEST Enhanced Ethernet serial transceiver GCI General circuit interface GPCM General purpose chip select machine HDLC Hi...

Page 324: ...SCC Serial communication controller SCP Serial control port SDLC Synchronous data link control SDMA Serial DMA SI Serial interface SIU System interface unit SMC Serial management controller SNA Systems network architecture SPI Serial peripheral interface SPR Special purpose register SRAM Static random access memory TDM Time division multiplexed TLB Translation lookaside buffer TSA Time slot assign...

Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...

Page 326: ...IV vi MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...

Page 327: ...alSignals 13 1 Chapter 13 External Signals 130 130 This chapter contains descriptions of the MPC860 input and output signals showing multiplexing pin assignments and reset values Figure 13 1 shows the signals grouped by function ...

Page 328: ...CA PC4 L1TSYNCA PD15 L1RSYNCA PD14 L1TSYNCB PD13 L1RSYNCB PD12 RxD3 PD11 TxD3 PD10 RxD4 PD9 TxD4 PD8 RTS3 PD7 RTS4 PD6 REJECT2 PD5 REJECT3 PD4 REJECT4 PD3 TMS DSDI TDI DSCK TCK TRST DSDO TDO AS MPC860 32 1 1 1 1 1 1 1 1 1 1 1 1 32 4 1 1 1 1 2 1 6 1 1 1 1 1 1 4 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 5 1 1 2 1 1 1 1 1 2 1 1 1 1 1 129 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 329: ...GO3 PB15 RSTRT1 PB14 L1ST1 RTS1 DREQ0 PC15 L1ST2V RTS2 DREQ1 PC14 L1ST3 L1RQb PC13 L1ST4 L1RQa PC12 CTS1 PC11 CTS2 PC9 TGATE2 CD2 PC8 CTS3 SDACK2 L1TSYNCB PC7 CD3 L1RSYNCB PC6 CTS4 SDACK1 L1TSYNCA PC5 CD4 L1RSYNCA PC4 L1TSYNCA PD15 L1RSYNCA PD14 L1TSYNCB PD13 L1RSYNCB PD12 RxD3 PD11 TxD3 PD10 RxD4 PD9 TxD4 PD8 RTS3 PD7 RTS4 PD6 REJECT2 PD5 REJECT3 PD4 REJECT4 PD3 TMS DSDI TDI DSCK TCK TRST DSDO TD...

Page 330: ...4Ð1 1 1 A 0Ð31 TSIZ0 REG TSIZ1 R W BURST BDIP GPL_B5 TS TA TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D 0Ð31 DP 0Ð3 IRQ 3Ð6 BR BG BB FRZ IRQ6 IRQ 0Ð1 IRQ7 CS 0Ð5 CS6 CE1_B CS7 CE2_B WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A 0Ð3 GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A 2Ð3 GPL_B 2Ð3 CS 2Ð3 UPWAITA GPL_A4 UPWAITB GPL_B4 GPL_A5 PORESET RSTCONF HRESET SRESET XTAL EXTAL XFC CLKOUT...

Page 331: ...t when an external master starts a bus transaction RD WR Hi Z B2 Bidirectional Three state Read WriteÑDriven by a bus master to indicate the direction of the data transfer A logic one indicates a read from a slave device and a logic zero indicates a write to a slave device The MPC860 drives this signal when it is bus master Input when an external master initiates a transaction on the bus BURST Hi ...

Page 332: ... external pull up resistor RSV IRQ2 See Section 13 5 H3 Bidirectional Three state ReservationÑThe MPC860 outputs this three state signal in conjunction with the address bus to indicate that the core initiated a transfer as a result of a stwcx or lwarx Interrupt Request 2ÑOne of eight external inputs that can request by means of the internal interrupt controller a service routine from the core KR R...

Page 333: ...xternal masters Interrupt Request 4ÑOne of eight external inputs that can request by means of the internal interrupt controller a service routine from the core Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line if deÞned as IRQ4 and KR IRQ4 SPKROUT if deÞned as IRQ4 DP2 IRQ5 Hi Z W4 Bidirectional Three state Data Parity 2ÑProvides parity generat...

Page 334: ... the logical AND of FRZ IRQ6 if deÞned as IRQ6 and DP3 IRQ6 if deÞned as IRQ6 IRQ0 Hi Z V14 Input Interrupt Request 0ÑOne of eight external inputs that can request by means of the internal interrupt controller a service routine from the core IRQ1 Hi Z U14 Input Interrupt Request 1ÑOne of eight external inputs that can request by means of the internal interrupt controller a service routine from the...

Page 335: ... WE2 BS_B2 PCOE High B6 Output Write Enable 2ÑOutput asserted when the MPC860 starts a write access to an external slave controlled by the GPCM WE2 is asserted if D 16Ð23 contains valid data to be stored by the slave device Byte Select 2 on UPMBÑOutput asserted under control of the UPMB as programmed by the user In a read or write transfer BS_B2 is asserted only D 16Ð23 contains valid data PCMCIA ...

Page 336: ...drive capability for CS2 and CS3 is independently deÞned for each signal in the SIUMCR UPWAITA GPL_A4 Hi Z C1 Bidirectional User Programmable Machine Wait AÑThis input is sampled as deÞned by the user when an access to an external slave is controlled by the UPMA General Purpose Line 4 on UPMAÑThis output reßects the value speciÞed in the UPMA when an external transfer to a slave is controlled by U...

Page 337: ...gh B3 Output Card Enable 1 Slot AÑThis output enables even byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface CE2_A High A3 Output Card Enable 2 Slot AÑThis output enables odd byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface WAIT_A Hi Z R3 Input Wait Slot AÑThis input if asserted low causes a delay ...

Page 338: ...f the PCMCIA interface I O Device B is 16 Bits Port SizeÑThe MPC860 monitors this input when a PCMCIA interface transaction is initiated to an I O region in socket B in the PCMCIA space Address Type 2ÑThe MPC860 drives this bidirectional three state signal when it initiates a transaction on the external bus If the core initiates the transaction it indicates if the transfer is instruction or data T...

Page 339: ...changes are reported in the PIPR and PSCR of the PCMCIA interface Program TraceÑTo allow program ßow tracking the MPC860 asserts this output to indicate an instruction fetch is taking place Address Type 3ÑThe MPC860 drives the bidirectional three state signal when it starts a transaction on the external bus When the core initiates a transfer AT3 indicates whether it is a reservation for a data tra...

Page 340: ...n The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer AS Hi Z L3 Input Address StrobeÑInput driven by an external asynchronous master to indicate a valid address on A 0Ð31 The MPC860 memory controller synchronizes AS and controls the memory device addressed under its control PA...

Page 341: ... the general purpose I O port A CLK2ÑOne of eight clock inputs that can be used to clock SCCs and SMCs TOUT1ÑTimer 1 output BRGCLK1ÑOne of two external clock inputs of the BRGs PA 5 CLK3 TIN2 L1TCLKA BRGO2 Hi Z N18 Bidirectional General Purpose I O Port A Bit 5ÑBit 5 of the general purpose I O port A CLK3ÑOne of eight clock inputs that can be used to clock SCCs and SMCs TIN2ÑTimer 2 external clock...

Page 342: ...ional Optional Open drain General Purpose I O Port B Bit 29ÑBit 29 of the general purpose I O port B SPIMOSIÑSPI output data when it is conÞgured as a master or SPI input data when it is conÞgured as a slave PB 28 SPIMISO BRGO4 Hi Z D19 Bidirectional Optional Open drain General Purpose I O Port B Bit 28ÑBit 29 of the general purpose I O port B SPIMISOÑSPI input data when the MPC860 is a master SPI...

Page 343: ... the general purpose I O port B RTS1ÑRequest to send modem line for SCC1 L1ST1ÑOne of four output strobes that can be generated by the serial interface PB 18 RTS2 L1ST2 Hi Z N17 Bidirectional Optional Open drain General Purpose I O Port B Bit 18ÑBit 18 of the general purpose I O port B RTS2ÑRequest to send modem line for SCC2 L1ST2ÑOne of four output strobes that can be generated by the serial int...

Page 344: ...serial interface RTS44ÑRequest to send modem line for SCC4 PC 11 CTS1 Hi Z J19 Bidirectional General Purpose I O Port C Bit 11ÑBit 11 of the general purpose I O port C CTS1ÑClear to send modem line for SCC1 PC 10 CD1 TGATE1 Hi Z K19 Bidirectional General Purpose I O Port C Bit 10ÑBit 10 of the general purpose I O port C CD1ÑCarrier detect modem line for SCC1 TGATE1ÑTimer 1 timer 2 gate signal PC 9...

Page 345: ...port D L1TSYNCBÑInput transmit data sync signal to the TDM channel B PD 12 L1RSYNCB Hi Z R16 Bidirectional General Purpose I O Port D Bit 12ÑBit 12 of the general purpose I O port D L1RSYNCBÑInput receive data sync signal to the TDM channel B PD 11 RXD3 Hi Z T16 Bidirectional General Purpose I O Port D Bit 11ÑBit 11 of the general purpose I O port D RXD3ÑReceive data for serial channel 3 PD 10 TXD...

Page 346: ...his input to SCC4 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match TCK DSCK Hi Z5 H16 Input Provides clock to scan chain logic or for the development port logic TMS Pulled up G18 Input Controls the scan chain test mode operations TDI DSDI Pulled up 6 H17 Input Input serial data for either the scan chain logic or the development port and determin...

Page 347: ...igh because if the voltage ever dips below the logic high threshold while the buffer is enabled as an output the buffer will reactivate Further external logic must not attempt to drive these signals low while active pull up buffers are enabled as outputs because the buffers will reactivate and drive high resulting in a buffer Þght and possible damage to the MPC860 to the system or to both Figure 1...

Page 348: ...other pins have internal pull ups or pull downs Resistance values for internal pull up and pull down resistors are not speciÞed because their values may vary due to process variations and shrinks in die size and they are not tested Typical values are on the order of 5 KW but can vary by approximately a factor of 2 13 4 Recommended Basic Pin Connections The following sections provided recommended p...

Page 349: ...ld be set with three state drivers that turn off after PORESET is negated however if MODCK 1Ð2 pinsÕ alternate output functions are not used in the system they can be conÞgured with pull up and pull down resistors 13 4 1 1 Bus Control Signals and Interrupts Signals with open drain buffers and active pull up buffers HRESET SRESET TEA TS TA BI and BB must have external pull up resistors Some other i...

Page 350: ...pull up resistors should be used on any unused inputs to keep them from oscillating For example if PCMCIA is not used the PCMCIA input pins WAIT_A WAIT_B IP_A 0Ð8 IP_B 0Ð8 should have external pull up resistors However unused pins of portA B C or D can be conÞgured as outputs and if they are conÞgured as outputs they do not require external terminations 13 4 4 Unused Outputs Unused outputs can be ...

Page 351: ...high impedance KR RETRY IRQ4 SPKROUT KR RETRY IRQ4 high impedance SPKROUT low FRZ IRQ6 FRZ low IRQ6 high impedance ALE_B DSCK AT1 ALE_B low DSCK AT1 high impedance IP_B 0Ð1 IWP 0Ð1 VFLS 0Ð1 IP_B 0Ð1 high impedance IWP 0Ð1 high VFLS 0Ð1 low IP_B3 IWP2 VF2 IP_B3 high impedance IWP2 high VF2 low IP_B4 LWP0 VF0 IP_B4 high impedance LWP0 high VF0 low IP_B5 LWP1 VF1 IP_B5 high impedance LWP1 high VF1 lo...

Page 352: ...13 26 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...

Page 353: ... bit address bus with transfer size indication 32 bit data bus Dynamic bus sizing to 32 16 or 8 bit ports accessed through the memory controller TTL compatible interface Bus arbitration supported optionally by internal or external logic Bus arbitration logic on chip supports an external master with programmable priority Compatible with PowerPC architecture Easy to interface to slave devices Bus is...

Page 354: ...wn in Figure 14 1 around the rising clock edge To ensure that an input signal is recognized on a speciÞc rising clock edge that input must be stable during the sample window If an input changes during the window the level recognized by the MPC860 is unpredictable however the MPC860 always resolves the latched level to either a logical high or low before using it For deterministic operation all inp...

Page 355: ...en an external device initiates a transaction and the memory controller was conÞgured to handle external master accesses RD WR Read Write 1 High O Driven by the MPC860 along with the address when it owns the external bus Driven high indicates that a read access is in progress Driven low indicates that a write access is in progress I Sampled by the MPC860 when an external device initiates a transac...

Page 356: ...saction BDIP Burst Data in Progress 1 Low O Driven by the MPC860 when it owns the external bus as part of the burst protocol Asserted indicates that the second beat in front of the current one is requested by the master Negated before the burst transfer ends to abort the burst data phase Transfer Start TS Transfer Start 1 Low O Driven by the MPC860 when it owns the external bus Indicates the start...

Page 357: ... by the slave in a read transaction Each parity line is sampled by the MPC860 and checked if enabled against the expected value parity value even or odd of its corresponding data bus byte For single beat transfers byte lanes not selected by A 30Ð31 and TSIZ 0Ð1 are not sampled by the MPC860 and its parity lines will not be checked Transfer Cycle Termination TA Transfer Acknowledge 1 Low I Driven b...

Page 358: ...s transaction Figure 14 3 shows a simpliÞcation of the basic transfer protocol Arbitration BR Bus Request 1 Low I Asserting BR when the internal arbiter is enabled indicates that an external master is requesting the bus O The MPC860 drives BR when the internal arbiter is disabled BG Bus Grant 1 Low O When the internal arbiter is enabled the MPC860 asserts BG to indicate that an external master may...

Page 359: ...the address transfer phase The master must consider the one dead clock cycle switching between drivers to avoid electrical contention The master can stop driving the data bus as soon as it samples TA asserted on the rising edge of CLKOUT On a read cycle the master accepts the data bus contents as valid at the rising edge of CLKOUT in which TA is sampled asserted 14 4 2 1 Single Beat Read Flow The ...

Page 360: ...MOTOROLA Part IV Hardware Interface Figure 14 5 Single Beat Read CycleÐBasic TimingÐZero Wait States CLKOUT BR BG BB A 0Ð31 R W TSIZ 0Ð1 AT 0Ð3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is Valid ...

Page 361: ...ite Flow The basic write cycle begins with a bus arbitration followed by the address transfer then the data transfer The following ßow and timing diagrams show the handshakes as applicable to the Þxed transaction protocol CLKOUT BR BG BB A 0Ð31 R W TSIZ 0Ð1 AT 0Ð3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is Valid Wait State ...

Page 362: ... 14 7 Basic Flow of a Single Beat Write Cycle MASTER Bus Request BR Receives Bus Grant BG from arbiter Asserts Bus Busy BB if no other master is driving Asserts Transfer Start TS Drives address and attributes Asserts Transfer Acknowledge TA Interrupts data driving SLAVE Drives data ...

Page 363: ...erface 14 11 Part IV Hardware Interface Figure 14 8 Basic Timing Single Beat Write Cycle Zero Wait States CLKOUT BR BG BB A 0Ð31 R W TSIZ 0Ð1 AT 0Ð3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is sampled ...

Page 364: ... that external memory has a 32 bit port size The MPC860 provides an effective mechanism for interfacing with 16 and 8 bit port size memories by allowing transfers to these devices when they are controlled by the internal memory controller CLKOUT BR BG BB A 0Ð31 R W TSIZ 0Ð1 AT 0Ð3 BURST TS Data TA Assert BB drive address and assert TS Receive BG and BB negated Data is Sampled Wait State ...

Page 365: ...nally increment A28 and A29 and A30 in the case of a 16 bit port size slave device of the supplied address for each transfer causing the address to wrap around at the end of the four word block For slaves controlled by the memory controller the MPC860 increments the address on A 28Ð31 and or BADDR 28Ð30 Address and transfer attributes supplied by the bus master remain stable during the transfers t...

Page 366: ...ther the slave supports bursts Along with asserting TS the master drives the address address attributes and BURST signals to indicate that a burst transfer is being initiated Slaves that support bursting negate BI If the slave cannot burst it asserts the BI During the data phase of a burst write cycle the master drives the data It also asserts BDIP if it intends to drive the data beat after the cu...

Page 367: ...V Hardware Interface MPC860 bus supports critical data Þrst access for Þxed size burst The order of wraparound wraps back to the data 0 For example Case burst of four data 0 data 1 data 2 data 3 data 0 Case burst of eight data 0 data 1 data 2 data 6 data 7 data 0 ...

Page 368: ...tes Asserts Transfer Acknowledge TA Receives data SLAVE Asserts Burst Data in Progress BDIP Drives BURST asserted Receives address Returns data Asserts Transfer Acknowledge TA Returns data BDIP asserted Receives data asserts Transfer Acknowledge TA Returns data BDIP asserted Receives Data asserts Transfer Acknowledge TA Returns data BDIP asserted Negates Burst Data in Progress BDIP Yes Receives da...

Page 369: ... 17 Part IV Hardware Interface Figure 14 12 Burst Read Cycle 32 Bit Port Size Zero Wait State Expects Another Data Last Beat CLKOUT BR BG BB A 0Ð31 AT 0Ð3 R W TSIZ 0Ð1 BURST TS Data TA Data is BDIP PS 00 Valid Data is Valid Data is Valid Data is Valid 00 ...

Page 370: ...V Hardware Interface Figure 14 13 Burst Read CycleÐ32 Bit Port SizeÐOne Wait State Expects Another Data Last Beat CLKOUT BR BG BB A 0Ð31 AT 0Ð3 R W TSIZ 0Ð1 BURST TS Data TA Data is BDIP PS 00 Valid Data is Valid Data is Valid Data is Valid 00 Wait State ...

Page 371: ... Hardware Interface Figure 14 14 Burst Read CycleÐ32 Bit Port SizeÐWait States between Beats Expects Another Data Last Beat CLKOUT BR BG BB A 0Ð31 AT 0Ð3 R W TSIZ 0Ð1 BURST TS Data TA Data is BDIP PS 00 Valid Data is Valid Data is Valid Data is Valid 00 Wait State ...

Page 372: ...0 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface Figure 14 15 Burst Read Cycle One Wait State between Beats 16 Bit Port Size CLKOUT BR BG BB A 0Ð31 AT 0Ð3 R W TSIZ 0Ð1 BURST TS Data TA PS BDIP 00 10 ...

Page 373: ...ss and attributes Asserts Transfer Acknowledge TA Drives data SLAVE Asserts burst data in progress BDIP Drives BURST asserted Receives address Negates Burst Data in Progress BDIP Stops driving data DonÕt sample next data DonÕt sample next data Yes No Drives data BDIP asserted Asserts Transfer Acknowledge TA Drives data DonÕt sample next data Yes No BDIP asserted Asserts Transfer Acknowledge TA Dri...

Page 374: ... IV Hardware Interface Figure 14 17 Burst Write CycleÐ32 Bit Port SizeÐZero Wait States Will drive another data Last beat CLKOUT BR BG BB A 0Ð31 AT 0Ð3 R W TSIZ 0Ð1 BURST TS Data TA Data is BDIP sampled Data is sampled Data is sampled Data is sampled 00 ...

Page 375: ...lignment Byte access can have any address alignment Half word access must have A 31 0b0 Word access must have A 30Ð31 0b00 For burst accesses A 30Ð31 0b00 Misaligned accesses performed by the CPU are broken into multiple bus accesses with natural alignment Misaligned accesses performed by external masters are not supported CLKOUT BR BG BB A 0Ð27 A 28Ð29 A 30Ð31 R W TSIZ 0Ð1 TS BDIP Data BURST TA B...

Page 376: ...2 bits wide when beginning the cycle Figure 14 19 Figure 14 20 Table 14 2 and Table 14 3 use the following conventions OP0 is the MSB of a word operand OP3 is the LSB The two bytes of a half word operand are OP0 most signiÞcant and OP1 or OP2 most signiÞcant and OP3 depending on the address of the access The single byte of a byte length operand is OP0 OP1 OP2 or OP3 depending on the address of the...

Page 377: ...he arbitration conÞguration external or internal is set at system reset See Section 16 8 ÒExternal Master Support Ó Each bus master must have bus request BR bus grant BG and bus busy BB signals A device needing the bus asserts BR and then waits for the arbiter to assert BG The new Table 14 2 Data Bus Requirements For Read Cycles Transfer Size TSIZ 0Ð1 Address 32 Bit Port 16 Bit Port 8 Bit Port A30...

Page 378: ...master asserts BR to request bus mastership BR should be negated as soon as the bus is granted the bus is not busy and the new master can drive the bus If requests are pending the master can assert BR as long as needed When conÞgured for external arbitration the MPC860 drives BR when it requires bus mastership When the internal on chip arbiter is used BR is an input to the internal arbiter and sho...

Page 379: ...r until BB is deasserted The bus master should not relinquish or negate BB until it completes its transfer To avoid contention on BB masters should three state BB when it gets a logical 1 value This situation implies an external pull up resistor is needed to ensure that a master that acquires the bus can recognize the negation of BB regardless of how many cycles have passed since the previous mast...

Page 380: ...ation of external devices relative to the internal MPC860 bus masters If the external device requests the bus and the MPC860 does not require it or the external device has higher priority than the current internal bus master the MPC860 grants the bus to the external device Figure 14 24 shows the internal Þnite state machine that implements the arbiter protocol CLKOUT BR0 BG0 BR1 BG1 BB ADDR ATTR T...

Page 381: ...s granted mastership TS is asserted only for the Þrst cycle of the transaction and is negated in the successive clock cycles until the end of the transaction To avoid contention the master should three state this signal when it relinquishes the bus This situation indicates that an external pull up resistor should be connected to TS to avoid having a slave recognize this signal as asserted when no ...

Page 382: ...e or vice versa It may remain low for consecutive write cycles 14 4 7 3 2 Burst Indicator BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer 14 4 7 3 3 Transfer Size TSIZ 0Ð1 indicates the size of the requested data transfer The TSIZ signals may be used with BURST and A 30Ð31 to determine which data byte lane...

Page 383: ... Table 14 5 Address Types Definition STS TS CPU CPM AT0 User Supervisor AT1 Instruction Data AT2 Reservation Program Trace AT3 Program Trace PTR Reservation RSV Address Space DeÞnitions 1 x x x x x 1 1 No transfer or not the first transaction of a transfer 0 x x x x x x x Start of a transaction x 0 0 0 0 0 0 1 Core initiated normal instruction program trace supervisor mode 1 1 1 Core initiated nor...

Page 384: ...an also be monitored on two separate signals PTR and RSV if desired PTR is low when the following is true Ñ AT0 0 CPU access Ñ AT2 0 Instruction Ñ AT3 0 Program Trace x 1 0 0 0 0 0 1 Core initiated show cycle address instruction program trace supervisor mode 1 1 1 Core initiated show cycle address instruction supervisor mode 1 0 1 0 Core initiated reservation show cycle data supervisor mode 1 1 1 ...

Page 385: ...d increment the address for the slave to complete the burst transfer 14 4 8 3 Transfer Error Acknowledge TEA Terminates the bus cycle under a bus error condition for which the current cycle is aborted TEA overrides any other cycle termination signals such as TA 14 4 8 4 Termination Signals Protocol The transfer protocol was deÞned to avoid electrical contention on lines that can be driven by vario...

Page 386: ... by the local reservation logic The protocol tries to optimize reservation cancellation such that a PowerPC processor is notiÞed of memory reservation loss on a remote bus only when it has issued a STWCX cycle to that address Slave 1 Slave 2 External Bus Acknowledge Signals MPC860 clkout a 0Ð31 r w tsiz 0Ð1 ts data ta bi tea Slave 1 negates acknowledge signals and Slave 2 allowed to drive acknowle...

Page 387: ...on ßag If memory reservation is lost it is guaranteed that stwcx will not modify the memory 14 4 9 1 Cancel Reservation CR CR is a point to point signal To use it reservation logic must remember speciÞcally which bus master requested reservation for which address If another master writes to the reserved address the reservation logic asserts CR only to the master that holds the associated reservati...

Page 388: ...use it the reservation logic must only remember that one of the bus masters has a reservation for a particular address If another bus master writes to the address with an instruction other than stwcx the reservation logic remembers that the reservation for that address was lost When the master with the reservation subsequently attempts an stwcx instruction to that address the reservation logic res...

Page 389: ...ess or abort it if the remote bus supports aborted cycles The failure of stwcx is reported to the core 14 4 10 Bus Exception Control Cycles The MPC860 bus architecture requires assertion of the TA from an external device to signal that the bus cycle is complete TA is not asserted in the following cases The external device does not respond Various other application dependent errors occur External c...

Page 390: ...ycle Figure 14 29 shows that when the internal arbiter is enabled MPC860 negates BB and asserts BG in the clock cycle after RETRY is detected to allow any external master to gain bus ownership Normal arbitration resumes in the next clock cycle If the external master does not use the bus the MPC860 initiates a new transfer with the same address and attributes as before In Figure 14 30 the same situ...

Page 391: ...RETRY assertion as a retry termination if it detects it before the slave device acknowledges the Þrst data beat When RETRY is asserted as a termination signal on the second or third data beat of the access being the Þrst data beat acknowledged by a normal TA assertion it is processed by the MPC860 as a TEA CLKOUT BR Output BG BB A 0Ð31 R W TSIZ 0Ð1 BURST TS Data TA RETRY Allow external master to g...

Page 392: ...ll port size device the transfer size of the access is bigger than the slave port size and the Þrst transfer of this access is terminated normally by the assertion of TA then subsequent single beat transfers initiated by the MPC860 to complete the access process the RETRY assertion as a TEA Table 14 6 summarizes how the MPC860 recognizes the termination signals provided by the slave device that is...

Page 393: ...14 41 Part IV Hardware Interface Table 14 6 Termination Signals Protocol TEA TA RETRY KR Action Asserted X X Transfer error termination Negated Asserted X Normal transfer termination Negated Negated Asserted Retry transfer termination kill reservation ...

Page 394: ...14 42 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...

Page 395: ...low power mode options The MPC860 allows a system to optimize power utilization by providing performance on demand This is implemented through a variety of programmable power saving modes with automatic wake up features Figure 15 1 illustrates internal clock source and distribution that includes the system phase locked loop SPLL clock dividers drivers and crystal oscillator 15 1 Features The main ...

Page 396: ...lk1 gclk2 gclk1C gclk2C vcoout CLKOUT 2 1 mux CLKOUT XFC TMBclk tmbclk VDDSYN Driver Driver CRYSTAL XTAL EXTAL 2 1 MUX RTC PIT Clock and DRIVER Oscillator OSCM 2 1 MUX tbclk 4 or 16 MODCK 1 2 pitrtclk brgclk EXTCLK syncclk gclk2 tbs SCCR rtsel gclk1_50 gclk2_50 Low power Drivers dividers Clock osCclk 4 512 2 1 MUX rtdiv 2 ...

Page 397: ...e to count at a Þxed user deÞned rate regardless of system frequency The clock sources for OSCCLK PITRTCLK and TMBCLK are selected at reset The sources for PITRTCLK and TMBCLK can also be selected in software by manipulation of the SCCR control register For more information see Section 15 2 2 1 ÒSPLL Reset ConÞgurationÓ Section 15 3 2 ÒThe PIT and RTC Clock PITRTCLK Ó and Section 15 3 3 ÒThe Time ...

Page 398: ...o EXTAL and XTAL should be left unconnected If a crystal circuit is used it should be connected between EXTAL and XTAL The crystal circuit is composed of an on chip inverting ampliÞer an external parallel resonant crystal two capacitors and two resistors as shown in Figure 15 3 EXTAL is the ampliÞer input for the crystal circuit XTAL is the ampliÞer output Example values for the passive components...

Page 399: ...ted from either of the external clock sources described in Section 15 2 1 ÒExternal Reference Clocks Ó The main purpose of the SPLL is to generate a stable reference frequency by multiplying the frequency and eliminating the clock skew The SPLL allows the processor to operate at a high internal clock frequency using a low frequency clock input providing two advantages First lower frequency clock i...

Page 400: ... advantages over a crystal circuit in that clock oscillators are easier to work with resulting in faster design debugging and production Furthermore it should be noted that low frequency crystals should not be used for the source of OSCCLK if high frequency SPLL operation is desired This is because the default startup multiplication factor of the SPLL requires a loop Þlter capacitor XFC which is i...

Page 401: ...t parameter in deÞning the SPLL stability There are three factors related to the multiplication factor that deÞne SPLL stability Phase skewÑThe time difference between the falling edges of the EXTAL and CLKOUT pins for a capacitive load on CLKOUT over the entire process temperature ranges and voltage ranges For input frequencies greater than 15 MHz and MF 1 2 this skew is between 0 9 ns and 0 9 ns...

Page 402: ...nce pins for the analog SPLL circuitry For requirements concerning this ground reference refer to Section 15 4 3 ÒClock Synthesizer Power VDDSYN VSSSYN VSSYN1 XFCÑThe external Þlter capacitor pin that connects to the off chip capacitor for the SPLL Þlter One terminal of the capacitor is connected to XFC while the other terminal is connected to the VDDSYN pin Ñ For proper SPLL operation the XFC cap...

Page 403: ...Basic clocks supplied to the core the data and instruction caches and MMUs GCLK1 GCLK2 Basic clocks supplied to the SIU clock module RISC controller and most other features in the CPM GCLK1_50 GCLK2_5 0 Optionally divided versions of GCLK1 GCLK2 which are used to clock the GPCM and UPM in the memory controller and to provide the CLKOUT output for the external bus BRGCLK Clocks the four baud rate g...

Page 404: ...collectively as GCLKx The difference between the GCLKxC and GCLKx signals are as follows The GCLKxC clocks are supplied to the core data and instruction caches and memory management unit They are not active when the MPC860 is in doze sleep or deep sleep modes The GCLKx clocks are supplied to the SIU clock module memory controller and most of the other blocks in the CPM They are not active when the...

Page 405: ...hen the division factor is greater than 1 as shown in Figure 15 7 Figure 15 7 Divided System Clocks GCLKx Timing Diagram 15 3 1 2 Memory Controller and External Bus Clocks GCLK1_50 GCLK2_50 CLKOUT The MPC860 provides the capability to run the external bus and memory controller at a lower frequency than the internal modules This capability is provided by the external bus frequency dividers The exte...

Page 406: ...nd GCLK2_50 is 50 However if SCCR EBDF 1 the duty cycle of GCLK2_50 is 50 but the duty cycle of GCLK1_50 is 37 5 as shown in Figure 15 8 The low power frequency dividers described in Section 15 3 1 1 ÒThe Internal General System Clocks GCLK1C GCLK2C GCLK1 GCLK2 Ó also effect the frequency and duty cycle of GCLK1_50 GCLK2_50 and CLKOUT For an example of this see Figure 15 9 GCLK1 GCLK2 GCLK1_50 GCL...

Page 407: ... and is equivalent to the internal signal GCLK2_50 CLKOUT can drive at full strength half strength or it can be disabled The strength of the drive is controlled in the system clock and reset control register Disabling or decreasing the strength of CLKOUT reduces power consumption noise and electromagnetic interference on the printed circuit board While the SPLL is acquiring lock the CLKOUT signal ...

Page 408: ...uires that SCCR EBDF be written Þrst followed by the write to PLPRCR MF 15 3 1 4 The Baud Rate Generator Clock BRGCLK The baud rate generator clock BRGCLK is used by the four baud rate generators of the communication processor module and by the memory controller refresh counter The baud rate generator clock is controlled independently in order to allow the baud rate generators and memory refresh r...

Page 409: ...ted either from EXTCLK or the crystal oscillator circuit OSCM This input source can be divided by either 4 or 512 The PITRTCLK source and divide factor are selected by SCCR RTSEL and SCCR RTDIV When used by the real time clock RTC the PITRTCLK source is Þrst divided as determined by RTDIV and then divided in the RTC circuits by either 8192 or 9600 Therefore in order for the RTC to count in seconds...

Page 410: ...ESET deassertion the SCCR TBS and the SPLL multiplication factor determine the input clock source and prescaler value for TMBCLK 15 4 Power Distribution The various modules of the MPC860 are connected to four distinct power rails These power rails have different requirements as explained in the following sections The organization of the power rails is shown in Figure 15 12 Table 15 4 PITRTCLK Conf...

Page 411: ...fed by a 3 3V power supply VDDH must in all cases be greater than or equal to VDDL Table 15 6 MPC860 Modules vs Power Rails Block VDDH VDDL VDDSYN KAPWR I O Pad X CLKOUT X Digital SPLL X Clock Control X X Internal Logic X Clock Drivers X Analog SPLL X OSCM X SCCR PLPRCR and RSR X RTC PIT TB and DEC X Clock Control Analog PIT RTC TB DEC SCCR Internal Logic VDDH I O Pad VDDL VDDSYN KAPWR TEXP OSCM P...

Page 412: ...cient isolation is provided for VDDSYN as described above no additional isolation for VSSSYN and VSSSYN1 is required 15 4 4 Keep Alive Power KAPWR The OSCM timebase decrementer periodic interrupt timer real time clock SCCR PLPRCR and RSR are all connected to the keep alive power KAPWR rail This power rail architecture allows the system to remove the power at the VDDH VDDL VDDSYN pins during power ...

Page 413: ...ive VCOOUT 2DFNL 1 Software Ini tiation or Internal or External Interrupt Asynchronous exceptions 3 4 VCOOUT Clocks Synchronous exceptions 3 4 GCLK2 Clocks 20 mW 1 2 DFNL 1 W Doze high LPM 01 Active VCOOUT 2DFNH Internal or External Interrupt 20mW 0 4 2DFNH W Enabled SIU timers CPM and memory controller Disabled core MMU caches Doze low LPM 01 Active VCOOUT 2DFNL 1 Internal or External Interrupt 2...

Page 414: ...e Initiated1 Software Initiated1 Software Initiated1 Software Initiated1 Software Initiated1 IRQx RTC PIT TB DEC Interrupt Wake Up 500 OSCCLK Clocks Wake Up 3 4 GCLKx Clocks 1 Software is active only in normal high low modes Software Initiated1 RTC PIT TB DEC Interrupt HRESET Wake Up 3 4 VCOOUT Clocks TEXPS 1 Software init2 LPM 11 and TEXPS 0 2 Software initiation of power down mode requires that ...

Page 415: ...o Section 15 3 1 1 ÒThe Internal General System Clocks GCLK1C GCLK2C GCLK1 GCLK2 Note also that PLPRCR TMIST should be cleared before entering normal low mode for more information see Section 15 5 8 ÒTMIST Facilitating Nesting of SIU Timer Interrupts Normal low mode can be entered at any time and the frequency of operation of normal low mode can be changed dynamically This is controlled by PLPRCR ...

Page 416: ...15 5 4 Doze Low Mode Doze low mode is similar to Doze high mode except that additionally the system clock frequency has been reduced In doze low mode the GCLKx frequency is determined by SCCR DFNL For more information about SCCR DFNL refer to Section 15 3 1 1 ÒThe Internal General System Clocks GCLK1C GCLK2C GCLK1 GCLK2 Doze low mode is selected if PLPRCR CSRC 1 MSR POW 1 and PLPRCR LPM 01 Note al...

Page 417: ...re enabled Wake up capabilities for IRQx interrupts are enabled in the associated SIEL WMx bits A time out event of the RTC PIT TB or DEC occurs When the MPC860 leaves sleep mode it will enter normal high or normal low mode depending on the state of PLPRCR CSRC and SCCR PRQEN When the MPC860 enters normal high mode PLPRCR LPM is cleared Upon resumption of processing in normal high or low mode the ...

Page 418: ...in stability of the crystal oscillator switchover between the main power supply and KAPWR supply should be done smoothly The maximum power supply rise time seen at the KAPWR pin should be less than 1 7 V ms for a 32 KHz input frequency Power down mode can be used for A software initiated controlled shutdown with optional automatic wakeup Maintaining integrity of the real time clock RTC during a po...

Page 419: ...RCR TEXPS is asserted by the MPC860 when the real time clock or timebase time value matches the value programmed in its associated alarm register or when the periodic interrupt timer or decrementer decrements their value to zero or when the HRESET signal is externally asserted 15 5 7 2 Maintaining the Real Time Clock RTC During Shutdown or Power Failure The power down conÞguration can be used simp...

Page 420: ...onitor circuitÕs reset output is a constantly driven active driver i e not three state 15 5 7 3 Register Lock Mechanism Protecting SIU Registers in Power Down Mode If the MPC860 sets PLPRCR LPM 11 before entering power down mode then the registers of the SIU maintained by KAPWR are automatically protected However to provide protection of the SIU registers maintained by KAPWR against uncontrolled s...

Page 421: ...d POR is power on reset The Þeld is undeÞned ÑThe Þeld is unaffected RTDIV depends on the combination of MODCK1 and MODCK2 RTSEL depends on MODCK1 See Table 15 4 for more information This Þeld is set according to the default of the hard reset conÞguration word Figure 15 15 SCCR Table 15 8 SCCR Field Descriptions Bits Name Description 0 Ñ Reserved should be cleared 1Ð2 COM Clock Output Module This ...

Page 422: ...r or MSR POW is clear normal mode Cleared by power on or hard reset 0 The system remains in low frequency even if there is a pending interrupt from the interrupt controller or MSR POW 0 normal mode 1 The system switches to high frequency when there is a pending interrupt from the Interrupt controller or MSR POW 0 11Ð12 Ñ Reserved should be cleared 13Ð14 EBDF External Bus Division Factor This Þeld ...

Page 423: ... when you change the value of this Þeld This Þeld is cleared by a power on or hard reset 000 Divide by 2 001 Divide by 4 010 Divide by 8 011 Divide by 16 100 Divide by 32 101 Divide by 64 110 Reserved 111 Divide by 256 24Ð26 DFNH Division factor high frequency Sets the VCOOUT frequency division factor for general system clocks to be used in normal mode In normal mode the MPC860 automatically switc...

Page 424: ...anging the MF Þeld causes the SPLL to lose its lock All clocks are disabled until the SPLL reaches lock condition 12Ð15 Ñ Reserved should be cleared 16 SPLSS System PLL Lock Status Sticky Cleared by power on reset Not affected by hard reset An out of lock indication sets the SPLSS bit and it remains set until the software clears it At power on reset the state of the SPLSS bit is zero Write a 1 to ...

Page 425: ...t can clear this Þeld 00 Normal high normal low mode 01 Doze high doze low mode 10 Sleep mode 11 Deep sleep power down mode 24 CSR Checkstop reset enable Enables an automatic reset when the processor enters checkstop mode If the processor enters debug mode at reset then reset is not generated automatically refer to Table 15 10 See Section 37 5 2 2 ÒDebug Enable Register DER Ó 25 LOLRE Loss of lock...

Page 426: ...15 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...

Page 427: ...herals The UPM provides both more features and because it supports bursting higher performance Therefore it is typically used to interface with higher performance run time memory such as DRAM and bursting SRAM The UPM supports address multiplexing of the external bus periodic timers and generation of programmable control signals for row address and column address strobes to allow for a glueless in...

Page 428: ... or external synchronous master requests a single beat or burst read or write access Ñ User speciÞed control signal patterns run when an external asynchronous master requests a single beat read or write access Ñ UPM periodic timer runs a user speciÞed control signal pattern to support refresh Ñ User speciÞed control signal patterns can be initiated by software Ñ Each UPM can be deÞned to support D...

Page 429: ...r MCR Memory Status Register MSTAT Memory Address Register MAR Option Register OR UPM Arbiter Memory Data Register MDR Base Register BR Base Register BR UPMA or UPMB GPCM Wait State Counter Memory Periodic Timer Prescale Register MPTPR Parity Logic DP 0Ð3 DP 0Ð31 CS 0Ð7 BS_x 0Ð3 GPLx 0Ð5 TA DLT3 Internal UPWAITx NA and AMX Fields WE 0Ð3 OE in RAM Word CS 0Ð7 WP RD WR SCY 0Ð3 Expired Load Attribute...

Page 430: ...re 16 2 Memory Controller Machine Selection The GPCM provides a glueless interface to EPROM SRAM ßash EPROM and other peripherals GPCM signals are available on CS 0Ð7 CS0 lets the CPU access the boot EPROM from reset Each chip select allows up to 30 wait states Some features are common to all eight memory banks The block size of each memory bank can vary between 32 Kbytes and 256 Mbytes for a full...

Page 431: ...signals on the DRAM Figure 16 3 Simple System Configuration The UPMs provide a ßexible interface to many types of memory devices Each UPM can control the address multiplexing necessary to access DRAM devices the timing of the BS signals and the timing of the GPL signals Each memory bank can be assigned to either UPM Each UPM is a programmable RAM based machine The UPM toggles the memory controller...

Page 432: ...er information Table 16 1 Memory Controller Register Usage Register Used by the GPCM Used by a UPM Base register bank 0Ð7 register BRx Ö Ö Option register bank 0Ð7 register ORx Ö Ö Memory status register MSTAT Ö Ö Memory command register MCR Ö Machine A mode register MAMR Ö Machine B mode register MBMR Ö Memory data register MDR Ö Memory address register MAR Ö Memory periodic timer prescaler regis...

Page 433: ...be programmed before BRx except when programming the boot chip select CS0 after hardware reset in which case BR0 should be programmed before OR0 16 3 3 Memory Bank Write Protection Attempting to write to an address range marked restricted in BRx WP causes a write protect violation for which MSTAT WPER is set 16 3 4 Address Type Protection BRx AT and ORx ATM can be used to implement address type pr...

Page 434: ...a registers MCR and MDR are used to initialize the UPMÕs RAM array The memory address register MAR speciÞes the address to be driven on the external bus when a UPM pattern is software initiated by issuing a RUN command in the MCR The memory command and memory data registers MCR and MDR are used to initialize the UPMÕs RAM array The memory address register MAR speciÞes the location in the RAM array...

Page 435: ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field BA AT PS PARE WP MS Ñ V Reset 0000_0000_0000_0000 R W R W Addr IMMR FFFF0000 0x102 BR0 0x10A BR1 0x112 BR2 0x11A BR3 0x122 BR4 0x12A BR5 0x132 BR6 0x13A BR7 Figure 16 5 Base Registers BRx Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field BA Reset 0000_0000_0000_0000 R W R W Addr IMMR FFFF0000 0x100 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 3...

Page 436: ...tion word described in Section 12 3 1 1 00 32 bit port size 01 8 bit port size 10 16 bit port size 11 Reserved 22 PARE Parity enable Used to enable parity checking on this bank 0 Parity checking is disabled 1 Parity checking is enabled 23 WP Write protect Can be used to restrict write accesses within the address range of a BR 0 Both read and write accesses are allowed 1 Only read accesses are allo...

Page 437: ...29 30 31 Field AM ATM CSNT SAM ACS G5LA G5LS BIH SCY SETA TRLX EHTR Ñ Reset 0000_0000_0000_0000 R W R W Addr IMMR FFFF0000 0x106 Figure 16 7 Option Registers ORx Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field AM Reset 0000_0000_0000_0000 R W R Addr IMMR FFFF0000 0x104 OR0 0x10C OR1 0x114 OR2 0x11C OR3 0x124 OR4 0x12C OR5 0x134 OR6 0x13C OR7 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Fiel...

Page 438: ...MB UPMB 21Ð22 ACS ACS address to chip select setup Lets the GPCM control CSx assertion relative to address lines valid 00 CS is output at the same time as the address lines 01 Reserved 10 CS is output a quarter of a clock after the address lines 11 CS is output half a clock after the address lines G5LA G5LS G5LA and G5LS general purpose line 5 A line 5 start are used for the UPM to determine how t...

Page 439: ...lso doubles the wait states programmed in SCY 30 EHTR Extended hold time on read GPCM only 0 Timing is deÞned by the memory controller 1 After a read from the current bank an additional clock cycle is inserted before the memory controller responds to a write or read to another bank 31 Ñ Reserved should be cleared Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field PER0 PER1 PER2 PER3 PER4 PER5 PER6 PE...

Page 440: ...odic timer x to request service 0 Periodic timer x is disabled 1 Periodic timer x is enabled 9Ð11 AMx Address multiplex size x When internal address multiplexing is used this Þeld speciÞes how the address on the external bus is multiplexed when enabled see Table 16 17 The SAM bit enables address multiplexing in the Þrst clock cycle The AMx Þeld of the RAM array entry enables address multiplexing i...

Page 441: ...used to dynamically insert wait states into UPM patterns 0 UPWAITx GPL_x4 is deÞned as GPL_x4 1 UPWAITX GPL_x4 is deÞned as UPWAITx 20Ð23 RLFx Read loop Þeld x SpeciÞes in binary the number of times a loop deÞned in the UPMx RAM word is executed for a burst read or single beat read cycle 0001 1 time 0001 2 times É 1111 15 times note that 0000 16 times 24Ð27 WLFx Write loop Þeld x SpeciÞes the numb...

Page 442: ...b11 Thus the address for this pattern is the value written to MAR The data bus is not driven 11 Reserved 2Ð7 Ñ Reserved should be cleared 8 UM User machine Selects the UPM for this command 0 UPMA 1 UPMB 9Ð15 Ñ Reserved should be cleared 16Ð18 MB Memory bank Indicates the appropriate CSx pin when a RUN command is executed 000 corresponds to CS0 001 corresponds to CS1 É 111 corresponds to CS7 19 Ñ R...

Page 443: ...Table 16 8 MDR Field Descriptions Bits Name Description 0Ð31 MD Memory data Contains the RAM array word Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field MA Reset 0000_0000_0000_0000 R w R W Address IMMR FFFF0000 0x164 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field MA Reset 0000_0000_0000_0000 R W R W Address IMMR FFFF0000 0x166 Figure 16 13 Memory Address Register MAR Table 16 9 MAR Fiel...

Page 444: ... between an SRAM device and the MPC860 Figure 16 15 GPCM to SRAM ConÞguration 16 5 1 Timing ConÞguration If BRx MS selects the GPCM the attributes for the memory cycle are taken from ORx These attributes include the CSNT ACS 0Ð1 SCY 0Ð3 TRLX EHTR and SETA Þelds See Table 16 11 for signal behavior and system response Table 16 10 MPTPR Field Descriptions Bits Name Description 0Ð7 PTP Periodic timers...

Page 445: ...avior Option Register Attributes Signal Behavior TRLX Access ACS CSNT Address to CS Asserted CS Negated to Address Data Invalid WE Negated to Address Data Invalid Total Cycles 0 Read 00 x 0 1 4 Clock x 2 SCY1 0 Read 10 x 1 4 Clock 1 4 Clock x 2 SCY 0 Read 11 x 1 2 Clock 1 4 Clock x 2 SCY 0 Write 00 0 0 1 4 Clock 1 4 Clock 2 SCY 0 Write 10 0 1 4 Clock 1 4 Clock 1 4 Clock 2 SCY 0 Write 11 0 1 2 Cloc...

Page 446: ...16 17 GPCM Peripheral Device Basic Timing ACS 1x and TRLX 0 16 5 1 2 Chip Select and Write Enable Deassertion Timing Figure 16 18 shows a basic connection between the MPC860 and a static memory device Here CS is connected directly to CE of the memory device The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte Address CE R W...

Page 447: ...ing for the appropriate strobe negation in write cycles When this attribute is asserted the strobe is negated one quarter of a clock before the normal case For example when ACS 00 and CSNT 1 WE is negated one quarter of a clock earlier as shown in Figure 16 19 When ACS 00 and CSNT 1 WE and CS are negated one quarter of a clock earlier as shown in Figure 16 20 Figure 16 19 GPCM Memory Device Basic ...

Page 448: ... memory systems that require more relaxed timing between signals When TRLX 1 and ACS 00 an additional cycle between the address and strobes is inserted by the MPC860 memory controller See Figure 16 21 and Figure 16 22 Figure 16 21 GPCM Relaxed Timing Read ACS 1x SCY 1 CSNT 0 and TRLX 1 Clock Address TS TA CS WE Data CSNT 1 ACS 11 ACS 10 Clock Address TS TA CS R W WE OE Data ACS 10 ACS 11 ...

Page 449: ...lier than in the normal case If ACS 0 CS is also negated one clock earlier as shown in Figure 16 23 and Figure 16 24 When a bank is selected to operate with external transfer acknowledge SETA and TRLX 1 the memory controller does not support external devices that provide TA to complete the transfer with zero wait states The minimum access duration in this case is 3 clock cycles Clock Address TS TA...

Page 450: ...Part IV Hardware Interface Figure 16 23 GPCM Relaxed Timing Write ACS 1x SCY 0 CSNT 1 TRLX 1 Figure 16 24 GPCM Relaxed Timing Write ACS 00 SCY 0 CSNT 1 TRLX 1 Clock Address TS TA CS R W WE OE Data ACS 10 ACS 11 Clock Address TS TA CS R W WE OE Data ...

Page 451: ... or a maximum 17 clock access by programming ORx SCY The internal TA generation mode is enabled if ORx SETA is cleared If TA is asserted externally at least two clock cycles before the wait state counter has expired the current memory cycle is terminated When TRLX is set the number of wait states inserted by the memory controller is deÞned by 2 x SCY or a maximum of 30 wait states 16 5 1 6 Extende...

Page 452: ...erface Figure 16 26 GPCM Write Followed by Read EHTR 1 Figure 16 27 GPCM Read Followed by Read from Different Banks EHTR 1 Clock Address TS TA CSx CSy R W OE Data Hold Time Long hold time allowed Clock Address TS TA CSx CSy R W OE Data Hold Time Long hold time allowed ...

Page 453: ...gister is accessed The boot chip select provides a programmable port size during system reset by using the BPS Þeld of the hard reset conÞguration word described in Setting these appropriately allows a boot ROM to be located anywhere in the address space The boot chip select does not provide write protection and responds to all address types CS0 operates this way until the Þrst write to OR0 and it...

Page 454: ...the timing for TRLX 0 when an external asynchronous master accesses SRAM TA WE and OE remain asserted until the external master negates AS at which point they deassert asynchronously Table 16 12 Boot Bank Field Values after Reset Register Field Value BR0 PS From hard reset conÞguration word PARE 0 WP 0 MS 0Ð11 00 V From hard reset conÞguration word OR0 AM 0Ð16 All zeros ATM 0Ð2 000 CSNT 1 ACS 0Ð1 ...

Page 455: ...ves that provide their TA signal external to the MPC8560 ORx SETA 1 However the GPCM keeps its chip select asserted only until the Þrst TA is sampled The GPCM cannot be used to burst to an external device the requires that the chip select signal remain asserted throughout a burst transaction However if the device requires only that the chip select be asserted up to the Þrst data beat of the burst ...

Page 456: ... following events initiate a UPM cycle Any internal or external master requests an external memory access to an address space mapped to a chip select serviced by the UPM A UPM periodic timer expires and requests a transaction such as a DRAM refresh A transfer error or reset generates an exception request The MCR receives a RUN command from the CPU Figure 16 31 User Programmable Machine Block Diagr...

Page 457: ...on condition pattern EXS A special pattern in the RAM array is associated with each of these cycle type Figure 16 32 shows the start addresses of these patterns in the UPM RAM according to cycle type MCR initiated RUN commands however can initiate patterns starting at any of the 64 UPM RAM words Figure 16 32 RAM Array Indexing 16 6 1 1 Internal External Memory Access Requests When an internal mast...

Page 458: ...Periodic Timer Request Block Diagram 16 6 1 3 Software RequestsÑMCR RUN Command Software can start a request to the UPM by issuing a RUN command to the MCR Some memory devices have their own signal handshaking protocol to put them into special modes such as self refresh mode Other memory devices must be issued special commands on their control signals such as for SDRAM initialization For these spe...

Page 459: ... external signals to behave according to the timing speciÞed in the current RAM word Figure 16 34 and Figure 16 35 show the clock schemes of the UPMs in the memory controller The clock phases shown reßect timing windows during which generated signals can change state Figure 16 34 shows the clock scheme selected when the SCCR EBDF 00 CLKOUT is the same as system clock Figure 16 34 UPM Clock Scheme ...

Page 460: ...the value of TSIZn The GPL lines toggle as programmed for any access that initiates a particular pattern but resolution of control is slightly more limited The examples in Figure 16 36 and Figure 16 37 show how to control the timing of CS GPL1 and GPL2 UPM RAM words determine the values of the CST 1Ð4 G1T3 G1T4 G2T3 and G2T4 bits which specify the timing of chip selects byte selects and GPL signal...

Page 461: ...k that matches the current address The selected BS is for the byte lanes read or written by the access Figure 16 38 RAM Array and Signal Generation CLKOUT GCLK1_50 GCLK2_50 GPL2 Clock Phase 1 2 3 4 1 2 3 CS GPL1 CST3 G1T4 CST1 CST4 CST2 CST2 CST4 CST3 CST1 G1T3 G1T4 G1T4 G1T3 G1T4 G2T3 G2T4 G2T4 G2T3 System Clock RAM Word 1 RAM Word 2 4 RAM Array Signals Timing Generator CS Signal Selector BS Sign...

Page 462: ...1 Negated at the falling edge of GCLK2_50 1 CST1 Chip select timing 1 DeÞnes the state of CS during clock phase 2 0 Asserted at the rising edge of GCLK1_50 1 Negated at the rising edge of GCLK1_50 2 CST2 Chip select timing 2 DeÞnes the state of CS during clock phase 3 0 Asserted at the rising edge of GCLK2_50 1 Negated at the rising edge of GCLK2_50 3 CST3 Chip select timing3 DeÞnes the state of C...

Page 463: ... edge of GCLK2_50 1 Negated at the falling edge of GCLK2_50 13 G1T3 General purpose line 1 timing 3 DeÞnes the state of GPL1 during phase 4 0 Asserted at the falling edge of GCLK1_50 1Negated at the falling edge of GCLK1_50 14 G2T4 General purpose line 2 timing 4 DeÞnes the state of GPL2 during phase 1Ð3 0 Asserted at the falling edge of GCLK2_50 1 Negated at the falling edge of GCLK2_50 15 G2T3 G...

Page 464: ... EXEN allows branching to an exception pattern at the exception start address EXS at a Þxed address in the RAM array 0 The UPM continues executing the remaining RAM words 1 The current RAM word allows a branch to the exception pattern after the current cycle if an exception condition is detected The exception condition can be an external device asserting TEA HRESET or SRESET 26Ð27 AMX Address mult...

Page 465: ...ord The state of each BS 0Ð3 signal depends on the value of each BSTx bit and the values of BRx PS TSIZn and A 30Ð31 in the current cycle The BS signals are also controlled by the port size of the accessed bank the transfer size of the transaction and the address accessed Figure 16 41 shows how UPMs control BS signals 30 TODT Turn on disable timer Controls the disable timer mechanism This bit has ...

Page 466: ...ling edge of GCLK1_50 or GCLK2_50 GPL0 has two 2 bit Þelds that perform this function plus an additional function explained below GPL5 and GPL0 offer the following enhancements beyond the other GPLx signals GPL5 can be controlled during phase 4 of the Þrst clock cycle according to the value of G5LS as shown in Figure 16 42 This allows it to assert earlier simultaneous with TS for an internal maste...

Page 467: ...command exception or memory periodic timer requests Table 16 15 GPL_X5 Signal Behavior Controlling Machine ORx RAM Word GPL_X5 Behavior at the Controlling Clock Edge Memory Access Slave Access Clock Cycle G5LA G5LS G5T4 G5T3 GPCM x N A N A x x GPL_A5 and GPL_B5 do not change their value UPMA First x 0 x x GPL_A5 is driven low at the falling edge of GCLK1_50 1 GPL_A5 is driven high at the falling e...

Page 468: ...f GCLK1_50 1 GPL_B5 is driven high at the falling edge of GCLK1_50 1 0 x x GPL_A5 is driven low at the falling edge of GCLK1_50 1 GPL_A5 is driven high at the falling edge of GCLK1_50 Second third 0 x 0 x GPL_B5 is driven low at the falling edge of GCLK2_50 in the current UPM cycle 1 x GPL_B5 is driven high at the falling edge of GCLK2_50 in the current UPM cycle x 0 GPL_B5 is driven low at the fa...

Page 469: ...lower address lines MxMR AMA and MxMR AMB control which upper address signals are on which lower address signals Note that this feature of internally multiplexing address signals should only be used in a system where the MPC860 is the only external bus master If other devices can be bus masters address multiplexing must be done in external logic One of the UPMÕs output signals can be used to contr...

Page 470: ...n when Address Multiplexing is Enabled Ñ Ñ A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 001 Ñ A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 010 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 011 Ñ A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 100 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 101 Ñ A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A...

Page 471: ...2 Mbyte 13 A19ÐA31 4 Mbyte 14 A18ÐA31 256 Kbyte 9 9 A23ÐA31 001 512 Kbyte 10 A22ÐA31 1 Mbyte 11 A21ÐA31 2 Mbyte 12 A20ÐA31 4 Mbyte 13 A19ÐA31 8 Mbyte 14 A18ÐA31 16 Mbyte 15 A17ÐA31 8 bits 1 Mbyte 10 10 A22ÐA31 010 2 Mbyte 11 A21ÐA31 4 Mbyte 12 A20ÐA31 8 Mbyte 13 A19ÐA31 16 Mbyte 14 A18ÐA31 32 Mbyte 15 A17ÐA31 64 Mbyte 16 A16ÐA31 4 Mbyte 11 11 A21ÐA31 011 8 Mbyte 12 A20ÐA31 16 Mbyte 13 A19ÐA31 32 M...

Page 472: ...e 14 A17ÐA30 2 Mbyte 10 10 A21ÐA30 010 4 Mbyte 11 A20ÐA30 8 Mbyte 12 A19ÐA30 16 Mbyte 13 A18ÐA30 32 Mbyte 14 A17ÐA30 64 Mbyte 15 A16ÐA30 8 Mbyte 11 11 A20ÐA30 011 16 Mbyte 12 A19ÐA30 32 Mbyte 13 A18ÐA30 64 Mbyte 14 A17ÐA30 32 Mbyte 12 12 A19ÐA30 100 64 Mbyte 13 A18ÐA30 128 Mbyte 14 A17ÐA30 256 Mbyte 15 A16ÐA30 128 Mbyte 13 13 A18ÐA30 101 256 Mbyte 13 A17ÐA30 Table 16 18 AMA AMB Definition for DRAM...

Page 473: ...d on the falling edge of GCLK2_50 instead of the rising edge which is normal This feature lets the user speed up the memory interface by latching data 1 2 clock early which can be useful during burst reads This feature should be used only in systems without external synchronous bus devices 32 bits 256 Kbyte 8 8 A22ÐA29 000 512 Kbyte 9 A21ÐA29 1 Mbyte 10 A20ÐA29 2 Mbyte 11 A19ÐA29 4 Mbyte 12 A18ÐA2...

Page 474: ...S precharge enforced outside of itself while another pattern requires only n 1 16 6 4 10 The Last Word LAST When the LAST bit is read in a RAM word the current UPM pattern terminates and the highest priority pending UPM request if any is serviced immediately in the external memory transactions If the disable timer is activated and the next access is top the same bank the execution of the next UPM ...

Page 475: ... previous falling edge of GLCK2_50 and WAEN 1 in the current RAM word In this wait state external signals are frozen after the falling edge of GCLK2_50 as programmed in the RAM word in which WAEN is set This is demonstrated in the example in Figure 16 46 in which the CSx and GPL1 states C12 and F and the WAEN value CC are frozen until AS is recognized as deasserted The TA signal driven by the UPM ...

Page 476: ...e very slow access time is greater than the maximum allowed by the user programming model or cannot guarantee a predeÞned access time for example some FIFO hierarchical bus interface or dual port memory devices These mechanisms are as follows The wait mechanismÑUsed only in accesses controlled by the UPM MAMR GPLA4DIS and MBMR GPLB4DIS enable this mechanism The external TA mechanism is used only i...

Page 477: ... time exceeds the maximum allowed by the user programming model The wait solution UPM ÑThe CPU generates a read access from the slow device The device in turn asserts the wait signal as long as the data is not ready The CPU samples data only after the wait signal is negated The external TA solution GPCM ÑThe CPU generates a read access from the slow device which must generate the synchronous TA wh...

Page 478: ...ted with the negation of AS If AEME 0 the memory controller is bypassed and the external asynchronous master must provide control signals to the slave In this mode the MPC860Õs AS signal cannot be used as an input See Figure 16 48 16 8 3 Special Case Address Type Signals for External Masters The AT signals are not sampled on the external bus for external master accesses When external masters acces...

Page 479: ... following sections provide external master examples 16 8 5 1 External Masters and the GPCM The following Þgures show examples of external mastersÕinteraction with the GPCM Note that synchronous and external masters behave differently Synchronous external masters behave like internal masters except for an extra clock cycle at the beginning of the access required for address decode Asynchronous ext...

Page 480: ...ng this conÞguration BADDR 28Ð30 connects to the multiplexer controlled by GPL_A5 Figure 16 50 shows the timing behavior of GPL_A5 BADDR and other control signals when an external master initiates a burst read access The state of GPL_A5 in the Þrst clock cycle of the memory device access is determined by the value of the corresponding ORx G5LS In this example the accessed critical word is addresse...

Page 481: ...ntroller 16 55 Part IV Hardware Interface Figure 16 49 Synchronous External Master Interconnect Example External DRAM Multiplexer Master MPC860 A 6Ð31 BADDR 28Ð30 D 0Ð31 R W TS BURST TA TSIZ 0Ð1 BI BR BG BB CS1 BS 0Ð3 GPL_A5 Bank ...

Page 482: ... 0 1 0 1 0 1 bst3 Bit 7 1 0 1 0 1 0 1 0 1 g0l0 Bit 8 g5t4 Bit 20 0 1 1 1 1 1 1 1 1 g5t3 Bit 21 0 1 1 1 1 1 1 1 1 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 1 0 1 0 1 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 X amx1 Bit 27 0 0 0 0 0 0 0 0 X na Bit 28 0 0 1 0 1 0 1 0 X uta Bit 29 1 0 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 0 0 0 1 last Bit 31 0 0 0 0 0 0 0 0 1 RBS RBS 1 RBS 2 RBS 3 RBS 4 RBS ...

Page 483: ...Figure 16 52 shows the timing behavior of GPL_A5 and other control signals when an external master to a DRAM bank initiates a single beat read The state of GPL_A5 in the Þrst clock cycle of the memory device access is determined by the value of the corresponding ORx G5LS Figure 16 51 Asynchronous External Master Interconnect Example External DRAM Multiplexer Master MPC860 A 6Ð31 D 0Ð31 R W AS TA T...

Page 484: ...t 0 0 0 0 0 0 cst1 Bit 1 0 0 0 0 0 cst2 Bit 2 0 0 0 0 1 cst3 Bit 3 0 0 0 0 1 bst4 Bit 4 1 1 0 0 0 bst1 Bit 5 1 0 0 0 0 bst2 Bit 6 1 0 0 0 1 bst3 Bit 7 1 0 0 0 1 g4t4 Bit 18 g4t3 WAEN Bit 19 0 1 1 1 0 g5t4 Bit 20 0 1 1 1 0 g5t3 Bit 21 0 1 1 1 1 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 exen Bit 25 0 0 0 0 0 amx0 Bit 26 0 0 0 0 0 amx1 Bit 27 0 0 0 0 0 na Bit 28 0 0 0 0 0 uta Bit 29 1 0 0 0 1 todt Bit ...

Page 485: ...tem architecture which includes the MPC860 and the memory system as shown in the example in Figure 16 53 2 Use the blank work sheet in Figure 16 70 to draw the timing diagrams for all the memory cycles The timing diagrams in Figure 16 54 through Figure 16 62 can be used as a reference Alternately use the UPM860 or MCU unit applications for this These applications are available at http www mot com ...

Page 486: ...quent cycles are controlled by the UPM RAM words Also notice that the AMX Þeld in the UPM RAM word controls address multiplexing for the next clock cycle rather than the current one Ñ Program MAMR to select the number of columns and refresh timer parameters Table 16 19 UPMA Register Settings Register Field Value Comments BR1 MS 10 Selects UPMA PS 00 Selects 32 bit bus width WP 0 Allows read and wr...

Page 487: ...1 bst3 Bit 7 1 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 exen Bit 25 0 0 0 amx0 Bit 26 0 0 x amx1 Bit 27 0 0 x na Bit 28 0 0 x uta Bit 29 1 0 1 todt Bit 30 0 0 1 last Bit 31 0 0 1 RSS RSS 1 RSS 2 CLKOUT GCLK2_50 GCLK1_50 A 6Ð31 TS R W D...

Page 488: ...0 1 bst3 Bit 7 1 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 exen Bit 25 0 0 0 amx0 Bit 26 0 0 x amx1 Bit 27 0 0 x na Bit 28 0 0 x uta Bit 29 1 0 1 todt Bit 30 0 0 1 last Bit 31 0 0 1 WSS WSS 1 WSS 2 CLKOUT GCLK2_50 GCLK1_50 A 6Ð31 TS R W...

Page 489: ...l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 1 0 1 0 1 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 x na Bit 28 0 0 1 0 1 0 1 0 x uta Bit 29 1 0 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 0 0 0 1 last Bit 31 0 0 0 0 0 ...

Page 490: ...g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 1 1 0 0 exen Bit 25 0 0 1 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 1 0 x uta Bit 29 1 0 1 0 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 RBS RBS 1 RBS 2 RBS 3 RBS 4 CLKOUT GCLK2_50...

Page 491: ...0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 1 0 1 0 1 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 x na Bit 28 0 0 1 0 1 0 1 0 x uta Bit 29 1 0 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 0 0 0 1 last Bit 31 0 0 0 0 0...

Page 492: ...g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 1 1 0 0 exen Bit 25 0 0 1 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 1 0 x uta Bit 29 1 0 1 0 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 WBS WBS 1 WBS 2 WBS 3 WBS 4 CLKOUT GCLK2_50...

Page 493: ... 0 bst2 Bit 6 0 0 1 bst3 Bit 7 0 0 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 exen Bit 25 0 0 0 amx0 Bit 26 0 0 x amx1 Bit 27 0 0 x na Bit 28 0 0 x uta Bit 29 1 1 1 todt Bit 30 0 0 1 last Bit 31 0 0 1 PTS PTS 1 PTS 2 CLKOUT GCLK2_50 GCLK1_...

Page 494: ...n be reduced from 9 to 6 cycles for 32 bit port size Cycles can be reduced by using faster DRAM or a slower system clock that meets the DRAM access time For a 16 bit port size memory the reduction is from 17 to 10 cycles and when an 8 bit port size memory is connected the reduction is from 33 to 18 cycles cst4 Bit 0 1 cst1 Bit 1 1 cst2 Bit 2 1 cst3 Bit 3 1 bst4 Bit 4 1 bst1 Bit 5 1 bst2 Bit 6 1 bs...

Page 495: ... g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 1 1 1 1 1 1 g4t3 Bit 19 0 0 0 0 0 0 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 0 exen Bit 25 0 0 0 0 0 0 amx0 Bit 26 0 0 0 0 1 x amx1 Bit 27 0 0 0 0 0 x na Bit 28 0 1 1 1 0 x uta Bit 29 1 0 1 0 0 1 todt Bit 30 0 0 0 0 0 1 last Bit 31 0 0 0 0 0 1 RBS RBS 1 RBS 2 RBS 3 RB...

Page 496: ...s multiplexing internally Figure 16 63 EDO DRAM Interface Connection Follow these steps to conÞgure a system for EDO DRAM 1 Determine the system architecture which includes the MPC860 and the memory system as shown in the example in Figure 16 64 2 The blank work sheet in Figure 16 70 can be used for timing diagrams The timing diagrams in Figure 16 64 through Figure 16 69 can be used as a reference...

Page 497: ...o note that the AMX Þeld in the UPM RAM word controls address multiplexing for the next clock cycle and not the current one Ñ Program MBMR to select the number of columns and refresh timer parameters Table 16 20 UPMB Register Settings Field Register Value Comments MS BR2 10 Selects UPMB PS BR2 00 Selects 32 bit bus width WP BR2 0 Allows read and write accesses PTP MPTPR 00000010 Prescaler divided ...

Page 498: ...0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 0 0 0 0 0 g1t3 Bit 13 0 0 0 0 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 exen Bit 25 0 0 0 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 0 0 x uta Bit 29 1 1 1 0 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 RSS RSS 1 RSS 2 RSS 3 RSS ...

Page 499: ...g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 1 1 1 1 g1t3 Bit 13 1 1 1 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 exen Bit 25 0 0 0 0 amx0 Bit 26 0 0 0 x amx1 Bit 27 0 0 0 x na Bit 28 0 0 0 x uta Bit 29 1 1 0 1 todt Bit 30 0 0 0 1 last Bit 31 0 0 0 1 WSS WSS 1 WSS 2 WSS 3 CLKOUT GCLK2_50 GCLK1...

Page 500: ...Bit 12 0 0 0 0 0 0 0 0 0 0 0 g1t3 Bit 13 0 0 0 0 0 0 0 0 0 0 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 0 1 0 1 0 1 0 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 0 0 x na Bit 28 0 0 1 0 0 1 0 1 0 0 x uta Bit 29 1 1 1 0 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 ...

Page 501: ...1t4 Bit 12 1 1 1 1 1 1 1 1 1 1 g1t3 Bit 13 1 1 1 1 1 1 1 1 1 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 0 0 0 0 0 exen Bit 25 0 0 0 1 0 1 0 1 0 0 amx0 Bit 26 0 0 0 0 0 0 0 0 0 x amx1 Bit 27 0 0 0 0 0 0 0 0 0 x na Bit 28 0 0 0 1 0 1 0 1 0 x uta Bit 29 1 0 1 1 0 1 0 1 0 1 todt Bit 30 0 0 0 0 0 0 0 0 0 1 la...

Page 502: ...t 7 0 1 1 1 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 1 1 1 1 1 g1t3 Bit 13 1 1 1 1 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 0 0 0 0 exen Bit 25 0 0 0 0 0 amx0 Bit 26 0 0 0 0 x amx1 Bit 27 0 0 0 0 x na Bit 28 0 0 0 0 x uta Bit 29 1 1 1 1 1 todt Bit 30 0 0 0 0 1 last Bit 31 0 0 0 0 1 PTS PTS 1...

Page 503: ...st2 Bit 6 1 bst3 Bit 7 1 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 1 g1t3 Bit 13 1 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 0 exen Bit 25 0 amx0 Bit 26 x amx1 Bit 27 x na Bit 28 x uta Bit 29 1 todt Bit 30 1 last Bit 31 1 EXS CLKOUT GCLK2_50 GCLK1_50 TA CS2 RAS BS_B 0Ð3 CAS 0Ð3 GPL_B1 OE ...

Page 504: ...8 g0l1 Bit 9 g0h0 Bit 10 g0h1 Bit 11 g1t4 Bit 12 g1t3 Bit 13 g2t4 Bit 14 g2t3 Bit 15 g3t4 Bit 16 g3t3 Bit 17 g4t4 Bit 18 g4t3 Bit 19 g5t4 Bit 20 g5t3 Bit 21 Ð Bit 22 Ð Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 na Bit 28 uta Bit 29 todt Bit 30 last Bit 31 xxS xxS 1 xxS 2 xxS 3 xxS 4 xxS 5 xxS 6 xxS 7 xxS 8 xxS 9 xxS 10 CLKOUT GCLK2_50 GCLK1_50 A 6Ð31 R W D 0Ð31 TA CSx RAS BS_x 0Ð3 CAS ...

Page 505: ...his system conÞguration the sockets and system bus must be electricalyl isolated using external buffers and bus transceivers These buffers also provide voltage conversion required from the 3 3 to 5 V cards These somponents should be powered by the card power supply Because the MPC860 can accept 5 V inputs while generating 3 3 V outputs conversion is not required for inputs The PCMCIA host adapter ...

Page 506: ...ess_A 25 0 CE1_A CE2_A 3V 12V Socket MAX 780A A 6 31 8 8 1 1 26 1 1 1 Vcc_A Vpp1_A 5V 1 Vpp2_A WE PGM REG_A 1 REG OE_A 1 OE IORD_A IOWR_A 2 IORD IOWR RESET_A B 2 SPKROUT PCMCIA Host Adapter A Module 2 2 26 2X3 1 1 1 2 2x2 8 8 B 1 1 6 2 or equiv WAIT_A B IOIS16_A B 2 Power On indication POE_A B 2 IRQ 2 1 buffer with OE Transparent latch with OE Transceiver buffer with OE CD1_x CD2_x VS1_x VS2_x 2X4...

Page 507: ... 0 8 bit odd 1 0 1 8 bit even 0 1 0 No access X 1 1 D 0Ð15 Data bus Bidirectional D 0Ð15 constitute the bidirectional data bus The msb is D0 and the lsb is D15 WAIT_ Extend bus cycle Input Asserted by the PC card to delay completion of the pending memory or I O cycle R W External transceiver direction Output Asserted during MPC860 read cycles and negated driven low during write cycles Used in the ...

Page 508: ... are connected to IP_x 0Ð1 WP Write protect Input When the card and socket are programmed for memory interface operation this signal is used as WP It reßects the state of the write protect switch on the PC card The PC card must assert WP when the card switch is enabled It must be negated when the switch is disabled For a PC card that is writable without a switch WP must be connected to ground If t...

Page 509: ..._x and must be asserted by a PC card to indicate that the PC card is busy processing a previous write command When the card and its socket are programmed for I O interface operation this signal is used as IREQ_x and must be asserted by a PC card to indicate that a device on the PC card requires service by host software Must be held negated when no interrupt is requested These signals are connected...

Page 510: ... on level low or high or edge fall or rise of the input signal 1 Because the minimum hold time is one clock the real access time is access time one clock 2 Worst case setup time STP The worst case setup time is address to strobe 3 Length LNG is the minimum strobe time 4 Worst case hold time HLD The worst case hold time is data disable from OE 1 Setup time worst case is for a write In these cases s...

Page 511: ...an I O device implemented as a PCMCIA card to respond to DMA transfer Any window can be programmed as a DMA window through PORxB PRS When conÞgured appropriately the PCMCIA controller supplies the required signals to the socket Notice that DMA to and from the PCMCIA interface is handled through dual access DMA transfers DMA requests can be supplied through SPKR IOIS16 or INPACK To support DMA INPA...

Page 512: ...R PCMCIA interface enable register PGCRA PCMCIA interface general control register a PGCRB PCMCIA interface general control register b PBR 0Ð7 PCMCIA base registers 0Ð7 per window POR 0Ð7 PCMCIA option registers 0Ð7 per window Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field CAVS1 CAVS2 CAWP CACD2 CACD1 CABVD2 CABVD1 CARDY Ñ Field Ñ Reset 0000_0000_0000_0000 R W R Addr IMMR 0xFFFF0000 0x0F0 Bit 16 ...

Page 513: ...BVD1 Battery voltage STSCHG IN for card B 23 CBRDY RDY IRQ of card B pin 24Ð31 Ñ Reserved should be cleared Bit 0 1 2 3 4 5 6 7 8 9 10 11 12Ð15 Field CAVS1_C CAVS2_C CAWP_C CACD2_C CACD1_C CABVD2_C CABVD1_C Ñ CARDY_L CARDY_H CARDY_R CARDY_F Ñ Reset UndeÞned R W R W Addr IMMR 0xFFFF0000 0x0E8 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28Ð31 Field CBVS1_C CBVS2_C CBWP_C CBCD2_C CBCD1_C CBBVD2_C CBBVD1_...

Page 514: ...0 CBCD1_C Card detect 1 for card B changed 21 CBBVD2_C Battery voltage SPKR in for card B changed 22 CBBVD1_C Battery voltage STSCHG in for card B changed 23 Ñ Reserved should be cleared 24 CBRDY_L RDY IRQ of card B pin is low Device and socket interrupt 25 CBRDY_H RDY IRQ of card B pin is high Device and socket interrupt 26 CBRDY_R RDY IRQ of card B pin rising edge detected Device and socket inte...

Page 515: ...rd A pin is high 10 CA_ERDY_R Enable for RDY IRQ card A pin rising edge detected 11 CA_ERDY_F Enable for RDY IRQ card A pin falling edge detected 12Ð15 Ñ Reserved should be 0 16 CB_EVS1 Enable for voltage sense 1 for card B changed Setting this bit enables the interrupt on any signal change 17 CB_EVS2 Enable for voltage sense 2 for card B changed Setting this bit enables the interrupt on any signa...

Page 516: ...eneral Control Register B PGCRx Table 17 11 PGCRx Field Descriptions Bits Name Description 0Ð7 CxIREQLVL Card x IREQ interrupt level Only one bit of this Þeld should be set at any time 8Ð15 CxSCHLVL Card x STSCHG interrupt level Only one CASCHLVLx bit should be set at any time 16Ð17 CxDREQ Card x DREQ DeÞnes internal DMA request for the on chip DMA controller CADREQ controls channel 0 CBDREQ contr...

Page 517: ...e 17 12 PBR Field Descriptions Bits Name Description 0Ð31 PBA PCMCIA base address Compared to the address on the address bus to determine if a PCMCIA window is being accessed by an internal bus master PBA is used in conjunction with POR BSIZE Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field BSIZE Ñ PSHT Reset UndeÞned R W R W Addr IMMR 0xFFFF0000 0x084 POR0 0x08C POR1 0x094 POR2 0x09C POR3 0x0A4 PO...

Page 518: ...111 1111 1111 1100 0000 00100 1111 1111 1111 1111 1111 1111 1000 0000 01100 1111 1111 1111 1111 1111 1111 0000 0000 01101 1111 1111 1111 1111 1111 1110 0000 0000 01111 1111 1111 1111 1111 1111 1100 0000 0000 01110 1111 1111 1111 1111 1111 1000 0000 0000 01010 1111 1111 1111 1111 1111 0000 0000 0000 01011 1111 1111 1111 1111 1110 0000 0000 0000 01001 1111 1111 1111 1111 1100 0000 0000 0000 01000 11...

Page 519: ...111 Strobe asserted 31 clock cycles 00000 Strobe asserted 32 clock cycles 25 PPS PCMCIA port size SpeciÞes the port size of this PCMCIA window 0 8 bits port size 1 16 bits port size 26Ð28 PRS PCMCIA region select 000 Common memory space 001 Reserved 010 Attribute memory space 011 I O space 100 DMA normal DMA transfer 101 DMA last transaction 11x Reserved Note The DMA encoding generates a normal DM...

Page 520: ...Manual MOTOROLA Part IV Hardware Interface 17 5 PCMCIA Controller Timing Examples Figure 17 9 PCMCIA Single Beat Read Cycle PRS 0 PSST 1 PSL 3 PSHT 1 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE PCOE WAIT CE1 2 PSST PSL PSHT ...

Page 521: ...hapter 17 PCMCIAInterface 17 17 Part IV Hardware Interface Figure 17 10 PCMCIA Single Beat Read Cycle PRS 0 PSST 2 PSL 4 PSHT 1 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE PCOE WAIT CE1 2 PSST PSL PSHT ...

Page 522: ... PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface Figure 17 11 PCMCIA Single Beat Read Cycle PRS 0 PSST 1 PSL 3 PSHT 0 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE PCOE WAIT CE1 2 PSST PSL PSHT ...

Page 523: ...hapter 17 PCMCIAInterface 17 19 Part IV Hardware Interface Figure 17 12 PCMCIA Single Beat Write Cycle PRS 2 PSST 1 PSL 3 PSHT 1 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE PCWE WAIT CE1 2 PSST PSL PSHT ...

Page 524: ...werQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface Figure 17 13 PCMCIA Single Beat Write Cycle PRS 3 PSST 1 PSL 4 PSHT 3 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE IOWR WAIT CE1 2 PSST PSL PSHT IO16 ...

Page 525: ...7 PCMCIAInterface 17 21 Part IV Hardware Interface Figure 17 14 PCMCIA Single Beat Write with Wait PRS 3 PSST 1 PSL 3 PSHT 0 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE IOWR WAIT CE1 2 PSST PSL PSHT WAIT DELAY ...

Page 526: ...ICC UserÕs Manual MOTOROLA Part IV Hardware Interface Figure 17 15 PCMCIA Single Beat Read with Wait PRS 3 PSST 1 PSL 3 PSHT 1 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE IORD WAIT CE1 2 PSST PSL PSHT WAIT DELAY ...

Page 527: ...A Chapter 17 PCMCIAInterface 17 23 Part IV Hardware Interface Figure 17 16 PCMCIA I O Read PPS 1 PRS 3 PSST 1 PSL 2 PSHT 0 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE IOWR CE1 PSST PSHT CE2 IO16 PSL ...

Page 528: ...erQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface Figure 17 17 PCMCIA I O Read PPS 1 PRS 3 PSST 1 PSL 2 PSHT 0 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE IOWR CE1 PSST PSHT CE2 IO16 PSST PSL PSL PSHT ...

Page 529: ...ace 17 25 Part IV Hardware Interface Figure 17 18 PCMCIA DMA Read Cycle PRS 4 PSST 1 PSL 3 PSHT 0 CLKOUT A 0Ð31 TS BR BG BB DATA TA RD WR BURST REG ALE IORD SIZE CE1 2 PSST PSHT SIZE WORD PSL PCOE PSST PSL PSHT SIZE HALF AT 0XF AT 0XF ...

Page 530: ...17 26 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part IV Hardware Interface ...

Page 531: ...ns processor CP that it contains note that this is separate from the embedded PowerPC processor It contains the following chapters Chapter 18 ÒCommunications Processor Module and CPM Timers Ó provides a brief overview of the MPC860 CPM and a detailed discussion of the clocking mechanisms supported Chapter 19 ÒCommunications Processor Ó describes the RISC communications processor CP which handles t...

Page 532: ...de Ó describes the MPC860 implementation of Ethernet protocol Chapter 29 ÒSCC Transparent Mode Ó describes the MPC860 implementation of transparent mode also called totally transparent mode which provides a clear channel on which the SCC can send or receive serial data without bit level manipulation Chapter 30 ÒSerial Management Controllers Ó describes two serial management controllers full duplex...

Page 533: ...iÞcations reference materials and detailed applications notes PowerPC Documentation The PowerPC documentation is organized in the following types of documents Programming environments manualsÑThese books provide information about resources deÞned by the PowerPC architecture that are common to PowerPC processors There are two versions one that describes the functionality of the combined 32 and 64 b...

Page 534: ...ax used to identify a destination GPR REG FIELD Abbreviations or acronyms for registers or buffer descriptors are shown in uppercase text SpeciÞc bits Þelds or numerical ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit Þeld indicates a donÕt care n Indicates an undeÞned...

Page 535: ...Effective address EEST Enhanced Ethernet serial transceiver EPROM Erasable programmable read only memory GCI General circuit interface GPCM General purpose chip select machine GUI Graphical user interface HDLC High level data link control I2C Inter integrated circuit IDL Inter chip digital link IEEE Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated se...

Page 536: ...A Serial DMA SI Serial interface SIU System interface unit SMC Serial management controller SNA Systems network architecture SPI Serial peripheral interface SRAM Static random access memory TDM Time division multiplexed TE Terminal endpoint of an ISDN connection TLB Translation lookaside buffer TSA Time slot assigner Tx Transmit UART Universal asynchronous receiver transmitter UPM User programmabl...

Page 537: ...rts multiple communications channels and protocols and it has ßexible Þrmware programmability The CPM frees the core of many computational tasks in the following ways By reducing the interrupt rate The core is interrupted only upon frame reception or transmission instead of on a per character basis By implementing some of the OSI layer 2 processing which provides more core bandwidth for higher lay...

Page 538: ...annels for memory to memory transfers or interfacing external peripherals Ñ RISC timer tables Four full duplex serial communications controllers SCCs that support the following Ñ UART protocol asynchronous or synchronous Ñ HDLC protocol Ñ AppleTalk protocol Ñ Asynchronous HDLC protocol Ñ BISYNC protocol 4 Baud Rate Generators SCC1 U Bus SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C Interrupt Controller 4 Timer...

Page 539: ...upport for master or slave modes Inter integrated circuit I2C bus controller Parallel interface port supporting Centronics A serial interface SI with a time slot assigner TSA that supports multiplexing of data from SCCs and SMCs onto two time division multiplexed TDM interfaces Four independent baud rate generators BRGs Four general purpose 16 bit timers or two 32 bit timers CPM interrupt controll...

Page 540: ...consists of the following Timer mode register TMR Timer capture register TCR Timer counter TCN Timer reference register TRR Timer event register TER Timer global conÞguration register TGCR EEST MC68160 T1 E1 Xceiver Embedded PowerPC Core SCC1 SCC3 32 Bit RISC RS 422 S T U Xceiver TDMa TDMb Time Slot Assigner PCMCIA SMC2 SPI I2C RJ 45 D 15 Mini DIN 8 MCM2814 RS 232 D 9 Debug Terminal Serial EPROM P...

Page 541: ...deable to form 32 bit timers Free run and restart modes Functionally compatible with MC68360 timers 18 2 2 CPM Timer Operation The following subsections describe the timer operation The timer mode registers TMRx and the timer global conÞguration register TGCR mentioned in this section are described in Section 18 2 3 ÒCPM Timer Register Set Ó Timer Clock Generator Capture Detection Event Register M...

Page 542: ... period is 268 435 456 cycles which is 10 7 seconds at 25 MHz 18 2 2 2 Timer Reference Count TMRx FRR the free run restart bit can be conÞgured so that when a reference is reached the count either continues or begins again When the reference value is reached the corresponding TERx event bit is set and an interrupt is issued if TMRx ORI 1 Also when the reference value is reached timers can output a...

Page 543: ...rating mode is selected in the TGCR Note that TGATEx is internally synchronized to the system clock However if TGATEx meets the asynchronous input setup time the counter begins counting after one system clock when the input clock source TMRx ICLK is internal 18 2 2 5 Cascaded Mode Timer 1 can be internally cascaded to timer 2 and timer 3 can be internally cascaded to timer 4 to form 32 bit timers ...

Page 544: ... The corresponding timer ignores the FRZ state 1 Stops the corresponding timer if the MPC860 enters FRZ state FRZ state is entered in debug mode as deÞned in Chapter 37 ÒSystem Development and Debugging Ó 2 6 10 14 STPx Stop timer x 0 Normal operation 1 Stop the timer This bit stops all clocks to the timer except the U bus interface clock allowing the timer registers to be read or written The cloc...

Page 545: ...nput by a value between 1 and 256 A 0x00 value divides the clock by 1 0xFF divides it by 256 8Ð9 CE Capture edge and enable Interrupt 00 Disable interrupt on capture event capture function is disabled 01 Capture on rising TINx edge only and enable interrupt on capture event 10 Capture on falling TINx edge only and enable interrupt on capture event 11 Capture on any TINx edge and enable interrupt o...

Page 546: ...causing its corresponding prescaler TMRx PS to be reset 13Ð14 ICLK Input clock source for the timer 00 Internally cascaded input For TMR1 the timer 1 input is the output of timer 2 For TMR3 the timer 3 input is the output of timer 4 For TMR2 and TMR4 this selection means no input clock is provided to the timer 01 Internal general system clock 10 Internal general system clock divided by 16 11 Corre...

Page 547: ...vent bits writing zeros has no effect Both event bits must be cleared before the timer negates the interrupt to the CPIC Table 18 3 describes the TER Þelds Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Up counter Reset 0 R W R W Addr 0x99C TCN1 0x99E TCN2 0x9AC TCN3 0x9AE TCN4 Figure 18 9 Timer Capture Registers TCR1ÐTCR4 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ REF CAP Reset 0 Addr 0x9...

Page 548: ...nable timer 2 interrupts in the CPIC and initialize the CICR 7 Set TGCR 0x0010 to enable timer 2 to begin counting To implement the same function with a 32 bit timer using timers 1 and 2 follow these steps 1 Set TGCR 0x0080 Cascade timers 1 and 2 and put them in reset state 2 Set TMR2 0x001A to set the prescaler to divide by 1 and the clock source to the general system clock This value also enable...

Page 549: ...or data communications and processing required by many wire line and wireless communications standards The CPÕs multiplier accumulator MAC composed of a 16 x 16 bit multiplier with two 40 bit accumulators supports many DSP applications as well 19 1 Features The following lists the CPÕs main features Performs lower layer protocol processing for communication channels Protocol processing microcode r...

Page 550: ... time 19 3 Communicating with the Peripherals The CP uses the peripheral bus to communicate with the peripherals The serial communications controllers SCCs have separate receive and transmit FIFOs The SCC1 receive and transmit FIFOs are 32 bytes each SCC2ÐSCC4 FIFOs are 16 bytes each The serial management controllers SMCs serial peripheral interface SPI and I2C are all double buffered creating eff...

Page 551: ...t 1 Reset in the CPCR or SRESET 2 SDMA bus error 3 Commands issued to the CPCR 4 IDMA emulation DREQ0 and DSP1 defaultÑoption 1 1 5 IDMA emulation DREQ1 and DSP2 defaultÑoption 1 1 6 SCC1 Rx 7 SCC1 Tx 8 SCC2 Rx 9 SCC2 Tx 10 SCC3 Rx 11 SCC3 Tx 12 SCC4 Rx 13 SCC4 Tx 14 IDMA emulation DREQ0 and DSP1 option 2 1 15 IDMA emulation DREQ1 and DSP2 option 2 1 16 SMC1 Rx 17 SMC1 Tx 18 SMC2 Rx 19 SMC2 Tx 20 ...

Page 552: ...er Set and CP Commands The following sections describe the communications processor registers and commands 19 5 1 RISC Controller ConÞguration Register RCCR The RISC controller conÞguration register RCCR shown in Figure 19 2 tells the CP to run microcode from ROM or dual port RAM and controls the CPÕs internal timer It also sets the IDMA request modes and priority 1 Offset from the base of the mis...

Page 553: ...A request 0 mode Controls the IDMA request 0 DREQ0 sensitivity mode See Section 20 3 7 ÒIDMA Interface SignalsÑDREQ and SDACK Ó 0 DREQ0 is edge sensitive 1 DREQ0 is level sensitive 10Ð11 DRQP IDMA emulation request priority Controls the priority of the external request signals that relate to the serial channels See Section 19 3 ÒCommunicating with the Peripherals Ó 00 IDMA requests have priority o...

Page 554: ...ximately 60 clocks but CPM initialization can start immediately after this command is issued Use RST to reset the registers and parameters for all the channels SCCs SMCs SPI I2C and PIP as well as the CPM and timer table RST does not however affect the serial interface or parallel I O registers 0 No reset issued 1 Reset issued 1Ð3 Ñ Reserved Should be cleared 4Ð7 OPCODE Operation code for the core...

Page 555: ...NIT RX AND TX PARAMS INIT RX AND TX PARAMS Ñ Ñ Ñ 0001 INIT RX PARAMS INIT RX PARAMS Ñ INIT RX PARAMS INIT RX PARAMS Ñ Ñ Ñ 0010 INIT TX PARAMS INIT TX PARAMS Ñ INIT TX PARAMS INIT TX PARAMS Ñ Ñ Ñ 0011 ENTER HUNT MODE ENTER HUNT MODE Ñ Ñ Ñ Ñ Ñ Ñ 0100 STOP TX STOP TX Ñ Ñ Ñ Ñ Ñ Ñ 0101 GRACEFUL STOP TX Ñ Ñ Ñ Ñ INIT IDMA Ñ Ñ 0110 RESTART TX RESTART TX Ñ Ñ Ñ Ñ Ñ Ñ 0111 CLOSE RX BD CLOSE RX BD Ñ CLOSE RX ...

Page 556: ...nsmission needs to be stopped as quickly as possible Transmission continues when RESTART TX is issued GRACEFUL STOP TX Graceful stop transmission Stops the transmitting channel after the whole current frame has been sent Transmission continues when RESTART TX is issued and the ready bit is set in the next TxBD RESTART TX Restart transmission After STOP TX or GRACEFUL STOP TX RESTART TX starts the ...

Page 557: ...crocode for the CP in system RAM only Scratchpad area for user software in any unused dual port RAM area The dual port RAM can be accessed either by the CP or by one of two internal U bus mastersÑthe PowerPC core or an SDMA channel The core and the SDMA channels access the dual port RAM in two clocks while the CP takes only one clock For simultaneous accesses with at least one write operation the ...

Page 558: ...available Depending on the memory requirements of the microcode package some or all of the shaded areas of Figure 19 5 become locked Reads to locked areas return all ones The unshaded 1 536 byte area of system RAM is always available to the user The enable RAM microcode Þeld of the RISC conÞguration register RCCR ERAM selects the three possible conÞgurations for microcode area sizesÑÞrst 512 byte ...

Page 559: ...dual port RAM called the parameter RAM It contains parameters for SCC SMC SPI I2C and IDMA channel operation Table 19 8 shows the parameter RAM memory map Table 19 7 General BD Structure BD Base Offset Field 0x00 Status and control 0x02 Data length 0x04 High order of buffer pointer 0x06 Low order of buffer pointer Table 19 8 Parameter RAM Memory Map Offset from IMMR Page Offset from DPRAM_base Con...

Page 560: ... Section 19 5 1 ÒRISC Controller ConÞguration Register RCCR Ó The tick is a multiple of 1 024 general system clocks The RISC timer table has the lowest priority of all CP operations so if it is busy with other tasks and unable to service the timer during a tick interval one or more of the timers might not be updated This behavior can be used to estimate the worst case loading of the CP see Section...

Page 561: ...eral timer parameters Table 19 9 shows its memory map Table 19 9 RISC Timer Table Parameter RAM Memory Map Offset 1 Name Width Description 0x00 TM_BASE Hword RISC timer table base address The actual timers are a small block of memory in the dual port RAM TM_BASE is the offset from the beginning of the dual port RAM where that block of memory resides Four bytes must be reserved at the TM_BASE for e...

Page 562: ...Word RISC timer internal count Tick counter that the CP updates after each tick or after the timer table is scanned It is updated if the CPÕs internal timer is enabled regardless of whether any of the 16 timers are enabled and it can be used to track the number of ticks the CP receives and responds to Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field V R PWM Ñ Timer Number Bit 16 17 18 19 20 21 22 2...

Page 563: ...erÕs RTMR bit is set the timerÕs RTER interrupt is enabled If an RTMR bit is cleared the corresponding interrupt in the RTER is masked The RISC timer table bit in the CPM interrupt mask register CIMR RTT described in Section 35 5 3 ÒCPM Interrupt Mask Register Ó acts as a global RISC timer interrupt mask Clearing CIMR RTT masks all RISC timer interrupts regardless of RTMR 19 7 5 PWM Mode Designate...

Page 564: ...timer NÐ1 to save space 3 Clear TM_CNT to show how many ticks have elapsed since the CP internal timer was enabled optional 4 Clear the RTER if it is not already cleared Writing 0xFFFF clears this register 5 ConÞgure the RTMR to enable the timers that need to generate interrupts A one enables interrupts 6 Set CIMR RTT to generate interrupts to the system The CPIC may require initialization not men...

Page 565: ...er it times out 8 Write 0x0851 to the CPCR to issue SET TIMER 9 Set RCCR TIME to start RISC timer table scanning 19 7 7 RISC Timer Interrupt Handling The following sequence shows what normally occurs within an interrupt handler for the RISC timer table 1 Once an interrupt occurs read the RTER to see which timers have caused interrupts The RISC timer event bits are usually cleared at this time 2 Is...

Page 566: ...hould be free running and have a timeout of 65 536 5 After a few hours of operation compare the general purpose timer to the current count of RISC timer 15 If the difference between them exceeds two ticks the CP has during some scan tick interval exceeded the 96 utilization level Note that when comparing timer counts the general purpose timers are up counters while RISC timers are down counters ...

Page 567: ...he two physical SDMA channels 20 1 SDMA Channels Data from the SCCs SMCs SPI and I2C can be routed to external memory path 1 or the internal dual port RAM path 2 as shown in Figure 20 1 On a path 1 access the SDMA channel must acquire both the U bus and the external system bus On a path 2 access the data transfer occurs only on the U bus independent of the external system bus unless the SIU is con...

Page 568: ...et in the CPM command register CPCR see Section 19 5 2 ÒCP Command Register CPCR Ó 20 1 2 U Bus Arbitration and the SDMA Channels The SDMA channels I cache D cache and SIU all contend for the U bus as internal masters with their relative priorities determined by an arbitration ID The user can adjust the SDMA bus arbitration priority but the other internal masters have Þxed arbitration IDs see Sect...

Page 569: ...overhead unless an external device is bus master Figure 20 2 shows an SDMA stealing a cycle from an internal bus master Figure 20 2 SDMA U Bus Arbitration Cycle Steal 20 2 SDMA Registers All SDMA channels share one conÞguration register SDCR a status register SDSR a mask register SDMR and a read only address register SDAR The conÞguration of each serial controller also affects their dedicated SDMA...

Page 570: ... Addr IMMR 0x032 Figure 20 3 SDMA Configuration Register SDCR Table 20 2 SDCR Bit Settings Bits Name Description 0Ð16 Ñ Reserved Should be cleared 17 FRZ Freeze Recognize or ignore the freeze signal If conÞgured to respond to the freeze signal the SDMA controller negates BR until freeze is negated or a reset occurs 0 SDMA channels ignore the freeze signal 1 SDMA channels respond to a freeze on the...

Page 571: ...onto the bus and then written to the destination Dual address transfers can take several bus cycles depending on the peripheralÕs port size In contrast single address ßy by IDMA bypasses internal storage transferring data directly between memory and a peripheral in a single bus cycle See Section 20 3 8 ÒIDMA TransfersÑDual Address and Single Address Ó The IDMA controller supports two buffer handli...

Page 572: ...MA handshaking for cycle steal and burst transfers Two buffer handling modesÑauto buffering and buffer chaining Optimized low overhead single buffer mode for peripheral to memory transfers on IDMA1 The MPC860Õs chip select and wait state generation logic can be used with IDMA 20 3 2 IDMA Parameter RAM Both IDMA channels have a dedicated portion of dual port RAM for channel parameters Table 20 4 sh...

Page 573: ... DCMR S D 0b0x 0x0C IBPTR Hword Current IDMA BD pointer If the IDMA channel is idle IBPTR points to the next valid BD in the table After a reset or when the end wrap bit of the BD table is reached the CP wraps IBPTR back to IBASE 0x0E WRITE_SP Hword Internal use 0x10 S_BYTE_C Word Internal source byte count 0x14 D_BYTE_C Word Internal destination byte count 0x18 S_STATE Word Internal state 0x1C IT...

Page 574: ...y address alignment and the amount of data remaining to be transferred 00 Word length 01 Half word length 10 Byte length 11 Reserved Note that the memory port size is transparent to the IDMA The SIU emulates a 32 bit port size regardless of the actual memory port size 13Ð14 S D Source destination DeÞnes the source and destinationÑmemory or peripheral For memory accesses the CP automatically increm...

Page 575: ... together in contiguous dual port RAM to form a standard BD table see Figure 20 7 Figure 20 7 IDMAx ChannelÕs BD Table An IDMA descriptor breaks down as follows The half word at offset 0 is the status and control Þeld The byte at offset 2 is the destination function code register DFCR See Section 20 3 4 1 ÒFunction Code RegistersÑSFCR and DFCR Ó 6 DONE Buffer chain done Indicates IDMA transfer ter...

Page 576: ...ure 20 8 shows the descriptor structure Table 20 7 describes an IDMA descriptorÕs status and control Þeld Offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0x00 V Ñ W I L Ñ CM Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ 0x02 DFCR SFCR 0x04 Buffer Length 0x06 0x08 Source Buffer Pointer 0x0A 0x0C Destination Buffer Pointer 0x0E Figure 20 8 IDMA Buffer Descriptor Structure Table 20 7 IDMA BD Status and Control Bits Bits Name Descr...

Page 577: ... ÒAuto Buffering and Buffer Chaining Ó 0 Normal mode buffer chaining The CP clears the V bit after this descriptor is processed 1 Continuous mode auto buffering The CP does not clear the V bit after this descriptor is processed 7Ð15 Ñ Reserved Bit 0 1 2 3 4 5 6 7 Field Ñ BO AT 1Ð3 Addr DFCR is at offset 0x02 SFCR is at offset 0x03 Figure 20 9 Function Code RegistersÑSFCR and DFCR Table 20 8 SFCR a...

Page 578: ...o mark the last BD of a chain When the CPM completes a chain it ßags IDSR DONE triggering a maskable interrupt to the core The I bit individual BD interrupt behavior is independent of the L bitÑthe user may disable individual BD interrupts and or mask them for multi buffer chains 20 3 5 IDMA CP Commands The core issues the following IDMA commands to the CP INIT IDMAÑThe CPM resets the IDMA interna...

Page 579: ... corresponding PCSO DREQ suspends the IDMA channel transfer A transfer in progress will be completed before the bus is released No further bus cycles are started while PCSO DREQ remains cleared During channel suspension the core can access IDMA internal registers to determine the status of the channel or to alter parameters If PCSO DREQ is set again while a transfer request is pending the channel ...

Page 580: ...nel bandwidth for devices requiring high transfer rates For external devices that generate a pulsed transfer signal for each data operand edge sensitive requests should be used 20 3 7 2 1 Level Sensitive Requests Setting RCCR DRnM makes the corresponding IDMA channel level sensitive to requests DREQ is sampled at rising edge of the clock The device requests service by asserting DREQ and leaving it...

Page 581: ...f the bus cycle For memory reads SAPR is automatically incremented by 1 2 4 or 16 depending on the address and size information speciÞed by DCMR See Section 20 3 2 ÒIDMA Parameter RAM Ó and Section 20 3 3 1 ÒDMA Channel Mode Registers DCMR Ó Dual address destination writeÑThe data in internal storage is written to the peripheral or memory governed by the address in DAPR the address type in DFCR an...

Page 582: ...es like a normal read bus cycle The SAPR is incremented by 1 2 or 4 according to the programming of DCMR SIZE The destination device is controlled by the IDMA handshake signals DREQ and SDACK Asserting SDACK provides write control to the destination device Figure 20 10 and Figure 20 11 show the transaction timing diagrams for asynchronous and synchronous single address peripheral writes See Sectio...

Page 583: ...ce requests service from the IDMA channel IDMA asserts SDACK to allow the source device to drive data onto the data bus The data is written to the memory address in DAPR the address type in DFCR and the size in DCMR The data bus is three stated for this write cycle The DAPR is incremented by 1 2 or 4 according to the programming of DCMR SIZE See Section 20 3 7 ÒIDMA Interface SignalsÑDREQ and SDAC...

Page 584: ...etting RCCR EIE the CPM external interrupt enable bit see Section 19 5 1 ÒRISC Controller ConÞguration Register RCCR Ó Note that the CPM external interrupt always refers to a special request to the CPM not to the core 1 From IDMA1 base IMMR 0x3CC0 Table 20 9 Single Buffer Mode IDMA1 Parameter RAM Map Offset1 Name Width Description 0x00 BAPR Word Buffer pointer Contains the destination buffer memor...

Page 585: ... 7 8 9 10 11 12 13 14 15 Field 1 Ñ BO AT 1Ð3 STR Ñ BPR Reset 0000_0000_0000_0000 R W R W Addr IDMA1 Base 0x08 Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field Ñ Reset 0000_0000_0000_0000 R W R W Addr IDMA1 Base 0x0A Figure 20 13 IDMA Channel Mode Register DCMR Single Buffer Mode Table 20 10 DCMR Field Descriptions Single Buffer Mode Bits Name Description 0 Ñ Must be set 1Ð2 Ñ Reserved Sho...

Page 586: ...ode A typical single address burst timing when IDMA1 is in single buffer mode is illustrated in Figure 20 15 The peripheral asserts DREQ0 and waits for SDACK1 to initiate a burst transfer to memory The peripheral must negate DREQ0 before the last beat of the transfer otherwise IDMA assumes that another DMA request is pendingÑDCMR STR will not be clearedÑand immediately initiates another transfer I...

Page 587: ...le Monitor the AT signals of the SDMA channels for the user deÞned function code AT0 is always high for a DMA access Monitor SDACK which shows accesses to the peripheral SDACK activates on either the source or destination bus cycles depending on DCMR S D Note that if Ethernet is running this method does not work since SCCs in Ethernet mode also toggle SDACK for SDMA transfers CLKOUT GCLK1 A 0 31 T...

Page 588: ... reset interrupt vector 0x00100 Transfer error acknowledge TEA ÑWhen a fatal error occurs during an IDMA bus cycle TEA is used to abort the cycle and systematically terminate the channelÕs operation The IDMA terminates the current bus cycle ßags an error in SDSR and interrupts the core if not masked by SDMR The IDMA waits for the CPM to reset before starting any new bus cycles Note that data read ...

Page 589: ... accomplished through a set of TDM pins and a time slot assigner TSA Two independent TDM channels TDMa and TDMb are available The user programs the TSA to route data from the TDM data stream to and from the SCCs and SMCs The TSA also provides external strobe signals L1ST1Ð4 which can be used to enable external devices such as codecs to insert or take data from the TDM data stream An external frame...

Page 590: ... Time Slot Assigner R clocks T clocks R clocks T clocks R sync T sync TDM a b Pins Strobes U Bus Route SI RAM Tx Rx RAM Control Mode Register TDM a b Tx Rx Tx Rx Command Register Status Register Clock Route MUX SMC1 Pins SMC1 Non multiplexed Serial Interface NMSI MUX SMC2 Pins SMC2 MUX SCC1 Pins SCC1 MUX SCC2 Pins SCC2 MUX SCC3 Pins SCC3 MUX SCC4 Pins SCC4 TIMERS ...

Page 591: ... clock output pins Bit or byte resolution in routing masking and strobe selection Supports frames up to 8 192 bits long Internal routing and strobe selection can be programmed dynamically Supports automatic echo and loopback modes for each TDM channel The NMSI is discussed in Section 21 3 ÒNMSI ConÞguration Ó Its main features are as follows Each SCC and SMC can be programmed independently to work...

Page 592: ...ons of the received data frame from the TDM pins to the target SCCs and SMCs while the target SCC or SMC handles the received data in the actual protocol In its simplest mode the TSA identiÞes both Rx and Tx frames using one sync pulse and a single clock signal provided by the user externally This mode can be enhanced to allow independent routing of Tx and Rx data on the TDM channel The user deÞne...

Page 593: ...DM Example Ð Unique Routing Slot 1 SCC2 Slot 2 SMC1 TDM Tx TDM Rx 1 TDM Clk 1 TDM Sync SMC1 SCC2 TDM TSA Even More ComplexTDM Example Ð MultipleTime Slots per Channel with Varying Sizes ofTime Slots SCC2 SMC1 SCC2 SCC2 NOTE The two shaded areas of SCC2 Rx are received as one high speed data stream by the SCC2 and stored together in the same data buffers TDM Tx TDM Rx TDM Tx Clk TDM Tx Sync SMC1 SC...

Page 594: ...support the multiplexed interface or for enabling disabling three state I O buffers in a multi transmitter system Note that the open drain option on the TXDx pins to support multiple transmitters is programmed in the parallel I O block see Chapter 34 ÒParallel I O Ports Ó The strobes can also generate output waveforms for such applications as stepper motor control The TSA routing is programmed in ...

Page 595: ...outes the SI loopback mode does more than the individual SCC loopback Programming echo and loopback modes are programmed in SIMODE SDMx see Section 21 2 4 2 ÒSI Mode Register SIMODE Ó Loopback mode can also be programmed on a time slot basis in an individual SI RAM entry see Section 21 2 3 7 ÒProgramming the SI RAM Ó Note that loopback operation requires that the receive and transmit sections of t...

Page 596: ...I Global Mode Register SIGMR Ó Once the connections are made the exact routing is determined in the SI RAM See Figure 21 4 Figure 21 4 Enabling Connections through the SI 21 2 3 SI RAM The 512 byte SI RAM contains the SCC and SMC routing information for the TDM channels The SI RAM totals 128 32 bit entriesÑ64 entries each for receive and transmit routing Representing one time slot an entry control...

Page 597: ...alized and disabled Also note that the SI RAM is uninitialized after power onÑthe core should program them before enabling the TDM channels 21 2 3 1 Disabling and Reenabling the TSA The following steps must be taken any time the TSA is disabled These steps also apply to changing the SI routing when the TSA is conÞgured for static frames 1 SCC and SMC connections to the TSA must be disabled 2 The S...

Page 598: ... into the shadow RAM Setting the channelsÕ change shadow RAM bits SICMR CSRRx CSRTx in the SI command register tells the SI to activate the shadow RAM deactivating the current route RAM when the next frame sync arrives The SI signals the user by clearing SICMR CSRRx CSRTx when the swap takes effect These steps can be repeated with the former current route RAM always becoming the new shadow RAM and...

Page 599: ...hen using both TDMs with dynamic changes as in Figure 21 7 the initial current route RAM byte addresses are as follows 0Ð63 RXa route 128Ð191 RXb route 256Ð319TXa route 384Ð447 TXb route The shadow RAMs are at addresses 64Ð127 RXa route 192Ð255 RXb route 320Ð383 TXa route 448Ð511TXb route ...

Page 600: ... for the new The SI swaps between Swap the shadow and the Rx and Tx route and sets the second part of the RAM CSRxn 0 current route RAMs 256 319 320 383 384 447 448 511 RAM Address CSRTa 0 CSRRb 0 CSRTb 0 CSRRa 1 CSRTa 1 CSRRb 1 CSRTb 1 CSRRa 0 CSRTa 0 CSRRb 0 CSRTb 0 L1TCLKb L1TSYNCb 16 TXb Shadow 16 TXa 16 TXb Route Route Framing Signals L1TCLKa L1TSYNCa 16 TXa Shadow RAM Address CSRxn L1RCLKb L...

Page 601: ...ntries apiece for Tx and Rx data strobe routing as shown in Figure 21 9 One partition is the current route RAM the other is shadow RAM that can be safely reprogrammed After programming the shadow RAM the user sets SICMR CSRx When the next frame sync arrives the SI swaps the current route RAM with the shadow RAM Figure 21 9 SI RAM Partitioning Using Two TDMs with Dynamic Frames 0 SI RAM Address 32 ...

Page 602: ...rce 2Ð5 SSELn Strobe select 1Ð4 The four strobes L1ST 1Ð4 can be assigned to the Rx or the Tx RAM and asserted negated in sync with the corresponding L1RCLKx or L1TCLKx Using active high logic each SSELn will be the value of the corresponding strobe during this time slot Multiple strobes can be asserted simultaneously A strobe can be conÞgured to remain asserted for multiple consecutive SI RAM ent...

Page 603: ...ming Example This section shows how to program the SI RAM to support the 10 bit IDL bus whose format is shown in Figure 21 26 Here the TSA supports the B1 channel with SCC2 the D channel with SCC3 the Þrst 4 bits of the B2 channel with an external device using a strobe to enable the external device and the last 4 bits of B2 with SMC1 Additionally the TSA marks the D channel with another strobe sig...

Page 604: ...and sync for both sets of SI RAM entries For examples showing register programming see Section 21 2 5 2 ÒProgramming the IDL Interface Ó and Section 21 2 6 3 ÒGCI Interface SCIT Mode Programming Example Ó 21 2 4 The SI Registers The following sections describe the SI registers 21 2 4 1 SI Global Mode Register SIGMR The SI global mode register SIGMR shown in Figure 21 12 deÞnes the SI RAM division ...

Page 605: ...ns Bits Name Description 0Ð3 Ñ Reserved should be cleared 4 ENb Enable TDMb 0 TDMb is disabled SI RAM and TDM routing are in a state of reset all other SI functions still operate 1 TDMb is enabled 5 ENa Enable TDMa 0 TDMa is disabled SI RAM and TDM routing are in a state of reset all other SI functions still operate 1 TDMa is enabled 6Ð7 RDM RAM division mode DeÞnes the SI RAM partitioning based o...

Page 606: ...e bank of clocks However Tx and Rx clocks must be common when connected to the NMSI 000 BRG1 001 BRG2 010 BRG3 011 BRG4 100 CLK1 for SMC1 CLK6 for SMC2 101 CLK2 for SMC1 CLK6 for SMC2 110 CLK3 for SMC1 CLK7 for SMC2 111 CLK4 for SMC1 CLK8 for SMC2 4Ð5 20Ð21 SDMx SI diagnostic mode for TDMa b In modes 01 10 and 11 Rx and Tx clocks should be common 00 Normal operation 01 Automatic echo The TDM trans...

Page 607: ... activation see Section 21 2 6 1 ÒGCI Activation Deactivation Ó 11 27 CEx Clock edge for TDMa b When DSCx 0 0 Data is sent on the rising clock edge and received on the falling edge use for IDL and GCI 1 Data is sent on the falling edge of the clock and received on the rising edge When DSCx 1 0 Data is sent on the rising clock edge and received on the rising edge 1 Data is sent on the falling edge ...

Page 608: ...smit frame sync delay for TDMa b Determines the delay between the Tx sync and the Þrst bit of the Tx frame If CRTx is set the Rx sync is used as the common sync and the TFSDx bits refer to this common sync 00 No bit delay The Þrst bit of the frame is sent on the same clock as the sync 01 1 bit delay 10 2 bit delay 11 3 bit delay Table 21 5 SIMODE Field Descriptions Continued Bits Name Description ...

Page 609: ...ffect when DSC 1 Figure 21 18 shows SIMODE FE behavior with SIMODE CE set and no frame sync delay L1TxD Rx Sampled Here L1ST L1SYNC L1SYNC L1CLK Bit 0 On Bit 0 L1ST Driven from Clock High for Both FE Settings xFSD 1 FE 0 FE 1 CE 1 L1TXD Rx Sampled Here L1ST L1SYNC L1SYNC L1CLK Bit 0 On Bit 0 L1ST is Driven from Clock Low FE 0 FE 1 CE 0 in Both the FE Settings ...

Page 610: ...MODE xFSD are zero L1TXD L1ST L1SYNC L1CLK Bit 0 On Bit 0 xFSD 0 FE 0 CE 1 The L1ST is Driven from Sync Data is Driven from Clock Low L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 0 L1ST is Driven from Clock High L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 1 Both Data Bit 0 and L1ST are Driven from Sync Rx Sampled Here Rx Sampled Here L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 1 L1ST and Data Bit 0 is Driven from Clock Lo...

Page 611: ...ank of clock pins The SICR also connects the SCCs to the TSA and enables the grant mechanism chosen in SIMODE L1TXD L1ST L1SYNC L1CLK Bit 0 On Bit 0 xFSD 0 FE 1 CE 0 The L1ST is Driven from Sync Data is Driven From Clock High L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 1 L1ST is Driven from Clock Low L1TXD L1ST L1SYNC Bit 0 On Bit 0 FE 0 Both the Data and L1ST from Sync when Asserted during Clock High Rx ...

Page 612: ...me Description 0 8 16 24 GRx Grant support of SCCx 0 Transmitter does not support the grant mechanism The grant is always asserted internally 1 Transmitter supports the grant mechanism as determined by SIMODE GMx 1 9 17 25 SCx SCCx connection 0 SCCx is not connected to the TSA It is either connected directly to the NMSI pins or is not used The choice of general purpose I O port versus SCCx functio...

Page 613: ...ared by the SI when the swap completes 0 The shadow RAM is invalid The shadow RAM can be written to program a new routing 1 The shadow RAM is valid The SI swaps the RAMs taking the new routing from the shadow RAM 1 3 CSRT 4Ð7 Ñ Reserved should be cleared Bit 0 1 2 3 4 5 6 7 Field CRORa CROTa CRORb CROTb Ñ Reset 0 R W R Addr OxAE6 Figure 21 22 SI Status Register SISTR Table 21 8 SISTR Field Descrip...

Page 614: ...soon as the next SI RAM entry begins processing The value of SIRP changes on serial clock transitions Before acting on the information in this register perform two reads to verify the same value is returned One of the four strobes can be connected externally to an interrupt pin to generate an interrupt on a particular SI RAM entry to start or stop TSA execution The pointers in SIRP indicate the SI...

Page 615: ...r TbPTR is used depends on which portion of the Tx RAM is active If VRa 1 RaPTR points to the active RXa entry The Rx address block is 0Ð127 SISTR CRORa 0 If VRb 1 RbPTR points to the active RXa entry The Rx address block is 128Ð255 SISTR CRORa 1 If VTa 1 TaPTR points to the active TXa entry The Tx address block is 256Ð383 SISTR CROTa 0 If VTb 1 TbPTR points to the active TXa entry The Tx address ...

Page 616: ...own in Figure 21 24 Figure 21 24 Dual IDL Bus Application Example 21 2 5 1 ISDN Terminal Adaptor Application An example IDL application is the ISDN terminal adaptor shown in Figure 21 25 In such an application the IDL interface connects the 2B D channels between the MPC860 CODEC and S T transceiver An SCC is conÞgured in HDLC mode to handle the D channel Another SCC is used to rate adapt the termi...

Page 617: ...signals that may be present L1TXDxÑIDL transmit data Output from the MPC860 Valid only for bits supported by the IDL otherwise three stated L1RQxÑIDL request permission to transmit on the D channel Output from the MPC860 on L1RQx L1GRxÑIDL grant permission to transmit on the D channel Input to the MPC860 on L1TSYNCx The basic rate IDL bus has three channels B1 is a 64 Kbps bearer channel B2 is a 6...

Page 618: ...ut that supports an external device The MPC860 supports the request grant method for contention detection on the D channel of the IDL basic rate and when the MPC860 has data to send on the D channel it asserts L1RQx The physical layer device monitors the physical layer bus for activity on the D channel and indicates that the channel is free by asserting L1GRx The MPC860 samples L1GRx when the IDL ...

Page 619: ...L frame structure by programming SIMODE xFSD to have a 1 bit delay from frame sync to data SIMODE FE to sample the sync on the falling edge and SIMODE CE to transmit on the rising edge of the clock Program L1TXDx to be three stated when inactive via the parallel I O open drain register To support the D channel set the appropriate SICR GR bit and program the RAM entry to route data to the chosen SC...

Page 620: ...lso supports the D channel access control in S T interface terminals by using the command indication C I channel The GCI bus consists of four signalsÑtwo data lines a clock and a frame synchronization line Usually an 8 KHz frame structure deÞnes the various channels within the 256 Kbps data rate The MPC860 supports two independent GCI buses each with independent receive and transmit sections With ...

Page 621: ... MPC860 can support any channel of the GCI bus in the primary rate by modifying the SI RAM programming The GCI supports the CCITT I 460 recommendation as a method for data rate adaptation since it can access each bit of the GCI separately The current route RAM speciÞes which bits are supported by the interface and serial controller The receiver accepts only the bits that are enabled by the SI RAM ...

Page 622: ...ata clock as one half the input clock rate Also if the receive and transmit sections are used to interface with the same GCI bus set SIMODE CRTx to internally connect the Rx clock and sync signals to the SI RAM transmit section Then deÞne the GCI frame routing and strobe select using the SI RAM When the receive and transmit sections use the same clock and sync signals the sections should use the s...

Page 623: ...Da to be an open drain output 5 PAPAR 7Ð9 0b111 ConÞgure L1TXDa L1RXDa and L1RCLKa 6 PADIR 7Ð9 0b011 ConÞgure L1TXDa L1RXDa and L1RCLKa 7 If the 1 GCI data clock is required conÞgure L1CLKOa as an output by setting PBPAR 20 and PBDIR 20 8 PCPAR 4 1 ConÞgure L1RSYNCa 9 SIGMR 0x04 Enable TDMa one static TDM 10 SICMR is not used 11 SISTR and SIRP do not need to be read but can be used for debugging w...

Page 624: ...me clock rate they can share the same pin leaving other pins available other functions and minimizing the potential skew between multiple clock sources The baud rate generators also make their clocks available to external logic regardless of whether the BRGs are being used by an SCC or SMC The BRGOn pins are multiplexed with other functions so all BRGOn pins may not always be available See Chapter...

Page 625: ... CTS1 CD1 The SCC2 in NMSI mode has its own set of modem control signals TXD2 RXD2 TCLK2 BRG1ÐBRG4 CLK1ÐCLK4 RCLK2 BRG1ÐBRG4 CLK1ÐCLK4 RTS2 CTS2 CD2 SMC1 SMC2 SCC2 Rx SCC2 Tx BRG1 BRG2 BRG3 BRG4 CLK1 CLK2 SMCLK1 RCLK1 TCLK1 SMCLK2 RCLK2 TCLK2 BRGO1 BRGO2 BRGO3 BRGO4 Bank of Clocks Selection Logic SCC clock source selected in SICR SMC clock source selected in SIMODE CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 SC...

Page 626: ...signals TXD4 RXD4 TCLK4 BRG1ÐBRG4 CLK5ÐCLK8 RCLK4 BRG1ÐBRG4 CLK5ÐCLK8 RTS4 CTS4 CD4 The SMC1 in NMSI mode has its own set of modem control signals SMTXD1 SMRXD1 SMCLK1 BRG1ÐBRG4 CLK1ÐCLK4 SMSYN1 used only in the totally transparent protocol The SMC2 in NMSI mode has its own set of modem control signals SMTXD2 SMRXD2 SMCLK2 BRG1ÐBRG4 CLK5ÐCLK8 SMSYN2 used only in the totally transparent protocol Un...

Page 627: ...tobaud support option Each BRG output can be routed to a pin BRGOn Figure 21 29 shows a baud rate generator Figure 21 29 Baud Rate Generator BRG Block Diagram The BRG clock source can be BRGCLK CLK2 or CLK6 selected in BRGCn EXTC The BRGCLK is generated in the MPC860 clock synthesizer as a source speciÞcally for the BRGs the SPI and the I2 C internal baud rate generator Alternatively the CLK2 and ...

Page 628: ...0 is cleared at reset A reset disables the BRG and drives the BRGO output clock high The BRGC can be written at any time with no need to disable the SCCs or external devices that are connected to BRGO ConÞguration changes occur at the end of the next BRG clock cycle no spikes occur on the BRGO output clock BRGC can be changed on the ßy however two changes should not occur within a time equal to tw...

Page 629: ...AÕ Software should then check for other characters such as ÔtÕ or ÔTÕ and program the preferred parity mode in the UARTÕs protocol speciÞc mode register PSMR 15 EN Enable BRG count Used to dynamically stop the BRG from countingÑuseful for low power modes 0 Stop all clocks to the BRG 1 Enable clocks to the BRG 16Ð17 EXTC External clock source Selects the BRG input clock 00 BRGCLK internal clock gen...

Page 630: ...ing when using the SCC as a UART Rates of 8 and 32 are also available Assuming 16 oversampling is chosen in the UART the maximum data rate is 25 MHz 16 1 5625 Mbps Keeping the above in mind use the following formula to calculate the bit rate based on a particular BRG conÞguration for a UART async baud rate BRGCLK or CLK2 or CLK6 1 or 16 according to BRGCx DIV16 clock divider 1 8 16 or 32 according...

Page 631: ... CLK6 1 or 16 according to BRGCx DIV16 clock divider 1 For example to get a rate of 64 Kbps the system clock can be 24 96 MHz DIV16 0 and the clock divider 389 38400 0 32 37879 0 40 38109 0 39 38400 57600 0 21 56818 0 26 57870 0 26 56889 115200 0 10 113636 0 13 111607 0 12 118154 Table 21 14 Typical Baud Rates for Asynchronous Communication Continued Baud Rate System Frequency 20 MHz 25 MHz 24 576...

Page 632: ...21 44 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 633: ...ribed in Chapter 23 ÒSCC UART Mode Ó HDLC and HDLC bus described in Chapter 24 ÒSCC HDLC Mode Ó IrDA or asynchronous HDLC described in Chapter 26 ÒSCCAsynchronous HDLC Mode and IrDA Ó AppleTalk LocalTalk described in Chapter 25 ÒSCC AppleTalk Mode Ó BISYNC described in Chapter 27 ÒSCC BISYNC Mode Ó Transparent described in Chapter 29 ÒSCC Transparent Mode Ó Ethernet described in Chapter 28 ÒSCC Et...

Page 634: ...tware and additional parallel I O lines can be used to support additional handshake signals Figure 22 1 shows the SCC block diagram Figure 22 1 SCC Block Diagram 22 1 Features The following is a list of the main SCC features Performance Þgures assume a 25 MHz system clock Implements HDLC SDLC HDLC bus asynchronous HDLC BISYNC synchronous start stop asynchronous start stop UART AppleTalk LocalTalk ...

Page 635: ...ti buffer data structure for receive and send the number of buffer descriptors BDs is limited only by the size of the internal dual port RAMÑ8 bytes per BD Deep FIFOs The SCC1 transmit and receive FIFOs are 32 bytes each SCC2ÐSCC4 FIFOs are 16 bytes each Transmit on demand feature decreases time to frame transmission transmit latency Low FIFO latency option for send and receive in character orient...

Page 636: ...s used to reduce signal noise 0 No glitch detection Clear GDE if the external serial clock exceeds the limits of glitch detection logic 6 25 MHz assuming a 25 MHz system clock if an internal BRG supplies the SCC clock or if external clocks are used and glitch detection matters less than power consumption 1 Glitches can be detected and reported as maskable interrupts in the SCC event register SCCE ...

Page 637: ...hich time the transfer begins Useful for connecting MPC860 in transparent mode since the RTS of one MPC860 can connect directly to the CD CTS of another 25 TFL Transmit FIFO length 0 Normal operation The SCC1 transmit FIFO is 32 bytes SCC2ÐSCC4 Tx FIFOs are 16 bytes each 1 The Tx FIFO is 1 byte This option is used with character oriented protocols such as UART to ensure a minimum FIFO latency at t...

Page 638: ...BISYNC The receiver synchronizes on a 16 bit sync pattern stored in the DSR 30 RTSM RTS mode Determines whether ßags or idles are to be sent Can be changed on the ßy 0 Send idles between frames as deÞned by the protocol and the TEND bit RTS is negated between frames default 1 Send ßags syncs between frames according to the protocol RTS is always asserted whenever the SCC is enabled 31 RSYN Receive...

Page 639: ... data setup time for the external transceiver 4Ð5 TSNC Transmit sense Determines the amount of time the internal carrier sense signal stays active after the last transition on RXD indicating that the line is free For instance AppleTalk can use TSNC to avoid a spurious CS changed SCCE DCC interrupt that would otherwise occur during the frame sync sequence before the opening ßags If RDCR is conÞgure...

Page 640: ...Ð15 TDCR Transmitter receiver DPLL clock rate If the DPLL is not used choose 1 mode except in asynchronous UART mode where 8 16 or 32 must be chosen TDCR should match RDCR in most applications to allow the transmitter and receiver to use the same clock source If an application uses the DPLL the selection of TDCR RDCR depends on the encoding decoding If communication is synchronous select 1 FM0 FM1...

Page 641: ... requirements For TDM operation the diagnostic mode is selected by SIMODE SDMx see Section 21 2 4 2 ÒSI Mode Register SIMODE Ó 26 ENR Enable receive Enables the receiver hardware state machine for this SCC 0 The receiver is disabled and data in the Rx FIFO is lost If ENR is cleared during reception the receiver aborts the current character 1 The receiver is enabled ENR can be set or cleared regard...

Page 642: ...ÑAt reset DSR defaults to 0x7E7E two HDLC ßags so it does not need to be written Figure 22 4 shows the sync Þelds 22 1 4 Transmit on Demand Register TODR In normal operation if no frame is being sent by an SCC the CP periodically polls the R bit of the next TxBD to see if a new frame buffer is requested Depending on the SCC conÞguration this polling occurs every 8Ð32 serial Tx clocks The transmit ...

Page 643: ...tatus bits after the buffer is sent or received The half word at offset 0x2 data length holds the number of bytes sent or received Ñ For an RxBD this is the number of bytes the controller writes into the buffer The CP writes the length after received data is placed into the associated buffer and the buffer closed In frame based protocols this Þeld contains the total frame length including CRC byte...

Page 644: ...ge can reside in as many buffers as necessary Each buffer has a maximum length of 65 535 bytes The CP does not assume that all buffers of a single frame are currently linked to the BD table The CP does assume however that the unlinked buffers are provided by the core in time to be sent or received otherwise an error condition is reportedÑan underrun error when sending and a busy error when receivi...

Page 645: ...rocessing and does not skip BDs that are not ready When the CP sees a BDÕs W bit wrap set it returns to the start of the BD table after this last BD of the table is processed The CP clears R not ready after using a TxBD which keeps it from being retransmitted before it is conÞrmed by the core However some protocols support a continuous mode CM for which R is not cleared always ready The CP uses Rx...

Page 646: ...only when the transmitter is disabledÑafter a STOP TRANSMIT command and before a RESTART TRANSMIT command or after the buffer frame Þnishes transmitting after a GRACEFUL STOP TRANSMIT command and before a RESTART TRANSMIT command Rx parameter RAM can be written only when the receiver is disabled Note the CLOSE RX BD command does not stop reception but it does allow the user to extract data from a ...

Page 647: ...essed 0x10 RBPTR Hword Current RxBD pointer Points to the current BD being processed or to the next BD the receiver uses when it is idling After reset or when the end of the BD table is reached the CP initializes RBPTR to the value in the RBASE Although most applications do not need to write RBPTR it can be modiÞed when the receiver is disabled or when no Rx buffer is in use 0x12 Hword Rx internal...

Page 648: ...in the CPM interrupt conÞguration register CICR To allow interrupt handling for SCC speciÞc events further event mask and status registers are provided within each SCCÕs internal memory map area see Table 22 6 Since interrupt events are protocol dependent event descriptions are found in the speciÞc protocol chapters Bit 0 1 2 3 4 5 6 7 Field Ñ BO AT 1Ð3 Reset 0000_0000_0000_0000 R W R W Addr SCCx ...

Page 649: ...r SDCR RAID Þeld to 0b01 U bus arbitration priority level 5 3 ConÞgure the parallel I O registers to enable RTS CTS and CD if these signals are required Table 22 6 SCCx Event Mask and Status Registers Register IMMR Offset Description SCCEx 0xA10 SCC1 0xA30 SCC2 0xA50 SCC3 0xA70 SCC4 SCC event register This 16 bit register reports events recognized by any of the SCCs When an event is recognized the...

Page 650: ... reenabled after any dynamic change to its parallel I O ports or serial channel physical interface conÞguration A full reset can also be implemented using CPCR RST 22 3 4 Controlling SCC Timing with RTS CTS and CD When GSMR_L DIAG is programmed to normal operation CD and CTS are controlled by the SCC In the following subsections it is assumed that GSMR_L TCI is zero implying normal transmit clock ...

Page 651: ...a negating it during frame transmission causes a CTS lost error Negating CTS forces RTS high and Tx data to become idle If GSMR_H CTSS is zero the SCC must sample CTS before a CTS lost is recognized otherwise the negation of CTS immediately causes the CTS lost condition See Figure 22 11 1 A frame includes opening and closing ßags and syncs if present in the protocol TCLK TXD Last Bit of Frame Data...

Page 652: ...sing Rx clock edge before data is received If GSMR_H CDS is 1 CD transitions cause data to be immediately gated into the receiver 1 GSMR_H CTSS 0 CTSP 0 or no CTS lost can occur TCLK TXD First Bit of Frame Data NOTE CTS Sampled Low Here 1 GSMR_H CTSS 1 CTSP 0 or no CTS lost can occur TCLK First Bit of Frame Data NOTE CTS Sampled High Here Data Forced High RTS Forced High Data Forced High RTS Force...

Page 653: ...addition the UART protocol has an option for CTS ßow control as described in Chapter 23 ÒSCC UART Mode Ó If CTS is already asserted when RTS is asserted transmission begins in two additional bit times If CTS is not already asserted when RTS is asserted and GSMR_H CTSS 0 transmission begins in three additional bit times If CTS is not already asserted when RTS is asserted and GSMR_H CTSS 1 transmiss...

Page 654: ... bypassed by selecting 1x mode for GSMR_L RDCR TDCR If the DPLL is bypassed only NRZ or NRZI encodings are available The DPLL must not be used when an SCC is programmed to Ethernet and is optional for other protocols Figure 22 13 shows the DPLL receiver block Figure 22 14 shows the transmitter block diagram Figure 22 13 DPLL Receiver Block Diagram DPLL HSRCLK RXD RINV TSNC EDGE RDCR RENC Receiver ...

Page 655: ...PLL operation While the counter is counting the DPLL watches the incoming data stream for transitions when one is detected the DPLL adjusts the count to produce an output clock that tracks incoming bits The DPLL has a carrier sense signal that indicates when data transfers are on RXD The carrier sense signal asserts as soon as a transition is detected on RXD it negates after the programmed number ...

Page 656: ...erator may be up to 25 MHz on a 25 MHz MPC8560Voyager if the DPLL 8 16 or 32 option is used Note the 1 2 system clock serial clock ratio does not apply when the DPLL is used to recover the clock in the 8 16 or 32 modes Synchronization occurs internally after the DPLL generates the Rx clock Therefore even the fastest DPLL clock generation the 8 option easily meets the required 1 2 ratio clocking li...

Page 657: ...ed A zero is represented by no transition at all FM0 A one is represented by a transition only at the beginning of the bit A zero is represented by a transition at the beginning of the bit and another transition at the center of the bit FM1 A one is represented by a transition at the beginning of the bit and another transition at the center of the bit A zero is represented by a transition only at ...

Page 658: ...d for SCC parameters that cannot be changed dynamically For instance the internal baud rate generators allow on the ßy changes but the DPLL related GSMR does not The steps in the following sections show how to disable reconÞgure and re enable an SCC to ensure that buffers currently in use are properly closed before reconÞguring the SCC and that subsequent data goes to or from new buffers according...

Page 659: ...f the INIT RX PARAMETERS command was not issued in step 2 issue an ENTER HUNT MODE command 4 Set GSMR_L ENR Reception begins using the RxBD pointed to by RBPTR assuming the E bit is set 22 3 7 4 Reset Sequence for an SCC Receiver To reinitialize the SCC receiver to the state it was in after reset follow these steps 1 Clear GSMR_L ENR 2 Make any modiÞcations then issue the INIT RX PARAMETERS comman...

Page 660: ...22 28 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 661: ...the bit value Traditionally the middle 3 of the 16 samples are used Two UARTs can communicate using this system if the transmitter and receiver use the same parameters such as the parity scheme and character length When data is not sent a continuous stream of ones is sent idle condition Because the start bit is always a zero the receiver can detect when real data is once again on the line UART spe...

Page 662: ...and protocols an SCC UART controller can communicate with any existing RS 232 type device and provides a serial communications port to other microprocessors and terminals either locally or via modems The independent transmit and receive sections whose operations are asynchronous with the core send data from memory either internal or external to TXD and receive data from RXD The UART controller sup...

Page 663: ...fter the three middle samples are taken The UART transmit shift register sends outgoing data on TXDx Data is then clocked synchronously with the transmit clock which may have either an internal or external source Characters are sent lsb Þrst Only the data portion of the UART frame is stored in the buffers because start and stop bits are generated and stripped by the SCC A parity bit can be generat...

Page 664: ... when a STOP TRANSMIT command is issued For 8 data bits no parity 1 stop bit and 1 start bit each break character consists of 10 zero bits 0x3E PAREC Hword User initialized 16 bit moduloÐ2 16 counters incremented by the CP PAREC counts received parity errors FRMEC counts received characters with framing errors NOSEC counts received characters with noise errors BRKEC counts break conditions on the ...

Page 665: ...0x3C00 SCC1 or 0x3D00 SCC2 or 0x3E00 SCC3 or 0x3F00 SCC4 0x50 CHARACTER1 Hword Control character 1Ð8 These characters deÞne the Rx control characters on which interrupts can be generated 0x52 CHARACTER2 Hword 0x54 CHARACTER3 Hword 0x56 CHARACTER4 Hword 0x58 CHARACTER5 Hword 0x5A CHARACTER6 Hword 0x5C CHARACTER7 Hword 0x5E CHARACTER8 Hword 0x60 RCCM Hword Receive control character mask Used to mask...

Page 666: ... parameters including the TxBD can be modiÞed TBPTR points to the next TxBD in the table Transmission begins once the R bit of the next BD is set and a RESTART TRANSMIT command is issued RESTART TRANSMIT Enables transmission The controller expects this command after it disables the channel in its PSMR after a STOP TRANSMIT command after a GRACEFUL STOP TRANSMIT command or after a transmitter error...

Page 667: ...leared The incoming address is checked against UADDR1 and UADDR2 When a match occurs RxBD AM indicates whether UADDR1 or UADDR2 matched Manual multidrop modeÑThe controller receives all characters An address character is always written to a new buffer and can be followed by data characters User software performs the address comparison Figure 23 2 Two UART Multidrop Configurations 23 9 Receiving Co...

Page 668: ...2 13 14 15 0x50 E R Ñ CHARACTER1 0x52 E R Ñ CHARACTER2 0x5E E R Ñ CHARACTER8 0x60 1 1 Ñ RCCM 0x62 Ñ RCCR 1 From SCCx base address Figure 23 3 Control Character Table RCCM and RCCR Table 23 4 Control Character Table RCCM and RCCR Descriptions Offset Bits Name Description 0x50Ð 0x5E 0 E End of table In tables with eight control characters E is always 0 0 This entry is valid 1 The entry is not valid ...

Page 669: ...ty than the other characters in the transmit buffer but does not preempt characters already in the transmit FIFO This means that the XON or XOFF character may not be sent for eight SCC1 or four SCC2ÐSCC4 character times To reduce this latency set GSMR_H TFL to decrease the FIFO size to one character before enabling the transmitter 0x60 0Ð1 0b11 Must be set Used to mark the end of the control chara...

Page 670: ...r For example for 8 data bits no parity 1 stop bit and 1 start bit a preamble of 10 ones is sent before the Þrst character in the buffer Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ REA I CT Ñ A CHARSEND Reset 0000_0000_0000_0000 R W R W Addr SCC base 0x4E Figure 23 4 Transmit Out of Sequence Register TOSEQ Table 23 5 TOSEQ Field Descriptions Bit Name Description 0Ð1 Ñ Reserved should be clea...

Page 671: ...zation Register DSR Table 23 6 DSR Fields Descriptions Bit Name Description 0 Ñ 0b0 1Ð4 FSB Fractional stop bits For 16 oversampling 1111 Last transmitted stop bit 16 16 Default value after reset 1110 Last transmitted stop bit 15 16 É 1000 Last transmitted stop bit 9 16 0xxx Invalid Do not use For 32 oversampling 1111 Last transmitted stop bit 32 32 Default value after reset 1110 Last transmitted ...

Page 672: ... The channel also increments the parity error counter PAREC In automatic multidrop mode the receiver enters hunt mode immediately Noise A noise error occurs when the three samples of a bit are not identical When this error occurs the channel writes the received character to the buffer proceeds normally but increments the noise error counter NOSEC Note that this error does not occur in synchronous ...

Page 673: ... in synchronous mode and PSMR RZS is set Fractional stop bits are conÞgured in the DSR 0 One stop bit 1 Two stop bits 2Ð3 CL Character length Determines the number of data bits in the character not including optional parity or multidrop address bits If a character is less than 8 bits most signiÞcant bits are received as zeros and are ignored when the character is sent CL can be modiÞed on the ßy 0...

Page 674: ...2 16 is recommended for most applications 1 Synchronous SCC UART controller using 1 clock isochronous UART operation GSMR_L TENC RENC must select NRZ and GSMR_L RDCR TDCR select 1 mode A bit is transferred with each clock and is synchronous to the clock which can be internal or external 9 DRT Disable receiver while transmitting 0 Normal operation 1 While the SCC is sending data the internal RTS di...

Page 675: ...to the next buffer after one of the following occurs A user deÞned control character is received An error occurs during message processing A full receive buffer is detected A MAX_IDL number of consecutive idle characters is received An ENTER HUNT MODE or CLOSE RXBD command is issued An address character is received in multidrop mode The address character is written to the next buffer for a softwar...

Page 676: ...h Pointer 1 XXXX 32 Bit Buffer Pointer E Rx BD 3 Status Length Pointer Byte 1 Byte 2 Byte 8 Buffer Byte 9 Byte 10 Buffer Byte 1 Byte 2 Byte 3 Buffer Byte 4 Error Empty Additional Bytes will be Stored Unless Idle Count Expires MAX_IDL 8 Bytes 8 Bytes 8 Bytes 8 Bytes Characters Received by UART Fourth Character 10 Characters Long Idle Period has Framing Error Present Time Time 5 Characters Buffer Fu...

Page 677: ... Þlled by the CPM indicating the need for the core to process the buffer Setting SCCE RX causes an interrupt if not masked 4 C Control character 0 This buffer does not contain a control character 1 The last byte in this buffer matches a user deÞned control character 5 A Address 0 The buffer contains only data 1 For manual multidrop mode A indicates the Þrst byte of this buffer is an address byte S...

Page 678: ...ed should be cleared 14 OV Overrun Set when a receiver overrun occurs during reception 15 CD Carrier detect lost Set when the carrier detect signal is negated during reception 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 R Ñ W I CR A CM P NS Ñ CT Offset 2 Data Length Offset 4 Tx Buffer Pointer Offset 6 Figure 23 9 SCC UART Transmit Buffer Descriptor TxBD Table 23 11 SCC UART TxBD Status and Cont...

Page 679: ...rmal CTS lost error reporting and three bits of idle are sent between consecutive buffers 5 A Address Valid only in multidrop modeÑautomatic or manual 0 This buffer contains only data 1 This buffer contains address characters All data in this buffer is sent as address characters 6 CM Continuous mode 0 Normal operation The CPM clears R after this BD is closed 1 The CPM does not clear R after this B...

Page 680: ... CCR IDL RX IDL BRKS BRKE IDL CD Break Line Idle 10 Characters RXD CD Characters Received by UART Time Line Idle TXD RTS Characters Transmitted by UART CTS TX CTS CTS Line Idle Line Idle 7 Characters Notes UART SCCE Events 1 The Þrst RX event assumes Rx buffers are 6 bytes each 2 The second IDL event occurs after an all ones character is received 3 The second RX event position is programmable base...

Page 681: ...quence 10 BRKS Break start Set when the Þrst character of a break sequence is received Multiple BRKS events are not received if a long break sequence is received 11 Ñ Reserved should be cleared 12 CCR Control character received and rejected Set when a control character is recognized and stored in the receive control character register RCCR 13 BSY Busy Set when a character is received and discarded...

Page 682: ... Connect the SCC2 to the NMSI Clear SICR SC2 7 Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD tables in dual port RAM Assuming one RxBD at the start of dual port RAM followed by one TxBD write RBASE with 0x0000 and TBASE with 0x0008 8 Write 0x0041 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2 This command updates RBPTR and TBPTR of the serial channel ...

Page 683: ...0 to conÞgure automatic ßow control using CTS 8 bit characters no parity 1 stop bit and asynchronous SCC UART operation 26 Write 0x0002_8034 to GSMR_L2 to enable the transmitter and receiver This ensures that ENT and ENR are enabled last Note that after 16 bytes are sent the transmit buffer is closed Additionally the receive buffer is closed after 16 bytes are received Data received after 16 bytes...

Page 684: ...be cleared When an end of line character is received the current buffer is closed and made available to the core for processing This buffer contains an entire S record that the processor can now check and copy to memory or disk as required XOFF E should be cleared R should be set Whenever the core receives a control character received CCR interrupt and the RCCR contains XOFF the software should im...

Page 685: ...fferent Þelds to specify various access points within one device LAPD also deÞnes a broadcast address Some HDLC type protocols permit addressing beyond 16 bits The 8 or 16 bit control Þeld provides a ßow control number and deÞnes the frame type control or data The exact use and structure of this Þeld depends on the protocol using the frame The length of the data in the data Þeld depends on the fra...

Page 686: ...data from memory and starts sending the frame after sending the minimum number of ßags speciÞed between frames When the end of the current buffer is reached and TxBD L last buffer in frame is set the CRC and closing ßag are appended In HDLC mode the lsb of each octet and the msb of the CRC are sent Þrst Figure 24 1 shows a typical HDLC frame Figure 24 1 HDLC Framing Structure After a closing ßag i...

Page 687: ... E and generates a maskable interrupt if RxBD I is set If the incoming frame is larger than the current buffer the SCC continues receiving using the next BD in the table During reception the SCC checks for frames that are too long using MFLR When the frame ends the CRC Þeld is checked against the recalculated value and written to the buffer RxBD Data Length of the last BD in the HDLC frame contain...

Page 688: ...the SCC reports frame status and frame length in the last RxBD The MFLR is deÞned as all in frame bytes between the opening and closing ßags 0x48 MAX_CNT Hword Maximum length counter A temporary down counter used to track frame length 0x4A RFTHR Hword Received frames threshold Used to reduce potential interrupt overhead when each in a series of short HDLC frames causes an SCCE RXF event Setting RF...

Page 689: ...x7F and stops polling the BDs When not transmitting the channel sends ßags or idles as programmed in the GSMR Note that if PSMR MFF 1 multiple small frames could be ßushed from the Tx FIFO a GRACEFUL STOP TRANSMIT command prevents this GRACEFUL STOP TRANSMIT Stops transmission smoothly Unlike a STOP TRANSMIT command it stops transmission after the current frame is Þnished or immediately if no fram...

Page 690: ...tes each SCC2ÐSCC4 FIFOs are 16 bytes each CTS Lost duringFrame Transmission The channel stops transmitting closes the buffer sets TxBD CT and generates the TXE interrupt if not masked Transmission resumes after a RESTART TRANSMIT command If this error occurs on the Þrst or second buffer of the frame and PSMR RTE 1 the channel resends the frame when CTS is reasserted and no error is reported If co...

Page 691: ...to the last byte rather than the last word of the buffer The lsb of each octet is sent Þrst while the msb of the CRC is sent Þrst CRC The channel writes the received CRC to the buffer closes the buffer sets RxBD CR generates a maskable RXF interrupt and increments the CRC error counter CRCEC After receiving a frame with a CRC error the receiver enters hunt mode An immediate back to back frame is s...

Page 692: ...e with Collision Detection Ó 11 BRM HDLC bus RTS mode Valid only if BUS 1 Otherwise it is ignored 0 Normal RTS operation during HDLC bus mode RTS is asserted on the Þrst bit of the Tx frame and negated after the Þrst collision bit is received 1 Special RTS operation during HDLC bus mode RTS is delayed by one bit with respect to the normal case which helps when the HDLC bus protocol is being run lo...

Page 693: ...tets to the data length Þeld 5 F First in frame 0 Not the Þrst buffer in a frame 1 First buffer in a frame 6 CM Continuous mode Note that RxBD E is cleared if an error occurs during reception regardless of CM 0 Normal operation 1 RxBD E is not cleared by the CPM after this BD is closed allowing the associated buffer to be overwritten next time the CPM accesses it 7 Ñ Reserved should be cleared 8 D...

Page 694: ...s Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 3 Status Length Pointer Address 1 Address 2 Control Byte Buffer CRC Byte 1 CRC Byte 2 Buffer Address 1 Address 2 Buffer Control Byte Empty 8 Bytes 8 Bytes 8 Bytes 8 Bytes Two Frames Received in HDLC Unexpected Abort Stored in Rx Buffer Line Idle Occurs before Present Time Time Stored in Rx Buffer Buffer Full Buffer Closed when Closing Flag...

Page 695: ...f TxBDs in this table is determined by TxBD W and the space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is processed 1 SCCE TXB or SCCE TXE is set when this buffer is processed causing interrupts if not masked 4 L Last 0 Not the last buffer in the frame 1 Last buffer in the frame 5 TC Tx CRC Valid only when TxBD L 1 Otherwise it is ignored 0 Transmi...

Page 696: ... Addr 0xA10 SCCE1 0xA14 SCCM1 0xA30 SCCE2 0xA34 SCCM2 0xA50 SCCE3 0xA54 SCCM3 0xA70 SCCE4 0xA74 SCCM4 Figure 24 8 HDLC Event Register SCCE HDLC Mask Register SCCM Table 24 9 SCCE SCCM Field Descriptions Bits Name Description 0Ð2 Ñ Reserved should be cleared 3 4 GLR G LT Glitch on Rx Tx Set when the SCC detects a clock glitch on the receive transmit clock See Section 22 3 6 ÒClock Glitch Detection ...

Page 697: ...he HDLC channel receives a buffer that is not the last in a frame Table 24 9 SCCE SCCM Field Descriptions Continued Bits Name Description CD IDL FLG RXB RXF IDL CD Line Idle Stored in Rx Buffer RXD CD Frame Received by HDLC Time Line Idle TXD RTS Frame Transmitted by HDLC CTS TXB CTS CTS Line Idle Line Idle Stored in Tx Buffer NOTES HDLC SCCE Events 1 RXB event assumes receive buffers are 6 bytes ...

Page 698: ...10 HDLC SCCS Field Descriptions Bits Name Description 0Ð4 Ñ Reserved should be cleared 5 FG Flags The line is checked after the data has been decoded by the DPLL 0 HDLC ßags are not being received The most recently received 8 bits are examined every bit time to see if a ßag is present 1 HDLC ßags are being received FG is set as soon as an HDLC ßag 0x7E is received on the line Once it is set it rem...

Page 699: ...ASE with 0x0008 8 Write 0x0041 to CPCR to execute the INIT RX AND TX PARAMS command for SCC2 This command updates RBPTR and TBPTR of the serial channel with the new values of RBASE and TBASE 9 Write RFCR with 0x10 and TFCR with 0x10 for normal operation 10 Write MRBLR with the maximum number of bytes per Rx buffer Choose 256 bytes MRBLR 0x0100 so an entire Rx frame can Þt in one buffer 11 Write C_...

Page 700: ...hat uses the DPLL in a Manchester encoding Provide a clock which is 16 the chosen bit rate of CLK3 Then connect CLK3 to the HDLC transmitter and receiver A baud rate generator could be used instead ConÞgure SCC2 to use RTS2 CTS2 and CD2 1 Follow steps 1Ð23 in example 1 above 2 Write 0x004A_A400 to GSMR_L2 to make carrier sense always active a 16 bit preamble of Ô01Õpatterns 16 operation of the DPL...

Page 701: ...sent a zero stops transmitting The station that sent a 1 continues as normal The I 430 and T1 605 standards provide a physical layer protocol that allows multiple terminals to share one physical connection These protocols handle collisions efÞciently because one station can always complete its transmission at which point it lowers its own priority to give other devices fair access to the physical ...

Page 702: ...ere the data is buffered in RAM and then resent to the other slave The beneÞt of this conÞguration however is that full duplex operation can be obtained In a point to multipoint environment this is the preferred conÞguration Figure 24 12 shows the single master conÞguration HDLC Bus Controller RXD CTS TXD A RCLK TCLK HDLC Bus Controller RXD CTS TXD B RCLK TCLK HDLC Bus Controller RXD CTS TXD C RCL...

Page 703: ...o transmit the HDLC bus controller monitors the bus using CTS It counts the one bits on CTS When eight consecutive ones are counted the HDLC bus controller starts transmitting on the line if a zero is detected the internal counter is cleared During transmission data is continuously compared with the external bus using CTS CTS is sampled halfway through the bit time using the rising edge of the Tx ...

Page 704: ...es a station normally waits for eight one bits on the line before attempting transmission After successfully sending a frame a station waits for 10 rather than eight consecutive one bits before attempting another transmission This mechanism ensures that another station waiting to transmit acquires the bus before a station can transmit twice When a low priority station detects 10 consecutive ones i...

Page 705: ...bit Setting PSMR BRM delays RTS by one bit which is useful when the HDLC bus connects multiple local stations to a transmission line If the transmission line driver has a one bit delay the delayed RTS can be used to enable the output of the line driver As a result the electrical effects of collisions are isolated locally Figure 24 16 shows RTS timing TCLK CTS Input TXD Output CTS sampled at three ...

Page 706: ...TXDx and L1RXDx Because collisions are still detected from the individual SCC CTS pin it must be conÞgured in port C to connect to the chosen SCC Because the SCC only receives clocks during its time slot CTS is sampled only during the Tx clock edges of the particular SCC time slot TCLK RTS active for only 2 bit times TXD CTS RTS 1st Bit 2nd Bit 3rd Bit Collision Local HDLC Bus HDLC Bus Controller ...

Page 707: ...to 1 if delayed RTS is desired ConÞgure CRC to 16 bit CRC CCITT 0b00 ConÞgure other bits to zero or default To program the general SCC mode register GSMR set the bits as described below Set MODE to HDLC mode 0b0000 ConÞgure CTSS to 1 and all other bits to zero or default ConÞgure the DIAG bits for normal operation 0b00 ConÞgure RDCR and TDCR for 1 clock 0b00 ConÞgure TENC and RENC for NRZ 0b000 Cl...

Page 708: ...24 24 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 709: ...lTalk frame shown in Figure 25 1 is basically a modiÞed HDLC frame Figure 25 1 LocalTalk Frame Format First a synchronization sequence of more than three bits is sent This sequence consists of at least one logical one bit FM0 encoded followed by two bit times or more of line idle with no particular maximum time speciÞed The idle time allows LocalTalk equipment to sense a carrier by detecting a mis...

Page 710: ...G of 400 ms In general these gaps are implemented by the software Depending on the protocol collisions should be encountered only during RTS and ENQ frames Once frame transmission begins it is fully sent regardless of whether it collides with another frame ENQ frames are infrequent and are sent only when a node powers up and enters the network A higher level protocol controls the uniqueness and tr...

Page 711: ...can be used to enable the RS 422 transmit driver 25 4 Programming the SCC in AppleTalk Mode The AppleTalk controller is implemented by setting certain bits in the HDLC controller Otherwise Chapter 24 ÒSCC HDLC Mode Ó describes how to program the HDLC controller Use GSMR PSMR or TODR to program the AppleTalk controller 25 4 1 Programming the GSMR Program the GSMR as described below 1 Set MODE to 0b...

Page 712: ...e edges are used to change the sample point default 11 Clear RTSM default 12 Set all other bits to zero or default 13 Set ENT and ENR as the last step to begin operation 25 4 2 Programming the PSMR Follow these steps to program the protocol speciÞc mode register 1 Set NOF to 0b0001 giving two ßags before frames one opening ßag plus one additional ßag 2 Set CRC 16 bit CRC CCITT 3 Set DRT 4 Set all ...

Page 713: ... unstufÞng provided by this mode supports only asynchronous transmission This mode cannot be used to provide octet stufÞng for synchronous communication lines 26 1 Asynchronous HDLC Features The following list summarizes the main features of the SCC in asynchronous HDLC mode Flexible buffer structure lets all or part of a frame be sent or received Separate interrupts for received frames and transm...

Page 714: ...D table or directly changing the current TxBD pointer TBPTR When the asynchronous HDLC controller receives a STOP TRANSMIT command it stops the transmission and sends the asynchronous HDLC abort sequence It then sends idle characters until the RESTART TRANSMIT command is given at which point it resumes transmission with the next TxBD 26 3 Asynchronous HDLC Frame Reception Processing The asynchrono...

Page 715: ...ue is between 0x00 and 0x1F and the corresponding bit in the Tx control character table is set When a condition applies a two byte sequence is sent instead of the byte The sequence consists of the control escape character 0x7D followed by the original byte exclusive ORed with 0x20 26 5 Receiver Transparency Decoding The asynchronous HDLC receiver decodes characters according to RFC 1549 To recover...

Page 716: ...he following errors Ñ CD carrier detect lost Ñ Receiver overrun Ñ Framing error Ñ Break sequence If an invalid sequence 0x7D7D is received the Þrst control escape character is discarded and the second is unconditionally XORed with 0x20 The sequence is thus stored in the buffer as 0x5D XOR_NEXT Rx CHAR CHAR 0x20 XOR_NEXT 1 CHAR CTRL ESC CHAR Closing Flag False True False True False True True False ...

Page 717: ... is sent The FCS is generated on the original frame before transparency characters start stop bits or ßags are added When receiving the FCS is checked automatically and calculated after any transparency characters start stop bits and ßags are removed For both the controller uses only a 16 bit CRC CCITT polynomial EncodingÑThe asynchronous HDLC controller supports 8 data bits one start bit one stop...

Page 718: ...used for the Tx Rx control characters See Figure 26 3 Each bit corresponds to a character that should be mapped according to RFC 1549 If a TXCTL_TBL bit is set its corresponding character is mapped otherwise it is not mapped If an RXCTL_TBL bit is set its corresponding character is discarded if received otherwise it is received normally TXCTL_TBL and RXCTL_TBL should be initialized to zero for IrL...

Page 719: ... transmit clocks or immediately if TODR TOD 1 and begins sending data if TxBD R is set Table 26 2 Asynchronous HDLC Specific GSMR Field Descriptions Name Description IRP Infrared Rx polarity GSMR_H 13 Determines the polarity of the received signal when SCC2 uses IrDA encoding decodingÑfor SCC2 only See Section 26 18 ÒIrDA Encoder Decoder SCC2 Only Ó 0 Active high polarity An active high pulse is d...

Page 720: ...e unless GSMR_H TFL 1 GRACEFUL STOP TRANSMIT Not supported by the asynchronous HDLC controller RESTART TRANSMIT Reenables transmission of characters the asynchronous HDLC controller expects it after a STOP TRANSMIT command or transmitter error The controller continues sending from the Þrst character in the buffer using the current TxBD pointed to by TBPTR INIT TX PARAMETERS Initializes all Tx para...

Page 721: ...he receiver then looks for the next frame CD Lost during Frame Reception The channel stops receiving frames closes the buffer and sets SCCE RXF and RxBD CD This error has highest priority The rest of the frame is lost and other errors are not checked in that frame The receiver then searches for the next frame once CD is reasserted Abort Sequence When an abort sequence 0x7D 0x7E for PPP 0x7D 0xC1 f...

Page 722: ...Break end Marks the end of a break sequenceÑset when an idle bit is detected after a break sequence 11 BRKS Break start Set when the Þrst break character of a break sequence is received Only one BRKS event occurs per break sequence no matter the length of the sequence 12 RXF Rx frame Set when the number of frames speciÞed in RFTHR are received RXF is set no sooner than when the midpoint of the clo...

Page 723: ... 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field FLC Ñ CHLN Ñ Reset 0 R w R W Addr 0xA08 PSMR1 0xA28 PSMR2 0xA48 PSMR3 0xA68 PSMR4 Figure 26 6 Asynchronous HDLC Mode Register PSMR Table 26 9 PSMR Field Descriptions Bits Name Description 0 FLC Flow control 0 Normal operation 1 Asynchronous ßow control When CTS is negated the transmitter stops at the end of the current character If CTS remains negated pas...

Page 724: ... after this buffer is used SCCE RXF is unaffected 1 SCCE RXB or SCCE RXF is set when this buffer is used by the asynchronous HDLC controller 4 L Last in frame 0 Not the last buffer in a frame 1 Set by SCC when a buffer is the last in a frame which happens when a closing ßag or error is received If an error occurs one or more of the BRK CD OV BOF CR and AB bits are set The SCC updates RxBD Data Len...

Page 725: ...C TxBDs Table 26 11 Asynchronous HDLC TxBD Status and Control Field Descriptions Bits Name Description 0 R Ready 0 The buffer is not ready for transmission the BD and the buffer can be updated The CPM clears R after the buffer is sent or after an error condition 1 The buffer is ready but is not sent or is being sent Do not update the BD while R 1 1 Ñ Reserved should be cleared 2 W Wrap last BD in ...

Page 726: ... error counters in the HDLC controller are not implemented in the asynchronous HDLC controller Noisy characters characters for which all three samples are not identical are not accounted for in the asynchronous HDLC controller It is assumed that the CRC catches any data integrity problems 26 17 SCC Asynchronous HDLC Programming Example The following example shows initialization for an SCC in async...

Page 727: ... Initialize all TxBDs 15 Clear SCCE by writing 0xFFFF to it 16 Program SCCM to enable all preferred interrupts 17 Program GSMR_H 18 Program GSMR_L to asynchronous HDLC mode but do not turn on the transmitter or receiver 19 Set the PSMR appropriately See Section 26 13 3 ÒAsynchronous HDLC Mode Register PSMR Ó 20 Enable the transmitter and receiver in GSMR_L 26 18 IrDA Encoder Decoder SCC2 Only The ...

Page 728: ...iver and LED are 3 16 of a bit period in duration or for the slower bit rates as short as 3 16 of the bit period for 115 2 Kbps Electrical pulses between the detector receiver and IR receive decoder are nominally the same duration as those between the IR transmit encoder output driver and LED Figure 26 10 UART and IR Frames The SIR encoding decoding is supported only for SCC2 To activate it set GS...

Page 729: ...a combination longitudinal sum check and vertical parity redundancy check if 7 bit characters are used In transparent operation a special character DLE is deÞned that tells the receiver that the next character is text allowing BISYNC control characters to be valid text data in a frame A DLE sent as data must be preceded by a DLE character This is sometimes called byte stufÞng The physical layer of...

Page 730: ...support SYNC DLE stripping and insertion CRC16 and LRC sum check generation checking VRC parity generation checking Supports BISYNC transparent operation Maintains parity error counter Reverse data mode capability 27 2 SCC BISYNC Channel Frame Transmission The BISYNC transmitter is designed to work with almost no core intervention When the transmitter is enabled it starts sending SYN1ÐSYN2 pairs i...

Page 731: ...cter recognition Control characters are discussed in Section 27 6 ÒSCC BISYNC Control Character Recognition Ó When enabled the receiver enters hunt mode where the data is shifted into the receiver shift register one bit at a time and the contents of the shift register are compared to the contents of DSR SYN1 SYN2 If the two are unequal the next bit is shifted in and the comparison is repeated When...

Page 732: ...hould be preset to all ones or zeros depending on the BCS used 0x3A PTCRC Hword 0x3C PAREC Hword Receive parity error counter This 16 bit modulo 2 16 counter maintained by the CP counts parity errors on receive if the parity feature of BISYNC is enabled Initialize PAREC while the channel is disabled 0x3E BSYNC Hword BISYNC SYNC register Contains the value of the SYNC to be sent as the second byte ...

Page 733: ...SMIT is issued RESTART TRANSMIT Lets characters be sent on the transmit channel The BISYNC controller expects it after a STOP TRANSMIT or a GRACEFUL STOP TRANSMIT command is issued after a transmitter error occurs or after a STOP TRANSMIT is issued and the channel is disabled in its SCCM The controller resumes transmission from the current TBPTR in the channelÕs TxBD table INIT TX PARAMETERS Initi...

Page 734: ...e block to be received without interrupting software Up to eight control characters can be deÞned to inform the BISYNC controller that the end of the current block is reached and whether a BCS is expected after the character For example the end of text character ETX implies an end of block ETB with a subsequent BCS An enquiry ENQ character designates an end of block without a subsequent BCS All th...

Page 735: ...ed 0 The character is written into the receive buffer and the buffer is closed 1 The character is written into the receive buffer The receiver waits for one LRC or two CRC bytes of BCS and then closes the buffer This should be used for ETB ETX and ITB 2 H Hunt mode Enables hunt mode when the current buffer is closed 0 The BISYNC controller maintains character synchronization after closing this buf...

Page 736: ...ller examines the control character table and acts accordingly If the character is not in the table the buffer is closed with the DLE follow character error bit set If the valid bit is not set the receiver treats the character as a normal character When using 7 bit characters with parity the parity bit should be included in the DLE register value Table 27 6 describes BDLE Þelds Table 27 5 BSYNC Fi...

Page 737: ...e SCCE Modem lines can be directly monitored via the port C pins Table 27 8 describes transmit errors Table 27 7 Receiver SYNC Pattern Lengths of the DSR GSMR_H SYNL Setting Bit Assignments 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00 An external SYNC signal is used instead of the SYNC pattern in the DSR 01 4 Bit 10 8 Bit 11 16 Bit Table 27 8 Transmit Errors Error Description Transmitter Underrun The ...

Page 738: ...oses the buffer sets RxBD CD and generates the RXB interrupt if not masked This error has the highest priority If the rest of the message is lost no other errors are checked in the message The receiver immediately enters hunt mode Parity The channel writes the received character to the buffer and sets RxBD PR The channel stops receiving closes the buffer sets RxBD PR and generates the RXB interrup...

Page 739: ...s reset BCS calculations exclude the latest fully received data byte When RBCS is set BCS calculations continue as normal 7 RTR Receiver transparent mode 0 Normal receiver mode with SYNC stripping and control character recognition 1 Transparent receiver mode SYNCs DLEs and control characters are recognized only after a leading DLE character The receiver calculates the CRC16 sequence even if it is ...

Page 740: ...0 Even parity 11 Force high parity always send a one in the parity bit position 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 E Ñ W I L F CM Ñ DE Ñ NO PR CR OV CD Offset 2 Data Length Offset 4 Rx Data Buffer Pointer Offset 6 Figure 27 6 SCC BISYNC RxBD Table 27 11 SCC BISYNC RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty 0 The buffer is full or stopped receiving becaus...

Page 741: ...he frame 1 The Þrst buffer in the frame 5 F First in frame Set when this is the Þrst buffer in a frame 0 Not the Þrst buffer in a frame 1 First buffer in a frame 6 CM Continuous mode 0 Normal operation 1 The CP does not clear E after this BD is closed the buffer is overwritten when the CP accesses this BD next However E is cleared if an error occurs during reception regardless of how CM is set 7 Ñ...

Page 742: ... services this buffer which can cause an interrupt 4 L Last in message 0 The last character in the buffer is not the last character in the current block 1 The last character in the buffer is the last character in the current block The transmitter enters and stays in normal mode after sending the last character in the buffer and the BCS if enabled 5 TB Transmit BCS Valid only when the L bit is set ...

Page 743: ...utomatically inserts DLEÐSYNC pairs if an underrun occurs the controller Þnishes a buffer with L 0 and the next BD is not available It also checks all characters before sending them If a DLE is detected another DLE is sent automatically Insert a DLE or program the controller to insert one before each control character The transmitter calculates the CRC16 BCS even if PSMR BCS is programmed to LRC I...

Page 744: ... when DPLL is used 6Ð7 Ñ Reserved should be cleared 8 GRA Graceful stop complete Set as soon the transmitter Þnishes any message in progress when a GRACEFUL STOP TRANSMIT is issued immediately if no message is in progress 9Ð10 Ñ Reserved should be cleared 11 TXE Tx Error Set when an error occurs on the transmitter channel 12 RCH Receive character Set when a character is received and written to the...

Page 745: ...te After analyzing the initial characters of a block either set PSMR RTR or issue a RESET BCS CALCULATION command For example if a DLE STX is received enter transparent mode By setting the appropriate PSMR bit the controller strips the leading DLE from DLE character sequences Thus control characters are recognized only when they follow a DLE character PSMR RTR should be cleared after a DLE ETX is ...

Page 746: ...O 8 9 and PCPAR 14 clear PCPAR 8 9 and PCDIR 8 9 14 3 ConÞgure port A to enable CLK3 Set PAPAR 5 and clear PADIR 5 4 Connect CLK3 to SCC2 using the serial interface Set SICR R2CS T2CS to 0b110 5 Connect the SCC2 to the NMSI and clear SICR SC2 6 Initialize the SDMA conÞguration register SDCR 7 Assuming one RxBD at the beginning of dual port RAM followed by one TxBD write RBASE with 0x0000 and TBASE...

Page 747: ...r any previous events 22 Write 0x0013 to SCCM to enable the TXE TXB and RXB interrupts 23 Write 0x20000000 the CIMR so SCC2 can generate a system interrupt CICR should also be initialized 24 Write 0x00000020 to GSMR_H2 to conÞgure a small receive FIFO width 25 Write 0x00000008 to GSMR_L2 to conÞgure CTS and CD to automatically control transmission and reception DIAG bits and the BISYNC mode Notice...

Page 748: ...27 20 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 749: ...he Ethernet type Þeld IEEE 802 3 length Þeld The type Þeld signiÞes the protocol used in the rest of the frame and the length Þeld speciÞes the length of the data portion of the frame For Ethernet and IEEE 802 3 frames to coexist on the same LAN the length Þeld of the frame must always be different from any type Þelds used in Ethernet This limits the length of the data portion of the frame to 1 50...

Page 750: ...SIA and transceiver function to complete the interface to the media This function is implemented in the Motorola MC68160 enhanced Ethernet serial transceiver EEST The MPC860 EEST solution provides a direct connection to the attachment unit interface AUI or twisted pair 10BASE T The EEST provides a glueless interface to the MPC860 Manchester encoding and decoding automatic selection of 10BASE T ver...

Page 751: ... support Ñ Enforces the collision jamming Ñ Truncated binary exponential backoff algorithm for random wait Ñ Two nonaggressive backoff modes Ñ Automatic frame retransmission until Òattempt limitÓ is reached Ñ Automatic discard of incoming collided frames Ñ Delay transmission of new frames for speciÞed interframe gap Maximum 10 Mbps bit rate Optional full duplex support Back to back frame reception...

Page 752: ... mode 28 3 Learning Ethernet on the MPC860 The standard SCC functionality has been enhanced on the MPC860 to support Ethernet First time MPC860 users who plan to use Ethernet should Þrst read the following Chapter 22 ÒSerial Communications Controllers Ó describes basic operation of the SCCs Chapter 18 ÒCommunications Processor Module and CPM Timers Ó describes how the CPM issues special commands t...

Page 753: ...on the MPC860 Note that RCLK and TCLK should not be connected to the same CLKx since the EEST provides separate transmit and receive clock signals Transmit data TXD Ñthe MPC860 TXD signal Receive data RXD Ñthe MPC860 RXD signal The following signals take on different functionality when the SCC is in Ethernet mode Transmit enable TENA ÑRTS becomes TENA The polarity of TENA is active high whereas th...

Page 754: ...ta Þeld and appends the FCS to the frame 28 5 SCC Ethernet Channel Frame Transmission The Ethernet transmitter works with almost no core intervention When the core enables the transmitter the SCC polls the Þrst TxBD in the table every 128 serial clocks Setting TODR TOD lets the next frame be sent without waiting for the next poll To begin transmission the SCC in Ethernet mode called the Ethernet c...

Page 755: ...d characters to short frames If TxBD PAD is set the frame is padded up to the value of the minimum frame length register MINFLR To send expedited data before previously linked buffers or for error situations the GRACEFUL STOP TRANSMIT command can be used to rearrange transmit queue before the CPM sends all the frames the Ethernet controller stops immediately if no transmission is in progress or it...

Page 756: ...BD length is determined by MRBLR in the SCC general purpose parameter RAM which should be at least 64 bytes During reception the Ethernet controller checks for a frame that is either too short or too long When the frame ends the receive CRC Þeld is checked and written to the buffer The data length written to the last BD in the Ethernet frame is the length of the entire frame and it enables the sof...

Page 757: ...on or source address and to generate writes to the CAM for address recognition In addition RENA supplied from the EEST can abort the comparison if a collision occurs on the receive frame After the comparison if CAM control logic asserts REJECT for the current receive frame the Ethernet controller immediately stops writing data to system memory and reuses the buffer s for the next frame If the CAM ...

Page 758: ...ta is sent directly from the EEST serial interface to the CAM using RXD and RCLK RSTRT is asserted at the beginning of the destination address REJECT should be asserted during the frame to cause the frame to be rejected The system bus is used for CAM initialization and maintenance EEST MC68160 TXD TENA RTS TCLK CLKx RXD RENA CD RCLK CLKx CLSN CTS REJECT Tx TENA TCLK Rx RENA RCLK CLSN Loop Passive ...

Page 759: ...TS REJECT Tx TENA TCLK Rx RENA RCLK CLSN Loop Passive To Media Tag Destination Data Address Destination Address Type Length Source Address Frame Check Sequence 1 Byte Optional 4 Byte 2 Bytes 6 Bytes 2 Bytes 46Ð1500 Bytes 4 Bytes Parallel I O PB 16 23 SDACK1 SDACK2 CAM Control Optional Frame Tag Byte CAM System Bus SDMA SDACK2 SCC Bus Writes Asserted for One Cycle or Two 16 Bit Write Cycles etc Ass...

Page 760: ...nd discard frame counters The CPM maintains these 32 bit modulo 232 counters that can be initialized while the channel is disabled CRCEC is incremented for each received frame with a CRC error not including frames not addressed to the controller frames received in the out of buffers condition frames with overrun errors or frames with alignment errors ALEC is incremented for frames received with dr...

Page 761: ...rd 0x52 MAXD Hword Rx max DMA 0x54 DMA_CNT Hword Rx DMA counter A temporary down counter used to track frame length 0x54 MAX_B Hword Maximum BD byte count 0x58 GADDR1 Hword Group address Þlter 1Ð4 Used in the hash table function of the group addressing mode Write zeros to these values after reset and before the Ethernet channel is enabled to disable all group hash address recognition functions The...

Page 762: ...TR Hword Tx last BD pointer 0x80 TBUF1_DATA0 Word Save area 0Ñnext frame 0x84 TBUF1_DATA1 Word Save area 1Ñnext frame 0x88 TBUF1_RBA0 Word 0x8C TBUF1_CRC Word 0x90 TBUF1_BCNT Hword 0x92 TX_LEN Hword Tx frame length counter 0x94 IADDR1 Hword Individual address Þlter 1Ð4 Used in the hash table function of the individual addressing mode Zeros can be written to these values after reset and before the ...

Page 763: ...X and RX PARAMETERS resets both transmit and receive parameters Table 28 3 Receive Commands Command Description ENTER HUNT MODE After hardware or software is reset and the channel is enabled in GSMR_L the channel is in receive enable mode and uses the Þrst BD in the table The receiver then enters hunt mode waiting for an incoming frame The ENTER HUNT MODE command is generally used to force the Eth...

Page 764: ...ss recognition the Ethernet controller compares the destination address Þeld of the received frame with the user programmed physical address in PADDR1 Address recognition can be performed on multiple individual addresses using the IADDR1Ð4 hash table Figure 28 6 Ethernet Address Recognition Flowchart Check Address I G Address Hash_Search False G True True Multiple IND Broadcast Address Use Indicat...

Page 765: ...ed result to generate a number between 1 and 64 Bits 31Ð30 of the CRC result select one of the GADDRs or IADDRs bits 29Ð26 of the CRC result indicate the bit in that register When the Ethernet controller receives a frame the same process is used If the CRC generator selects a bit that is set in the group individual hash table the frame is accepted Otherwise it is rejected So if eight group address...

Page 766: ...8 15 Internal and External Loopback Both internal and external loopback are supported by the Ethernet controller In loopback mode both of the SCC FIFOs are used and the channel actually operates in a full duplex fashion Both internal and external loopback are conÞgured using combinations of PSMR LPB and GSMR DIAG Because of the full duplex nature of the loopback operation the performance of other ...

Page 767: ...vers have a heartbeat signal quality error self test To signify a good self test the transceiver indicates a collision to the MPC860 within 20 clocks after the Ethernet controller sends a frame This heartbeat condition does not imply a collision error but that the transceiver seems to be functioning properly If SCCE HBC 1 and the MPC860 does not detect a heartbeat condition after sending a frame a...

Page 768: ... it is received 1 The individual hash table is used to check all individual addresses that are received 4Ð5 CRC CRC selection Only CRC 10 is valid Complies with Ethernet speciÞcations 32 bit CCITT CRC X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X1 1 6 PRO Promiscuous 0 Check the destination address of incoming frames 1 Receive the frame regardless of its address unless REJECT is asserted as it ...

Page 769: ... 13 14 15 Offset 0 E Ñ W I L F Ñ M Ñ LG NO SH CR OV CL Offset 2 Data Length Offset 4 Rx Data Buffer Pointer Offset 6 Figure 28 8 SCC Ethernet Receive RxBD Table 28 7 SCC Ethernet Receive RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty 0 The buffer is full or stopped receiving data because an error occurred The core can read or write any Þelds of this RxBD The CPM does no...

Page 770: ...cepted in promiscuous mode but are ßagged as a miss by internal address recognition Thus in promiscuous mode M determines whether a frame is destined for this station 0 The frame is received because of an address recognition hit 1 The frame is received because of promiscuous mode 8Ð9 Ñ Reserved should be cleared 10 LG Rx frame length violation Set when a frame length greater than the maximum deÞne...

Page 771: ...ength Pointer 0 0x0045 32 Bit Buffer Pointer 0 E F Receive BD 1 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 2 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 3 Status Length Pointer Destination Address 6 Source Address 6 Type Length 2 Buffer CRC Bytes 4 Tag Byte 1 Buffer Buffer Old Data from Empty 64 Bytes 64 Bytes 64 Bytes 64 Bytes Two Frames Received in Ethern...

Page 772: ... constraints of the dual port RAM Note The TxBD table must contain more than one BD in Ethernet mode 3 I Interrupt 0 No interrupt is generated after this buffer is serviced 1 SCCE TXB or SCCE TXE is set after this buffer is serviced These bits can cause interrupts if they are enabled 4 L Last 0 Not the last buffer in the transmit frame 1 Last buffer in the transmit frame 5 TC Tx CRC Valid only whe...

Page 773: ... more retries were required The controller writes this Þeld after it successfully sends the buffer 14 UN Underrun Set when the Ethernet controller encounters a transmitter underrun while sending the buffer The Ethernet controller writes UN after it Þnishes sending the buffer 15 CSL Carrier sense lost Set when carrier sense is lost during frame transmission The Ethernet controller writes CSL after ...

Page 774: ...me Description RXB Line Idle Stored in Rx Buffer RXD RENA Frame Received in Ethernet Time Line Idle TXD TENA Frame Transmitted by Ethernet CLSN TXB GRA TXB Line Idle Line Idle Stored in Tx Buffer NOTES Ethernet SCCE Events 1 RXB event assumes receive buffers are 64 bytes each 2 The RENA events if required must be programmed in the port C parallel I O not in the SCC itself 3 The RxF interrupt may o...

Page 775: ...TxBD in the dual port RAM Assuming one RxBD at the beginning of the dual port RAM and one TxBD following that RxBD write RBASE with 0x0000 and TBASE with 0x0008 9 Program the CPCR to execute an INIT RX AND TX PARAMETERS command for this channel 10 Write RFCR and TFCR with 0x10 for normal operation 11 Write MRBLR with the maximum number of bytes per receive buffer Here assume 1520 bytes so MRBLR 0x...

Page 776: ...gister should also be initialized 30 Write 0x0000_0000 to GSMR_H1 to enable normal operation of all modes 31 Write 0x1088_000C to the GSMR_L1 register to conÞgure CTS CLSN and CD RENA to automatically control transmission and reception DIAG bits and the Ethernet mode TCI is set to allow more setup time for the EEST to receive the MPC860 transmit data TPL and TPP are set for Ethernet requirements T...

Page 777: ...ing the protocol encoded on that data path Transparent mode is conÞgured in the GSMR see Section 22 1 1 ÒGeneral SCC Mode Register GSMR Ó Transparent mode is selected in GSMR_H TTX TRX for the transmitter and receiver respectively Setting both bits enables full duplex transparent operation If only one is set the other half of the SCC uses the protocol speciÞed in GSMR_L MODE This allows loop back ...

Page 778: ...ely to the next buffer to begin transmission with no gap on the serial line between buffers Failure to provide the next buffer in time causes a transmit underrun which sets SCCE TXE In both cases an interrupt is issued according to TxBD I By appropriately setting TxBD I in each BD interrupts are generated after each buffer or group of buffers is sent The SCC then proceeds to the next BD in the tab...

Page 779: ...t is called transmit synchronization Similarly once the SCC receiver is enabled for transparent operation in the GSMR and the RxBD is made empty for the SCC receive synchronization must occur before data can be received An in line synchronization pattern or an external synchronization signal can provide bit level control of the synchronization process when sending or receiving 29 4 1 Synchronizati...

Page 780: ...frame Pulse operation allows an uninterrupted stream of data However use envelope mode to identify frames of transparent data The sampling option determines the delay between CD and CTS being asserted and the resulting action by the SCC Assume either that these signals are asynchronous to the data and internally synchronized by the SCC or that they are synchronous to the data with faster operation...

Page 781: ...and receiver and enabled 29 4 1 4 End of Frame Detection An end of frame cannot be detected in the transparent data stream since there is no deÞned closing ßag in transparent mode Therefore if framing is needed the user must use the CD line to alert the transparent controller of an end of frame RXD CD CLKx TXD RTS CD RXD BRGOx RTS TXD CLKx BRGOx BRGOx Last Bit of Frame Data First Bit of Frame Data...

Page 782: ... begins transmission eight clocks after the receiver achieves synchronization 29 4 2 2 Inherent Synchronization Inherent synchronization assumes synchronization by default when the channel is enabled all data sent from the TDM to the SCC is received To implement inherent synchronization Set GSMR_H CDP CDS CTSP CTSS If these bits are not set the received bit stream will be bit shifted The SCC loses...

Page 783: ...lling the Þrst BD every 64 clocks or immediately if TODR TOD 1 STOP TRANSMIT disables frame transmission on the transmit channel If the transparent controller receives the command during frame transmission transmission is aborted after a maximum of 64 additional bits and the transmit FIFO is ßushed The current TxBD pointer TBPTR is not advanced no new BD is accessed and no new buffers are sent for...

Page 784: ... INIT TX AND RX PARAMETERS resets receive and transmit parameters Table 29 5 Transmit Errors Error Description Transmitter Underrun When this occurs the channel stops sending the buffer closes it sets TxBD UN and generates a TXE interrupt if it is enabled Transmission resumes after a RESTART TRANSMIT command is received Underrun occurs after a transmit frame for which TxBD L was not set In this ca...

Page 785: ...Data Length Offset 4 Rx Buffer Pointer Offset 6 Figure 29 2 SCC Transparent Receive Buffer Descriptor RxBD Table 29 7 SCC Transparent RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty 0 The buffer is full or stopped receiving data because an error occurred The core can read or write to any Þelds of this RxBD The CPM does not use this BD when RxBD E is zero 1 The buffer is ...

Page 786: ...a length Þeld 0 Not the last buffer in a frame 1 Last buffer in a frame 5 F First in frame The transparent controller sets F when this buffer is the Þrst in the frame 0 Not the Þrst buffer in a frame 1 First buffer in a frame 6 CM Continuous mode 0 Normal operation 1 The CPM does not clear RxBD E after this BD is closed letting the buffer be overwritten when the CPM next accesses this BD However R...

Page 787: ...s determined only by TxBD W and overall space constraints of the dual port RAM 3 I Interrupt Note that clearing this bit does not disable SCCE TXE 0 No interrupt is generated after this buffer is serviced 1 When the CPM services this buffer SCCE TXB or SCCE TXE is set These bits can cause interrupts if they are enabled 4 L Last in message 0 The last byte in the buffer is not the last byte in the t...

Page 788: ...E2 0xA34 SCCM2 0xA50 SCCE3 0xA54 SCCM3 0xA70 SCCE4 0xA74 SCCM4 Figure 29 4 SCC Transparent Event Register SCCE Mask Register SCCM Table 29 9 SCCE SCCM Field Descriptions Bit Name Description 0Ð2 Ñ Reserved should be cleared 3 GLR Glitch on Rx Set when the SCC Þnds a glitch on the receive clock 4 GLT Glitch on Tx Set when the SCC Þnds a glitch on the transmit clock 5 DCC DPLL CS changed Set when th...

Page 789: ...he transparent controller is conÞgured with the RTS2 and CD2 pins active and CTS2 is conÞgured to be grounded internally in port C A 16 bit CRC CCITT is sent with each transparent frame The FIFOs are conÞgured for fast operation 14 TXB Tx buffer Set no sooner than when the last bit of the last byte of the buffer begins transmission assuming L is set in the TxBD If it is not TXB is set when the las...

Page 790: ...tialize the RxBD Assume the Rx buffer is at 0x0000_1000 in main memory Write 0xB000 to RxBD Status and Control 0x0000 to RxBD Data Length optional and 0x0000_1000 to RxBD Buffer Pointer 14 Initialize the TxBD Assume the Tx buffer is at 0x0000_2000 in main memory and contains Þve 8 bit characters Write 0xBC00 to TxBD Status and Control 0x0005 to TxBD Data Length and 0x0000_2000 to TxBD Buffer Point...

Page 791: ...otally transparent mode the SMC can be connected to a TDM channel such as a T1 line or directly to its own set of pins The receive and transmit clocks are derived from the TDM channel the internal BRGs or from an external 1 clock The transparent protocol allows the transmitter and receiver to use the external synchronization pin The SMC in transparent mode is not as complex as the SCC in transpare...

Page 792: ...tion 21 3 ÒNMSI ConÞguration Ó An SMC connected to a TDM derives a synchronization pulse from the TSA An SMC connected to the NMSI using transparent protocol can use SMSYN for synchronization to determine when to start a transfer SMSYN is not used when the SMC is in UART mode 30 1 SMC Features The following is a list of the SMCÕs main features Each SMC can implement the UART protocol on its own pi...

Page 793: ...s less than 8 the msbs of each byte in memory are not used on transmit and are written with zeros on receive If the length is more than 8 the msbs of each 16 bit word are not used on transmit and are written with zeros on receive The character must not exceed 16 bits For a 14 bit data length set SL to one stop bit and disable parity For a 13 bit data length with parity enabled set SL to one stop b...

Page 794: ...cter length is not larger than 8 bits 1 Transmit lower address byte Þrst Ñ Reserved should be cleared GCI 7 PM Parity mode UART 0 Odd parity 1 Even parity REVD Reverse data transparent 0 Normal mode 1 Reverse the character bit order The msb is sent Þrst C SCIT channel number GCI 0 SCIT channel 0 1 SCIT channel 1 Required for Siemens ARCOFI and SGS S T chips 8Ð9 Ñ Reserved should be cleared 10Ð11 S...

Page 795: ...MCs are conÞgured to operate in GCI mode their memory structure is predeÞned to be one half word long for transmit and one half word long for receive For more information on these half word structures see Section 30 5 ÒSMC in GCI Mode Ó 30 2 3 SMC Parameter RAM Each SMC parameter RAM area begins at the same offset from each SMC base The protocol speciÞc portions of the SMC parameter RAM are discus...

Page 796: ...e MRBLR only while the SMC receiver is disabled MRBLR should be greater than zero and should be even if character length exceeds 8 bits 0x08 RSTATE Word Rx internal state Can be used only by the CP 0x0C Ñ Word Rx internal data pointer 2 Updated by the SDMA channels to show the next address in the buffer to be accessed 0x10 RBPTR Hword RxBD pointer Points to the next BD for each SMC channel that th...

Page 797: ... contains the value to appear on the function code pins AT 1Ð3 when the associated SDMA channel accesses memory The FCRs also control byte ordering See Figure 30 4 Table 30 3 describes RFCR Þelds 30 2 4 Disabling SMCs On the Fly An SMC can be disabled and reenabled later by ensuring that buffers are closed properly and new data is transferred to or from a new buffer Such a sequence is required if ...

Page 798: ...AMETERS was not issued in step 3 5 Set SMCMR TEN Transmission now begins using the TxBD that the TBPTR value points to as soon as the R bit is set in that TxBD 30 2 4 2 SMC Transmitter Shortcut Sequence This shorter sequence reinitializes transmit parameters to the state they had after reset 1 Clear SMCMR TEN 2 Make any changes then issue an INIT TX PARAMETERS command 3 Set SMCMR TEN 30 2 4 3 SMC ...

Page 799: ...s time 2 Process the TxBD to reuse it if SMCE TX is set Extract data from the RxBD if SMCE RX is set To send another buffer set R in the RxBD 3 Clear CISR SMC1 4 Execute the rfi instruction 30 3 SMC in UART Mode SMCs generally offer less functionality and performance in UART mode than do SCCs which makes them more suitable for simpler debug monitor ports instead of full featured UARTs SMCs do not ...

Page 800: ...s which sends an interrupt request to the core to receive data from the buffer An idle character is deÞned as a full character length of logic high MAX_IDL can be used to demarcate frames in UART mode Clearing MAX_IDL disables this function so idle never causes the buffer to close regardless of how many idle characters are received The length of an idle character is calculated as follows 1 data le...

Page 801: ...W bits set the buffer is sent continuously until R is cleared in the BD 30 3 4 SMC UART Channel Reception Process When the core enables the SMC receiver it enters hunt mode and waits for the Þrst character The CP then checks the Þrst RxBD to see if it is empty and starts storing characters in the buffer When the buffer is full or the MAX_IDL timer expires if enabled the SMC clears the E bit in the...

Page 802: ... Disables transmission of characters on the transmit channel If the SMC UART controller receives this command while sending a message it stops sending The SMC UART controller Þnishes sending any data that has already been sent to its FIFO and shift register and then stops sending data The TBPTR is not advanced when this command is issued The SMC UART controller sends a programmable number of break...

Page 803: ...ter length FIFO for receiving data Data is moved to the buffer after the Þrst character is received into the FIFO if a receiver FIFO overrun occurs the channel writes the received character into the internal FIFO It then writes the character to the buffer closes it sets RxBD OV and generates the RX interrupt if it is enabled Reception then resumes as normal Overrun errors that occasionally occur w...

Page 804: ...tion is in progress This RxBD and its buffer are owned by the CP Once E is set the core should not write any Þelds of this RxBD 1 Ñ Reserved should be cleared 2 W Wrap last BD in RxBD table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CP receives incoming data into the Þrst BD that RBASE points to in the table The number of RxBDs in this table is determined o...

Page 805: ...eak Set when the buffer closes because a break sequence was received The CP writes BR after the received data is in the buffer 11 FR Framing error Set when a character with a framing error is received and located in the last byte of this buffer A framing error is a character with no stop bit A new receive buffer is used to receive additional data The CP writes FR after the received data is in the ...

Page 806: ...D 0 Status Length Pointer 0 0002 32 Bit Buffer Pointer 1 E ID Receive BD 1 Status Length Pointer 0 0004 32 Bit Buffer Pointer 0 E ID Receive BD 2 Status Length Pointer 1 XXXX 32 Bit Buffer Pointer E Receive BD 3 Status Length Pointer Byte 1 Byte 2 Byte 8 Buffer Byte 9 Byte 10 Buffer Byte 1 Byte 2 Byte 3 Buffer Byte 4 Error Empty Additional Bytes will be Stored Unless Idle Count Expires MAX_IDL 8 B...

Page 807: ...Ready 0 The buffer is not ready for transmission BD and its buffer can be altered The CP clears R after the buffer has been sent or an error occurs 1 The buffer has not been completely sent This BD must not be updated while R is set 1 Ñ Reserved should be cleared 2 W Wrap Þnal BD in the TxBD table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CP receives incom...

Page 808: ...M Þelds Bit 0 1 2 3 4 5 6 7 Field Ñ BRKE Ñ BRK Ñ BSY TX RX Reset 0 R W R W Address 0xA86 SMCE1 0xA96 SMCE2 0xA8A SMCM1 0xA9A SMCM2 Figure 30 9 SMC UART Event Register SMCE Mask Register SMCM Table 30 10 SMCE SMCM Field Descriptions Bits Name Description 0 Ñ Reserved should be cleared 1 BRKE Break end Set no sooner than after one idle bit is received after the break sequence 2 Ñ Reserved should be ...

Page 809: ...Write 0x0091 to CPCR to execute the INIT RX AND TX PARAMETERS command 6 Initialize the SDMA conÞguration register SDCR to 0x0001 7 Write RFCR and TFCR with 0x10 for normal operation 8 Write MRBLR with the maximum number of bytes per receive buffer Assume 16 bytes so MRBLR 0x0010 9 Write MAX_IDL with 0x0000 in the SMC UART speciÞc parameter RAM to disable the MAX_IDL functionality for this example ...

Page 810: ...ditional write ensures that the TEN and REN bits are enabled last After 5 bytes are sent the TxBD is closed The receive buffer closes after receiving 16 bytes Subsequent data causes a busy out of buffers condition since only one RxBD is ready 30 4 SMC in Transparent Mode Compared to the SCC in transparent mode the SMCs generally have less functionality simpler functions and slower speeds Transpare...

Page 811: ...d once every character time depending on the character length every 4 to 16 serial clocks When there is a message to transmit the SMC fetches the data from memory and starts sending the message when synchronization is achieved Synchronization can be achieved in two ways First when the transmitter is connected to a TDM channel it can be synchronized to a time slot Once the frame sync is received th...

Page 812: ...rking with its own set of pins the receiver starts reception when SMSYNx is asserted When the buffer full the SMC clears the E bit in the BD and generates an interrupt if the I bit in the BD is set If incoming data exceeds the buffer length the SMC fetches the next BD if it is empty the SMC continues transferring data to this BDÕs buffer If the CM bit is set in the RxBD the E bit is not cleared so...

Page 813: ... setting TEN may be insufÞcient The receiver can also be resynchronized this way 30 4 6 Using TSA for Synchronization The TSA offers an alternative to using SMSYN to internally synchronize the SMC channel This method is similar except that the synchronization event is the Þrst time slot for this SMC receiver transmitter after the frame sync indication rather than the falling edge of SMCLK SMSYN SM...

Page 814: ...NTER HUNT MODE command is issued the receiver loses synchronization closes the buffer and resynchronizes to the Þrst time slot after the frame sync Once SMCMR TEN is set the SMC waits for the transmit FIFO to be loaded before trying to achieve synchronization If only a single time slot in a TDM frame is assigned to the SMC SMC transmission as well as reception is always synchronized to the beginni...

Page 815: ...SMC Simply clearing and setting TEN may not be enough 30 4 7 SMC Transparent Commands Table 30 12 describes transmit commands issued to the CPCR Table 30 12 SMC Transparent Transmit Commands Command Description STOP TRANSMIT After hardware or software is reset and the channel is enabled in the SMCMR the channel is in transmit enable mode and polls the Þrst BD This command disables transmission of ...

Page 816: ...ive BD if it in use and to use the next BD in the list for subsequent received data If the SMC is not in the process of receiving data no action is taken iNIT RX PARAMETERS Initializes receive parameters in this serial channel to reset state Use only if the receiver is disabled The INIT TX AND RX PARAMETERS command resets receive and transmit parameters Table 30 14 SMC Transparent Error Conditions...

Page 817: ...buffer Once E is set the core should not write any Þelds of this RxBD 1 Ñ Reserved should be cleared 2 W Wrap last BD in RxBD table 0 Not the last BD in the table 1 Last BD in the table After this buffer is used the CP receives incoming data into the Þrst BD that RBASE points to The number of RxBDs is determined only by the W bit and overall space constraints of the dual port RAM 3 I Interrupt 0 N...

Page 818: ...this buffer is used the CP receives incoming data into the Þrst BD that TBASE points to The number of TxBDs in this table is programmable and determined by the W bit and overall space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is serviced unless an error occurs 1 SMCE TX or SMCE TXE are set when the buffer is serviced They can cause interrupts if t...

Page 819: ...terrupt request Figure 30 15 shows the SMCE SMCM register format Table 30 17 describes SMCE SMCM Þelds Bit 0 1 2 3 4 5 6 7 Field Ñ TXE Ñ BSY TX RX Reset 0 R W R W Address 0xA86 SMCE1 0xA96 SMCE2 0xA8A SMCM1 0xA9A SMCM2 Figure 30 15 SMC Transparent Event Register SMCE Mask Register SMCM Table 30 17 SMCE SMCM Field Descriptions Bits Name Description 0Ð2 Ñ Reserved should be cleared 3 TXE Tx error Se...

Page 820: ...he SDCR to initialize the SDCR 7 Write RFCR and TFCR with 0x10 for normal operation 8 Write MRBLR with the maximum bytes per receive buffer Assuming 16 bytes MRBLR 0x0010 9 Initialize the RxBD assuming the buffer is at 0x0000_1000 in main memory Write 0xB000 to RxBD Status and Control 0x0000 to RxBD Data Length optional and 0x0000_1000 to RxBD Buffer Pointer 10 Initialize the TxBD assuming the Tx ...

Page 821: ... RxBD Status and Control 0x0000 to RxBD Data Length optional and 0x0000_1000 to RxBD Buffer Pointer 7 Initialize the TxBD and assume the Tx buffer is at 0x0000_2000 in main memory and contains Þve 8 bit characters Write 0xB000 to TxBD Status and Control 0x0005 to TxBD Data Length and 0x0000_2000 to TxBD Buffer Pointer 8 Write 0xFF to SMCE to clear any previous events 9 Write 0x13 to SMCM to enable...

Page 822: ...ding and writing internal registers and transferring of the S and Q bits In SCIT conÞguration monitor channel 1 is used for programming and controlling voice data modules such as CODECs The core writes the byte into the TxBD The SMC sends the data on the monitor channel and handles the A and E control bits according to the GCI monitor channel protocol The TIMEOUT command resolves deadlocks when er...

Page 823: ...gnizes a change in the data and this value is received in two successive frames it is interpreted as valid data This is called the double last look method The CP stores the received data byte in the C I RxBD and a maskable interrupt is generated If the SMC is conÞgured to support SCIT channel 1 the double last look method is not used 30 5 4 SMC GCI Commands The commands in Table 30 19 are issued t...

Page 824: ...knowledged the previous byte 3 MS Data mismatch Set when two different consecutive bytes are received cleared when the last two consecutive bytes match The SMC waits for the reception of two identical consecutive bytes before writing new data to the RxBD 4Ð7 Ñ Reserved should be cleared 8Ð15 Data Data Þeld Contains the monitor channel data byte that the SMC received 0 1 2 3 4 5 6 7 8 9 10 11 12 13...

Page 825: ...he core 1 The core sets E to indicate that the byte associated with this BD has been read Note that additional data received is discarded until E bit is set 1Ð7 Ñ Reserved should be cleared 8Ð13 C I Data Command indication data bits For C I channel 0 bits 10Ð13 contain the 4 bit data Þeld and bits 8Ð9 are always written with zeros For C I channel 1 bits 8Ð13 contain the 6 bit data Þeld 14Ð15 Ñ Res...

Page 826: ...request to the CP interrupt controller CPIC Figure 30 20 shows the SMCE SMCM register format Table 30 24 describes SMCE SMCM Þelds Bit 0 1 2 3 4 5 6 7 Field Ñ CTXB CRXB MTXB MRXB Reset 0000_0000 R W R W Address 0xA86 SMCE1 0xA96 SMCE2 0xA8A SMCM1 0xA9A SMCM2 Figure 30 20 SMC GCI Event Register SMCE Mask Register SMCM Table 30 24 SMCE SMCM Field Descriptions Bits Name Description 0Ð3 Ñ Reserved sho...

Page 827: ...eiver sections an independent baud rate generator and a control unit The transmitter and receiver sections use the same clock which is derived from the SPI baud rate generator in master mode and generated externally in slave mode During an SPI transfer data is sent and received simultaneously Because the SPI receiver and transmitter are double buffered as shown in Figure 31 1 the effective FIFO si...

Page 828: ...erated in the MPC860 clock synthesizer SPICLK is a gated clock active only during data transfers Therefore SPI clock rates can be very high up to BRGCLK 4 in master mode or BRGCLK 2 in slave mode Note however that this high clock rate can be supported only over the period of a single character if messages consist of multiple back to back characters operation becomes limited by CPM performance and ...

Page 829: ... SPI signals through the port B signal assignment register PBPAR and the Port B data direction register PBDIR speciÞcally by setting PBPAR DDn and PBDIR DRn 31 3 ConÞguring the SPI Controller The SPI can be programmed to work in a single or multiple master environment This section describes SPI master and slave operation in a single master conÞguration and then discusses the multi master environme...

Page 830: ...characters until the whole buffer is sent or an error occurs The CPM then clears TxBD R and RxBD E and issues a maskable interrupt to the CPM interrupt controller CPIC When multiple TxBDs are ready TxBD L determines whether the SPI keeps transmitting without SPCOM STR being set again If the current TxBD L is cleared the next TxBD is processed after data from the current buffer is sent Typically th...

Page 831: ...s negated Transmission continues until no more data is available or SPISEL is negated If it is negated before all data is sent it stops but the TxBD stays open Transmission continues once SPISEL is reasserted and SPICLK begins toggling After the characters in the buffer are sent the SPI sends ones as long as SPISEL remains asserted 31 3 3 The SPI in Multimaster Operation The SPI can operate in a m...

Page 832: ...ELOUT0 SPISEL SPICLK SELOUT3 SELOUT2 SPI 0 Notes All signals are open drain For a multi master system with more than two masters SPISEL and SPIE MME It is the responsibility of software to arbitrate for the SPI bus with token passing for example will not detect all possible conßicts SELOUTx signals are implemented in software with general purpose I O signals SPISEL1 SPISEL0 SPISEL3 SPISEL2 SPIMISO...

Page 833: ...k polarity See Figure 31 5 and Figure 31 6 0 The inactive state of SPICLK is low 1 The inactive state of SPICLK is high 3 CP Clock phase Selects the transfer format See Figure 31 5 and Figure 31 6 0 SPICLK starts toggling at the middle of the data transfer 1 SPICLK starts toggling at the beginning of the data transfer 4 DIV16 Divide by 16 Selects the clock source for the SPI baud rate generator wh...

Page 834: ...16 bits A value less than 4 causes erratic behavior If the value is not greater than a byte every byte in memory holds LEN valid bits If the value is greater than a byte every half word holds LEN valid bits See Section 31 4 1 2 ÒSPI Examples with Different SPMODE LEN Values Ó 12Ð15 PM Prescale modulus select SpeciÞes the divide ratio of the prescale divider in the SPI clock generator BRGCLK is div...

Page 835: ...e line is first nmlk_j__vuts_r last with REV 1 the order of the string appearing on the line is first j_klmn__r_stuv last Example 2 with LEN 7 data size 8 the following data is selected msb ghij_klmn__opqr_stuv lsb with REV 0 the string transmitted is first nmlk_jihg__vuts_rqpo last with REV 1 the string is transmitted first ghij_klmn__opqr_stuv last Example 3 with LEN 0xC data size 13 the followi...

Page 836: ... SPI operation Bit 0 1 2 3 4 5 6 7 Field Ñ MME TXE Ñ BSY TXB RXB Reset 0 R W R W Addr 0xAA6 SPIE 0xAAA SPIM Figure 31 7 SPI Event Mask Registers SPIE SPIM Table 31 3 SPIE SPIM Field Descriptions Bits Name Description 0Ð1 Ñ Reserved should be cleared 2 MME Multimaster error Set when SPISEL is asserted externally while the SPI is in master mode 3 TXE Tx error Set when an error occurs during transmis...

Page 837: ...word 0x04 RFCR Byte Rx Tx function code Contains the value to appear on AT 1 3 when the associated SDMA channel accesses memory Also controls byte ordering for the transfers See Section 31 5 1 ÒReceive Transmit Function Code Registers RFCR TFCR Ó 0x05 TFCR Byte 0x06 MRBLR Hword Maximum receive buffer length The SPI has one MRBLR entry to deÞne the maximum number of bytes the MPC860 writes to a Rx ...

Page 838: ...TBPTR to the TBASE value Most applications do not need to modify TBPTR but it can be updated when the transmitter is disabled or when no Tx buffer is in use 0x22 Ñ Hword The Tx internal byte count2 is a down count value initialized with TxBD Data Length and decremented with every byte read by the SDMA channels 0x24 Ñ Word Tx temp Reserved for CPM use Note The user must initialize only items in bol...

Page 839: ...31 7 SPI Commands Command Description INIT TX PARAMETERS Initializes all transmit parameters in the parameter RAM to their reset state and should be issued only when the transmitter is disabled The INIT TX AND RX PARAMETERS command can also be used to reset both the Tx and Rx parameters CLOSE RXBD Forces the SPI controller to close the current RxBD and use the next BD for subsequently received dat...

Page 840: ...r example to send three characters of 8 bit data the data length Þeld should be initialized to 3 However to send three characters of 9 bit data the data length Þeld should be initialized to 6 since the three 9 bit data Þelds occupy three half words in memory The CPM never modiÞes this Þeld The word at offset 4 points to the beginning of the buffer Ñ For an RxBD the pointer must be even and can poi...

Page 841: ... port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is Þlled 1 SPIE RXB is set when this buffer is full indicating the need for the core to process the buffer SPIE RXB causes an interrupt if not masked 4 L Last Updated by the SPI when the buffer is closed In slave mode this occurs because SPISEL was negated The SPI updates L after received data is placed in the buffer 0 This buff...

Page 842: ...all space constraints of the dual port RAM 3 I Interrupt 0 No interrupt is generated after this buffer is processed if an error does not occur 1 SPIE TXB or SPIE TXE are set when this buffer is processed and causes interrupts if not masked Note that this bit does not mask SPIE TXE 4 L Last 0 This buffer does not contain the last character of the message 1 This buffer contains the last character of...

Page 843: ...conÞguration register SDCR 6 Write RFCR and TFCR with 0x10 for normal operation 7 Write MRBLR with the maximum number of bytes per Rx buffer For this case assume 16 bytes so MRBLR 0x0010 8 Initialize the RxBD Assume the Rx buffer is at 0x0000_1000 in main memory Write 0xB000 to RxBD Status and Control 0x0000 to RxBD Data Length optional and 0x0000_1000 to RxBD Buffer Pointer 9 Initialize the TxBD ...

Page 844: ...ta Length optional and 0x0000_1000 to RxBD Buffer Pointer 8 Initialize the TxBD Assume the Tx buffer is at 0x0000_2000 in main memory and contains Þve 8 bit characters Write 0xB800 to TxBD Status and Control 0x0005 to TxBD Data Length and 0x0000_2000 to TxBD Buffer Pointer 9 Write 0xFF to SPIE to clear any previous events 10 Write 0x37 to SPIM to enable all SPI interrupts 11 Write 0x0000_0020 to C...

Page 845: ...wed to handle interrupts in the SPI 1 Once an interrupt occurs read SPIE to determine the interrupt source Normally SPIE bits should be cleared at this time 2 Process the TxBD to reuse it and the RxBD to extract the data from it To transmit another buffer simply set TxBD R RxBD E and SPCOM STR 3 Clear the interrupt by writing a one to CISR SPI 4 Execute an rfi instruction ...

Page 846: ...31 20 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 847: ...ctions an independent baud rate generator BRG and a control unit The transmit and receive sections use the same clock which is derived from the I2 C BRG when in master mode and generated externally when in slave mode Wait states are inserted during a data transfer if SCL is held low by a slave device In the middle of a data transfer the master I2 C controller recognizes the need for wait states by...

Page 848: ...e generator Supports 7 bit I2C addressing Open drain output signals allow multiple master conÞguration Local loopback capability for testing 32 2 I2 C Controller Clocking and Signal Functions The I2 C controller can be conÞgured as a master or slave for the serial channel As a master the controllerÕs BRG provides the transfer clock The I2 C BRG takes its input from the BRG clock BRGCLK which is de...

Page 849: ...e ninth bit frame the transmitter signals a transmission error event I2ER TXE An I2C transfer timing diagram is shown in Figure 32 3 Figure 32 3 I2C Transfer Timing Select master or slave mode for the controller using the I2 C command register I2COM M S Set the masterÕs start bit I2COM STR to begin a transfer setting a slaveÕs I2COM STR activates the slave to wait for a transfer request from a mas...

Page 850: ...ission stops and the master generates a stop conditionÑa low to high transition on SDA while SCL is high 32 3 2 I2C Loopback Testing When in master mode an I2C controller supports loopback operation for master write requests The master I2C controller simply issues a write request directed to its own address programmed in I2ADD The masterÕs receiver monitors the transmission and reads the transmitt...

Page 851: ...e transaction is aborted If the slave is an MPC860 a maskable transmission error interrupt is triggered to allow software to prepare data for transmission on the next try Ñ If a mismatch occurs the slave ignores the message and searches for a new start condition 4 The master acknowledges each byte sent as long as an overrun does not occur If the master receiver fails to acknowledge a byte the slav...

Page 852: ...master before reading a slave writes the slave with a description of the requested data which register should be read for example This operation is typical with many I2C devices 32 4 I2C Registers The following sections describe the I2C registers 32 4 1 I2C Mode Register I2MOD The I2C mode register shown in Figure 32 6 controls the I2C modes and clock source Table 32 1 describes I2MOD bit function...

Page 853: ...GCLK 4 Note To both save power and reduce noise susceptibility select the PDIV with the largest division factor slowest clock that still meets performance requirements 7 EN Enable I2C operation 0 I2 C is disabled The I2 C is in a reset state and consumes minimal power 1 I2 C is enabled Do not change other I2MOD bits when EN is set Bit 0 1 2 3 4 5 6 7 Field SAD Ñ Reset 0000_0000 R W R W Addr 0x864 ...

Page 854: ...riptions Bits Name Description 0Ð7 DIV Division ratio 0Ð7 SpeciÞes the divide ratio of the BRG divider in the I2 C clock generator The output of the prescaler is divided by 2 DIV0ÐDIV7 3 and the clock has a 50 duty cycle DIV must be programmed to a minimum value of 3 if the digital Þlter is disabled and 6 if it is enabled Bit 0 1 2 3 4 5 6 7 Field Ñ TXE Ñ BSY TXB RXB Reset 0000_0000 R W R W Addr 0...

Page 855: ...slave mode setting STR when the I2C controller is idle causes it to load the Tx data register from the current Tx buffer if ready and start sending when it receives an address byte that matches the slave address with R W 1 STR is always read as a 0 1Ð6 Ñ Reserved and should be cleared 7 M S Master slave ConÞgures the I2C controller to operate as a master or a slave 0 I2C is a slave 1 I2C is a mast...

Page 856: ... RxBD pointer Points to the next descriptor the receiver transfers data to when it is in an idle state or to the current descriptor during frame processing for each I2 C channel After a reset or when the end of the descriptor table is reached the CP initializes RBPTR to the value in RBASE Most applications should not write RBPTR but it can be modiÞed when the receiver is disabled or when no receiv...

Page 857: ...es effect at the beginning of the next frame Ethernet HDLC and transparent or at the beginning of the next BD See Appendix A ÒByte Ordering Ó 00 Reserved 01 PowerPC little endian 1x Big endian or true little endian 5Ð7 AT 1Ð3 Address type 1Ð3 Contains the user deÞned function code value used during the SDMA channel memory access AT0 is always driven high to identify this channel access as a DMA ty...

Page 858: ...r closes The CPM updates this Þeld after the received data is placed into the associated buffer Memory allocated for this buffer should be no smaller than MRBLR Ñ For a TxBD this is the number of octets the CPM should transmit from its buffer Normally this value should be greater than zero The CPM never modiÞes this Þeld The word at offset 4 points to the beginning of the buffer Ñ For an RxBD the ...

Page 859: ...s RxBD and its buffer Once E is set the core should not write any Þelds of this RxBD 1 Ñ Reserved and should be cleared 2 W Wrap last BD in table 0 Not the last BD in the RxBD table 1 Last BD in the RxBD table After this buffer is used the CPM receives incoming data using the BD pointed to by RBASE top of the table The number of BDs in this table is determined only by the W bit and overall space c...

Page 860: ...the buffer is serviced If enabled an interrupt occurs 4 L Last 0 This buffer does not contain the last character of the message 1 This buffer contains the last character of the message After sending this buffer the transmitter generates a stop condition and deactivates Retrigger I2COM STR to initiate a new transmission 5 S Generate start condition Provides ability to send back to back messages on ...

Page 861: ...the core There are two handshake options for strobed I O Ñ Two interlocked handshake signals Supports level sensitive handshake control signals compatible with the advanced byte transfer mode of the P1284 protocol see Section 33 7 1 ÒInterlocked Handshake Mode Ó Ñ Two pulsed handshake signals Supports edge sensitive handshakes like those used for a Centronics interface see Section 33 7 2 ÒPulsed H...

Page 862: ... a character has arrived When software reads the port B data register PBDAT the PIP asserts ACK through STBO strobe out on PB15 When the PIP is conÞgured to send and the core writes PBDAT STB is driven low on STBO strobe out on PB15 When the destination device drives ACK low onto STBI strobe in on PB14 the PIP indicates that a character was successfully sent by ßagging PIPE TCH For a core controll...

Page 863: ...s to parameter RAM values after initialization because activity centers around the buffer descriptors Table 33 1 PIP Transmitter Parameter RAM Memory Map Offset1 Name Width Description 0x00 Ñ Hword Reserved for receiving 0x02 TBASE Hword PIP TxBD table base offset from the beginning of dual port RAM Initialize TBASE before enabling the channel TBASE should be divisible by 8 0x04 PFCR Byte PIP func...

Page 864: ... reading the individual status signals for errors When receiving core software drives the status signals using general purpose outputs Bit 0 1 2 3 4 5 6 7 Field Ñ BO AT 1Ð3 Reset 0000_0000_0000_0000 R W R W Addr PIP base 0x04 Figure 33 2 PIP Function Code Register PFCR Table 33 2 PFCR Field Descriptions Bits Name Description 0Ð2 Ñ Reserved and should be 0 3Ð4 BO Byte ordering Set BO to select the ...

Page 865: ...1 SELECT status line is checked during transmission If a select error occurs indication is given in TxBD S and a TXE event is generated in the PIPE 7 Ñ Reserved Should be 0 Table 33 4 PIP Receiver Parameter RAM Memory Map Offset 1 Name Width Description 0x00 RBASE Hword PIP Rx BD table base offset from the beginning of dual port RAM Initialize RBASE before enabling the channel RBASE should be divi...

Page 866: ... controller can be programmed to close the Rx buffer after a period of inactivity determined by MAX_SL The silence counter decrements every 1 024 system clocks If the counter reaches zero before new data arrives the Rx buffer closes Clearing MAX_SL disables this function 0x2A SL_CNT Hword Silence counter Internal use 0x2C CHARACTER1 Hword Control character table The PIP receiver uses this 8 entry ...

Page 867: ... is in the message A maskable interrupt is generated 1 If this character is recognized it is written to RCCR and not to the Rx buffer A maskable interrupt is generated The current Rx buffer is not closed 2Ð7 Ñ Reserved 8Ð15 CHARACTERn Control character values 1Ð8 DeÞnes control characters to be compared to the incoming character For characters smaller than 8 bits the most signiÞcant bits should be...

Page 868: ...before using SBSY or CBSY Note that PIPC T R should be cleared receiving if SBSY or CBSY are used 7 EBSY Enable BUSY The bit deÞnition depends on whether T R is set to receive or transmit BUSY is not affected by MODL programming if EBSY 1 T R 0 Receiving 0 Disable BUSY signal generation on PB31 for the receiver 1 Enable the BUSY output on PB31 EBSY takes effect only if BUSY is conÞgured as a PIP o...

Page 869: ...transferring data 00 Port B general purpose I O PIP disabled 01 Transparent transfer modeÑcontrolled by the CP 10 Interlocked handshake modeÑcontrolled by the CP or core 11 Pulsed handshake modeÑcontrolled CP or core 14 HSC Host control 0 The CP controls transfers using PIP parameter RAM buffer descriptors and SDMA channels 1 PIP data transfers are controlled by the core 15 T R Transmit receive Se...

Page 870: ...RCH TCH Character received transmitted Indicates that a data character has been sent or received Used to generate interrupts to the core if the PIP is conÞgured to be controlled by core software 7 RXB TXB Rx Tx buffer Under CP control indicates that the PIP controller has closed the current buffer due to one of the following events the transfer byte count reaches zero for Rx and Tx a user deÞned c...

Page 871: ... 2 ÒPort B Data Register PBDAT Ó Port B open drain register ConÞgures the data signals PBDAT 16Ð31 as normal or wired OR See Section 34 3 1 1 ÒPort B Open Drain Register PBODR Ó 33 5 PIP Buffer Descriptors The CP uses PIP receive and transmit buffer descriptors to manage the speciÞc transfer of each buffer Each 64 bit buffer descriptor has the following structure The half word at offset 0 contains...

Page 872: ...nsmit a buffer that is not ready PIPE TXE is ßagged 0 The buffer associated with this descriptor is not ready for transmission This descriptor and its buffer can be updated The CP clears R after the buffer is sent or an error is encountered 1 The buffer is ready for sending or is being sent No Þelds of this BD can be written while R 1 1 Ñ Reserved and should be cleared 2 W Wrap last buffer descrip...

Page 873: ... W I C Ñ CM SL Ñ Offset 2 Data Length Offset 4 Rx Buffer Pointer Offset 6 Figure 33 10 PIP Rx Buffer Descriptor RxBD Table 33 10 PIP RxBD Status and Control Field Descriptions Bits Name Description 0 E Empty 0 The buffer associated with this descriptor is full or stopped receiving data because an error occurred The core can read or write any Þelds of this RxBD The CP cannot use this BD while E is ...

Page 874: ...mmands Command Description STOP TRANSMIT Disables transmission of frames on the transmit channel If the PIP controller receives this command during frame transmission transmission stops and the TBPTR is not advanced to the next BD No new BD is accessed and no new buffers are sent for this channel The transmitter idles until RESTART TRANSMIT is issued RESTART TRANSMIT Used to begin or resume sendin...

Page 875: ...ollowing subsections describe interlocked and pulsed handshake modes 33 7 1 Interlocked Handshake Mode The interlocked handshake mode provides a fast connection between MPC860s and can be used for P1284 protocol advanced byte mode transfers To connect MPC860s using this interface connect STBO from one 860 to the STBI of the other and connect the appropriate data signals either PB 23Ð16 or PB 31Ð16...

Page 876: ...ses STB to latch input data and ACK to acknowledge the transfer The timing of ACK is also programmable The core conÞgures the PIP to implement a Centronics protocol by programming the PIP conÞguration PIPC register When the PIP is under CP control timing attributes are set in PTPR Transmit and receive errors are reported through BDs For information about supporting a Centronics interface see Secti...

Page 877: ...n also control the assertion and negation of BUSY via PIPC see Section 33 4 1 ÒPIP ConÞguration Register PIPC Ó BUSY is multiplexed onto PB31 It can be used only with the 8 bit PIP interface not the 16 bit interface A PIP transmitter can be conÞgured to ignore BUSY or suspend assertion of the STB output until the receiver BUSY signal is negated 33 7 2 2 Pulsed Handshake Timing When the PIP is unde...

Page 878: ...relative timing of BUSY to ACK Figure 33 15 through Figure 33 18 show how the deÞnitions of TPAR1 and TPAR2 vary for each receiver mode The receiver mode is selected in PIPC TMOD see Table 33 6 Figure 33 15 PIP Receiver TimingÑMode 0 Figure 33 16 PIP Receiver TimingÑMode 1 Figure 33 17 PIP Receiver TimingÑMode 2 STB Data TPAR1 TPAR2 ACK BUSY TPAR1 TPAR2 PB31 ACK BUSY TPAR1 TPAR2 PB31 ACK BUSY TPAR...

Page 879: ...nerates the request to the CP causing it to send or receive data Signal direction is controlled by the port B data direction register PBDIR 14 Figure 33 19 PIP Transparent Transfers 33 9 Implementing Centronics The PIP can implement a Centronics compatible interface for both sending and receiving The Centronics protocol is a parallel peripheral interface for communicating between a host computer a...

Page 880: ...ble receive control character comparison Flexible timing modes with programmable timing parameters Figure 33 20 shows the signals needed to implement a standard Centronics interface Figure 33 20 The PIP Centronics Interface Signals The following subsections describe the PIP conÞgured as a Centronics interface 33 9 1 PIP as a Centronics Transmitter Once the TxBDs are prepared and PIPC STR is set th...

Page 881: ...ns only the character based TCH interrupt applies Table 33 13 Centronics Tx Errors Error Description BD Not Ready The current BD to be processed is not ready PIPE TXE is ßagged The channel continues sending after S W prepares the BD and sets PIPC STR Printer Off Line The printer is off line TxBD S and PIPE TXE are ßagged The channel resumes sending after RESTART TRANSMIT Note that SMASK S must be ...

Page 882: ...nd BUSY handshake signals on the Centronics interface The ACK pulse width and the timing of BUSY with respect to ACK are determined by the timing parameter register PTPR Figure 33 22 shows the PIP conÞgured as a Centronics receiver The SELECT PERROR and FAULT signals shown are not automatically generated they are controlled by software and driven on general purpose outputs Figure 33 22 PIP as a Ce...

Page 883: ...upt controller CPIC Port D is shared with the RXD and TXD signals of SCC 3Ð4 TDM signals and Ethernet CAM support signals The read write port signals can be conÞgured as inputs or outputs with a latch for data output They can be conÞgured to be either general purpose I O or dedicated peripheral signals Regardless of the programmed function the I O signalsÕ state can always be read from their data ...

Page 884: ...t A Port A signals are conÞgured as follows in the port A pin assignment register PAPAR General purpose I O signal the corresponding PAPAR DDn 0 Dedicated on chip peripheral signal PAPAR DDn 1 PAPAR and the port A data direction register PADIR are cleared at reset thus conÞguring all port A signals as general purpose input signals Table shows defaults for port A signal options Table 34 1 Port A Pi...

Page 885: ...ODR bits conÞgure the signals for open drain operation 1 Clearing the corresponding PADIR bit makes the signal an input setting PADIR makes it an output 2 Available for MPC860 Rev B and later only when PA9 or PA8 is not used as RXD4 or TXD4 functions 3 Available for MPC860 Rev B and later 4 Multi function peripheral input signals such as CLK1 TIN1 L1RCLKA can perform multiple functions simultaneou...

Page 886: ...a direction register PADIR bits conÞgure port A signals as general purpose inputs or outputs If a signal is not programmed for general purpose I O PADIR selects the peripheral function to be performed Table 34 2 PAODR Bit Descriptions Bits Name Description 0Ð7 13 15 Ñ Reserved always reads as 0 8Ð12 14 ODn Tells how the corresponding port A signal is interpreted 0 The signal is actively driven as ...

Page 887: ...s or outputs when functioning as general purpose I O otherwise used to select the peripheral function 0 Select the signal for general purpose input or select peripheral function 0 1 Select the signal for general purpose output or select peripheral function 1 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 Reset 0 0 0 0 0 0 0 0 0...

Page 888: ... PA14 and PAODR OD14 1 TXD1 is an open drain output from SCC1 PA11 can be conÞgured as a general purpose I O and an open drain signal It can also be the L1TXDB signal for TDMb if PADIR DR11 is a 1 PA7 can be conÞgured as a general purpose I O signal but not an open drain signal Ñ If PADIR DR7 0 PA7 can also be CLK1 TIN1 L1RCLKA or all three The connections are made separately in the serial interfa...

Page 889: ...signals with open drain capability Figure 34 6 Block Diagram for PA14 True for all Open Drain Port Signals MUX 0 1 EN MUX 0 1 EN MUX 0 1 EN EN 16 Bits 16 Bits PAPAR PADIR Output Latch EN Write Path From PADAT 15 Read Path To PADAT 15 To SCC1 RXD1 RXD1 PA15 Pin MUX 0 1 EN MUX 0 1 EN MUX 0 1 EN EN 16 Bits 16 Bits PAPAR PADIR Output Latch EN Open Drain 16 Bits PAODR Control EN Read Path To PADAT 14 W...

Page 890: ...nto the port signal When PBDAT is read the port signal itself is read All port B signals can have multiple conÞgurations which include on chip peripheral functions for SPI I2C SMCs and the TDMs Port B is also multiplexed with the PIP which can implement fast parallel interfaces For a description of the dedicated PIP signal functions see Chapter 33 ÒParallel Interface Port Ó PB 26Ð28 and PB 15 are ...

Page 891: ...t B22 SMSYN2 SDACK2 SMSYN2 GND PB21 Port B21 SMTXD2 L1CLKOB Ñ PB20 Port B20 SMRXD2 L1CLKOA SMRXD2 GND PB19 Port B19 L1ST1 RTS1 Ñ PB18 Port B18 L1ST2 RTS2 Ñ PB17 Port B17 L1ST3 RTS31 L1RQb Ñ PB16 Port B16 L1ST4 RTS41 L1RQa Ñ PB15 Port B15 Ñ BRGO3 Ñ PB14 Port B14 Ñ RSTRT1 Ñ Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ Reset 0000_0000_0000_0000 R W Ñ Addr 0xAC0 Bit 16 17 18 19 20 21 22 23 24 25 ...

Page 892: ...r outputs If a signal is not programmed for general purpose I O PBDIR selects the peripheral function to be performed Table 34 7 PBODR Bit Descriptions Bits Name Description 0Ð15 Ñ Reserved 16Ð31 ODn Port B open drain conÞguration 0 The I O signal is actively driven as an output 1 The I O signal is an open drain driver As an output the signal is actively driven low Otherwise it is three stated Not...

Page 893: ...ister PBDIR Table 34 9 PBDIR Bit Descriptions Bits Name Description 0Ð13 Ñ Reserved 14Ð31 DRn Port B data direction ConÞgures port B signals as inputs or outputs when functioning as general purpose I O otherwise used to select the peripheral function 0 Select the signal for general purpose input or select peripheral function 0 1 Select the signal for general purpose output or select peripheral fun...

Page 894: ...10 PBPAR Bit Descriptions Bits Name Description 0Ð13 Ñ Reserved 14Ð31 DDn Port assignment Determines whether a signal is conÞgured for general purpose I O or dedicated peripheral function 0 General purpose I O The peripheral functions of the signal are not used 1 Dedicated peripheral function The signal is used by the internal module The on chip peripheral function to which it is dedicated can be ...

Page 895: ...ter The following steps can be taken to conÞgure a port C signal as a general purpose input signal that does not generate an interrupt 1 Write the corresponding PCPAR bit with a zero 2 Write the corresponding PCDIR bit with a zero 3 Write the corresponding PCSO bit with a zero 4 The corresponding PCINT bit is a ÔdonÕt careÕ bit 5 Write the corresponding CIMR bit with a zero to prevent interrupts f...

Page 896: ...INT bit to determine which edges cause interrupts 5 Write the corresponding CIMR bit with a 1 so that interrupts can be sent to the core 6 The signal value can be read at any time using the PCDAT register After connecting CTS or CD to the SCC choose normal operation mode in GSMR DIAG to enable or disable SCC transmission and reception with these signals PC14 and PC15 can be programmed to assert sp...

Page 897: ...eral purpose I O or dedicated for use with a peripheral Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ D4ÐD15 Reset 0 R W R W Addr 0x966 Figure 34 11 Port C Data Register PCDAT Table 34 12 PCDAT Bit Descriptions Bits Name Description 0Ð3 Ñ Reserved 4Ð15 Dn Contains the data on the corresponding signal Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ DR4ÐDR15 Reset 0000_0000_0000_0000 R W R W A...

Page 898: ...se I O or for dedicated peripheral function 0 General purpose I O The peripheral functions of the signal are not used 1 Dedicated peripheral function The signal is used by the internal module The on chip peripheral function to which it is dedicated can be determined by other bits Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ Ñ Ñ Ñ CD4 CTS4 CD3 CTS3 CD2 CTS2 CD1 CTS1 Ñ Ñ DREQ1 DREQ0 Reset 0 R W...

Page 899: ...as controlled by the PCINT bits 1 PCx is connected to the corresponding SCC input as well as being a general purpose interrupt signal 14Ð15 DREQx Enable DMA request to the CPM Set DREQx only if IDMA is being used Note that the IDMA request function and the general purpose interrupt function operate concurrently and independently 0 PCx is a general purpose interrupt I O signal If PCDIR conÞgures th...

Page 900: ...ss of whether it is an input or output This allows output conßicts to be found on the signal by comparing the written data with the data on the signal A write to a PDDAT bit is latched and if conÞgured as an output is driven onto its respective signal PDDAT can be read or written at any time PDDAT is not initialized and is undeÞned by reset Table 34 17 Port D Pin Assignment Signal Pin Function PDP...

Page 901: ... 5 6 7 8 9 10 11 12 13 14 15 Field Ñ D3ÐD15 Reset UndeÞned R W R W Addr 0x976 Figure 34 16 Port D Data Register PDDAT Table 34 18 PDDAT Bit Descriptions Bits Name Description 0Ð2 Ñ Reserved 3Ð15 Dn Contains the data on the corresponding signal Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ DR3 DR4 DR5 DR6 DR7 DR8 DR9 DR10 DR11 DR12 DR13 DR14 DR15 Reset 0000_0000_0000_0000 R W R W Addr 0x970 Fig...

Page 902: ...ptions Bits Name Description 0Ð2 Ñ Reserved and must be cleared Note that setting bits 0 or 1 causes erratic behavior resulting in CPM lockup These bits apply only for the MPC860SAR 3Ð15 DDn ConÞgures a signal for general purpose I O or for dedicated peripheral function 0 General purpose I O The peripheral functions of the signal are not used 1 Dedicated peripheral function The signal is used by t...

Page 903: ...ly generated by controllers such as the SCCs SMCs SPI and I2C but also include the 12 general purpose timers and port C parallel I O signals described in Section 34 4 ÒPort C Ó More than one of these sources may generate interrupts at the same time therefore the CIMR register is provided for masking individual sources Additional masking is provided for speciÞc interrupt events within each controll...

Page 904: ... source is pending the CPIC sends an interrupt request to the SIU at the interrupt level speciÞed in CICR IRL The CPIC then waits for the interrupt to be recognized The core honors the interrupt request and then acknowledges the interrupt by setting the IACK bit in the CPM interrupt vector register CIVR When CIVR IACK is set the contents of CIVR VN are updated with the 5 bit vector corresponding t...

Page 905: ...al sources are described in Section 34 4 1 5 ÒPort C Interrupt Control Register PCINT Ó 2 SCCs can be programmed to any of these locations Group and spread are described in Section 35 2 1 ÒProgramming Relative Priority Grouping and Spreading Ó Table 35 1 Prioritization of CPM Interrupt Sources Priority Source Description Multiple Events Priority Source Description Multiple Events 0x1F Highest Para...

Page 906: ...nd the request is cleared The next request can be presented to the core When the interrupt is taken the external interrupt enable bit of the coreÕs machine state register MSR EE is cleared to disable further interrupt requests until software can handle them The CPM interrupt in service register CISR can be used to allow a higher priority interrupt within the same interrupt level to be presented to...

Page 907: ...ear MSR EE Disable external interrupts to the core 2 Modify the mask register 3 Set MSR EE Enable external interrupts to the core This mask modiÞcation procedure ensures that an already pending interrupt is not masked before being serviced Masking a pending interrupt causes the interrupt error vector see Table 35 2 to be issued if no other valid CPM interrupts are pending The error vector cannot b...

Page 908: ...CIMR ÑCan be used to mask CPM interrupt sources CPM interrupt in service register CISR ÑAllows nesting interrupt requests within the CPM interrupt level Note that the names and placement of bits is identical in the CIPR CIMR and CISR Table 35 2 Interrupt Vector Encodings Interrupt Number Source Description CIVR 0Ð4 Interrupt Number Source Description CIVR 0Ð4 0x1F Parallel I OÐPC15 11111 0x0F Para...

Page 909: ... in the SCCd position 10Ð11 SCcP1 SCCc priority order DeÞnes which SCCs asserts its request in the SCCc priority position 00 SCC1 asserts its request in the SCCc position 01 SCC2 asserts its request in the SCCc position 10 SCC3 asserts its request in the SCCc position 11 SCC4 asserts its request in the SCCc position 12Ð13 SCbP1 SCCb priority order DeÞnes which SCCs that asserts its request in the ...

Page 910: ...namically 19Ð23 HP Highest priority SpeciÞes the 5 bit interrupt number of the CPIC interrupt source that is advanced to the highest priority in the table These bits can be modiÞed dynamically Programming HP 0b11111 keeps PC15 the highest priority source for external interrupts to the core 24 IEN Interrupt enable Master enable for CPM interrupts 0 CPM interrupts are disabled 1 CPM interrupts are e...

Page 911: ...the corresponding CIPR bit is set when an interrupt condition occurs but the interrupt request is not passed to the core If a CPM interrupt source is requesting interrupt service when its CIMR bit is cleared the request stops If the bit is set later the core processes previously pending interrupt requests according to priority The CIMR SCCx bit positions are unaffected by the relative priority pro...

Page 912: ...ibes CIVR Þelds Section 35 6 ÒInterrupt Handler ExampleÑ Single Event Interrupt Source Ó and Section 35 7 ÒInterrupt Handler ExampleÑ Multiple Event Interrupt Source Ó show how CIVR Þelds are used 35 6 Interrupt Handler ExampleÑSingle Event Interrupt Source In this example the CPIC hardware clears CIPR PC6 during the interrupt acknowledge cycle The following steps show how to handle an interrupt s...

Page 913: ...it 1 Set the CIVR IACK 2 Read CIVR VN to determine the vector number for the interrupt handler 3 Immediately read the SCC2 event register into a temporary location 4 Decide which events in the SCCE2 must be handled and clear those bits as soon as possible SCCE bits are cleared by writing ones 5 Handle the events in the SCC2 Rx BD or Tx BD tables 6 Clear CISR SCC1 7 Execute the rfi instruction If a...

Page 914: ...35 12 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 915: ...bis and V 34 Data and function parameters formatted by the core using function descriptors FDs DSP routines are core initiated using CP commands INIT DSP and START DSP Maskable interrupts issued to the core upon completion of DSP routines The following summarizes the DSP features of the CPM 16 bit 16 bit multiply and accumulate MAC engine Ñ Two 40 bit accumulators with overßow saturation logic Ñ T...

Page 916: ...once the CPM executes the chain Table 36 1 lists the available DSP functions with opcodes Table 36 1 DSP Library Functions Function Opcode Input CoefÞcient Output Application FIR1 00001 Real Real Real Decimation Rx interpolation FIR2 00010 Complex Real Complex Tx Þlter Rx Þlter FIR3 00011 Complex Complex Real Complex EC computation equalizer FIR5 00101 Complex Complex Real Complex Fractionally spa...

Page 917: ...function descriptor FD consists of eight 16 bit entries The Þrst entry contains status and control bits including the function opcode The remaining seven entries contain the functionÕs parameter packet Figure 36 3 shows the general structure of an FD Table 36 2 describes the status and control bits All of the library functions use the stop wrap and interrupt bits The use of the remaining control b...

Page 918: ...ed 1 A maskable interrupt is generated after this function is processed 4 X Complex number option Used to specify a real complex output or a real complex scalar for LMS 0 Use only the real component 1 Use both the real and imaginary components 5 IALL Auto increment X for all iterations 0 X input data pointer is incremented Modulo M 1 by the number of samples speciÞed in FD INDEX after the last ite...

Page 919: ... coefÞcient buffer pointers are 16 bit offsets from the base of the dual port RAM These include CBASE and the buffer pointers in the structures pointed to by XPTR and XYPTR The structures pointed to by XPTR and XYPTR consist of a halfword aligned array of the 16 bit pointers as deÞned by the particular DSP library function 36 7 DSP Parameter RAM Two areas of the dual port RAM hold the DSP paramete...

Page 920: ...FD pointer 0x08 DSTATE Word DSP state 0x0C Ñ Word Reserved 0x10 DSTATUS Hword Current FD status 0x12 I Hword Current FD number_of_iterations 0x14 TAP Hword Current FD number_of_taps 0x16 CBASE Hword Current FD coefÞcient buffer base 0x18 Ñ Hword Current FD sample buffer_size 1 0x1A XPTR Hword Current FD pointer to input buffer 0x1C Ñ Hword Current FD output buffer_size 1 0x1E YPTR Hword Current FD...

Page 921: ...ary Functions The DSP library provides Þve basic Þnite impulse response Þlters each specializing in a different combination of real or complex coefÞcients input samples and output The following sections describe each variety of FIR Þlter Table 36 6 shows the parameter packet common to all FIR Þlters Bit 0 1 2 3 4 5 6 7 Field SBER RINT Ñ DSP2 DSP1 Reset 0 R W R W Addr 0x908 SDSR 0x90C SDMR Figure 3...

Page 922: ...es are stored in order in a circular buffer containing M 1 bytes The 16 bit outputs are stored consecutively in a circular buffer containing N 1 bytes See Table 36 7 1 Offset from base of the FD Table 36 6 FIR Parameter Packet Offset 1 Name Description 0x2 I Number of iterations 0x4 K Number_of_taps 1 The number of taps should be a multiple of four 0x6 CBASE Filter coefÞcient vector base address 0...

Page 923: ...5 6 7 8 9 10 11 12 13 14 15 Offset 0x0 S Ñ W I Ñ IALL INDEX PC Ñ Ñ 00001 Offset 0x2 I Offset 0x4 K Offset 0x6 CBASE Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 9 FIR1 Function Descriptor Table 36 8 FIR1 Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 K Number_of_taps 1 The number of taps should be a multiple of four Hword 3 CBASE Filter coefÞc...

Page 924: ...unction 36 11 2 1 FIR2 CoefÞcient Input and Output Buffers The coefÞcient vector occupies K 16 bit entries in memory and C 0 is stored in the Þrst location The input sample buffer is a circular buffer that contains M 1 bytes and each input sample is two 16 bit entries real and imaginary components The next sample is stored in the address that follows the previous sample The output buffer is a circ...

Page 925: ...0 Table 36 9 FIR2 Coefficient Input and Output Buffers CoefÞcients Input Samples Output C 0 C 1 C 2 imaginary x n k 1 imaginary Y n k 1 real x n k 1 real Y n k 1 C k 1 imaginary x n 2 imaginary Y n 2 real x n 2 real Y n 2 imaginary x n 1 imaginary Y n 1 real x n 1 real Y n 1 imaginary x n imaginary Y n real x n real Y n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 S Ñ W I Ñ IALL INDEX PC Ñ Ñ 000...

Page 926: ...s and real or complex output The input data is in a circular buffer with size M 1 and the output data is in a circular buffer with size N 1 Table 36 10 FIR2 Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 K Number_of_taps 1 Hword 3 CBASE Filter coefÞcient vector base address Hword 4 M Input buffer_size 1 The minimum input buffer size is 8 4 samples Hword 5 XYPTR Po...

Page 927: ...hat contains N 1 bytes and each output is two 16 bit entries real and imaginary components The next output is stored in the address that follows the previous output See Table 36 11 Table 36 11 FIR3 Coefficient Input and Output Buffers CoefÞcients Input Samples Complex Output FD X 1 Real Output FD X 0 imaginary C 0 real C 0 imaginary C 1 imaginary x n k 1 imaginary Y n k 1 Y n k 1 real C 1 real x n...

Page 928: ...ffset 0x4 K Offset 0x6 CBASE Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 15 FIR3 Function Descriptor Table 36 12 FIR3 Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 K Number_of_taps 1 Hword 3 CBASE Filter coefÞcient vector base address Hword 4 M Input buffer_size 1 The minimum input buffer size is 8 2 samples Hword 5 XYPTR Pointer to a struct...

Page 929: ...memory and C 0 is stored in the Þrst location The input sample buffer is a circular buffer containing M 1 bytes Each input sample is two 16 bit entries real and imaginary components and the next sample is stored in the address that follows the previous sample The output buffer is a circular buffer that contains N 1 bytes and the next output is stored in the address that follows the previous output...

Page 930: ...aginary Y n real x n real Y n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 S Ñ W I X IALL INDEX PC Ñ Ñ 00101 Offset 0x2 I Offset 0x4 K Offset 0x6 CBASE Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 18 FIR5 Function Descriptor Table 36 14 FIR5 Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 K Number_of_taps 1 Hword 3 CBASE Filter coefÞcient vec...

Page 931: ...The coefÞcient vector occupies K pairs of 16 bit entries real and imaginary components in memory and C 0 is stored in the Þrst location The input sample buffer is a circular buffer containing M 1 bytes and each sample is a 16 bit entry The next sample is stored in the address that follows the previous sample The output buffer is a circular buffer that contains N 1 bytes and the next output is stor...

Page 932: ...ginary C 0 real C 0 imaginary C 1 x n k 1 imaginary Y n k 1 real C 1 real Y n k 1 x n 2 imaginary C k 1 x n 1 imaginary Y n 2 real C k 1 x n real Y n 2 imaginary Y n 1 real Y n 1 imaginary Y n real Y n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 S Ñ W I Ñ IALL INDEX PC Ñ Ñ 00110 Offset 0x2 I Offset 0x4 K Offset 0x6 CBASE Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 21 FIR6 ...

Page 933: ... coefÞcient vector occupies six 16 bit entries in memory and C 0 is stored in the Þrst location C 1 is only used in the last stage of a cascaded IIR Þlter The input sample buffer is a circular buffer that contains M 1 bytes The next sample is stored in the address that follows the previous one The output buffer is a circular buffer that contains N 1 bytes and the next output is stored in the addre...

Page 934: ... Ñ 00111 Offset 0x2 I Offset 0x4 TPTR Offset 0x6 CBASE Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 23 IIR Function Descriptor Table 36 18 IIR Parameter Packet Address Name Description Hword 1 I Number of iterations cascaded stages Hword 2 TPTR Pointer to a structure of temporary variables used by the delay line blocks The structure consists of two real numbers and can be left...

Page 935: ...K 1 bytes in memory The input sample buffer is a circular buffer containing M 1 bytes Each sample is a pair of 16 bit entries real and imaginary components and the next sample is stored in the address that follows the previous sample The output buffer is a circular buffer that contain N 1 bytes and the next output is stored in the address that follows the previous output The output buffer can be r...

Page 936: ... Offset 0 S Ñ W I X Ñ 01000 Offset 0x2 I Offset 0x4 K Offset 0x6 MPTR Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 25 MOD Function Descriptor Table 36 20 MOD Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 K Modulation table_size 1 The minimum modulation table size is 8 2 sin cos pairs Hword 3 MPTR Pointer to modulation table Hword 4 M Input bu...

Page 937: ...of 16 bit cosine and sine pairs that occupy K 1 bytes in memory The input sample buffer is a circular buffer containing M 1 bytes The next 16 bit sample is stored in the address that follows the previous sample The output buffer is a circular buffer that contains N 1 bytes and the next output is stored in the address that follows the previous output TheAGC constant is in the range 1 AGC 1 See Tabl...

Page 938: ...fset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 28 DEMOD Function Descriptor Table 36 22 DEMOD Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 K Modulation table_size 1 The minimum modulation table size is 8 2 sin cos pairs Hword 3 DPTR Pointer to a structure consisting of the modulation table pointer and the AGC constant real Hword 4 M Input buffer...

Page 939: ...The coefÞcient vector occupies K pairs of 16 bit entries real and imaginary components in memory and C 0 is stored in the Þrst location The input sample buffer is a circular buffer that contain M 1 bytes Each sample is a pair of 16 bit entries real and imaginary components and the next sample is stored in the address that follows the previous sample S Ñ W I X Ñ OPCODE Offset 0 S 0 W I 0 0 01001 Of...

Page 940: ...inter is incremented by two which is required for fractionally spaced equalizer updates The coefÞcients and input samples are complex numbers but the scalar is a real or complex number Figure 36 32 LMS2 Function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 S Ñ W I X Ñ INDEX Ñ Ñ Ñ 01010 Offset 0x2 Ñ Offset 0x4 K Offset 0x6 CBASE Offset 0x8 M Offset 0xA XPTR Offset 0xC EPTR Offset 0xE Ñ Figure 36 ...

Page 941: ... sample is stored in the address that follows the previous sample 36 16 2 LMS2 Function Descriptor The LMS2 function descriptor is shown in Figure 36 33 Table 36 25 LMS2 Coefficients and Input Buffers CoefÞcients Input Samples imaginary C 0 real C 0 imaginary C 1 imaginary X n k 1 real C 1 real X n k 1 imaginary C k 1 imaginary X n 2 real C k 1 real X n 2 imaginary X n 1 real X n 1 imaginary X n r...

Page 942: ...he two input vectors X1 and X2 Figure 36 34 WADD Function 36 17 1 WADD CoefÞcients and Input Buffers Each input vector is stored in a circular buffer containing M 1 bytes Each sample is a 16 bit entry and the next sample is stored in the address that follows the previous sample The output buffer is a circular buffer that contains N 1 bytes Each output is 16 bits and the newest output is stored in ...

Page 943: ...ples Output x1 n k 1 x2 n k 1 Y n k 1 x1 n 1 x2 n 1 Y n 1 x1 n x2 n Y n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Offset 0 S Ñ W I 0 01100 Offset 0x2 I Offset 0x4 a Offset 0x6 b Offset 0x8 M Offset 0xA XYPTR Offset 0xC N Offset 0xE Ñ Figure 36 35 WADD Function Descriptor Table 36 28 WADD Parameter Packet Address Name Description Hword 1 I Number of iterations Hword 2 a X1 weight coefÞcient Hword 3 b X...

Page 944: ...tionÑTx Filter 36 18 1 Tx Filter Example Core Only Implementing the Þlter using the following C code on the core takes 476 instructionsÑ371 for the Þlter and 105 for the modulation The transmission symbol rate requires running the Þlter 2 400 times a second Thus implementing the Þlter in software alone requires the core to execute 1 14 million instructions per second void tx_filter S16 coefr S16 s...

Page 945: ...lt sn1800 REAL cosindx modbuf REAL i mult sn1800 IMAG cosindx modbuf IMAG i cosindx if cosindx SIN1800TBL_LEN cosindx 0 i void main tx_filter modulator 36 18 2 Tx Filter Example Core and CPM Implementing the Þlter using the CPM functions the user software builds a static FD chain of two functionsÑan FIR and a MOD The core activates the CPM to execute the chain with a single write to the CP command...

Page 946: ...ion Figure 36 37 shows a conceptual view of the Þlter implementation followed by example code Figure 36 37 Core and CPM Implementation of Filter Example Function Descriptors typedef struct dsp_fd unsigned short status unsigned short parameter 7 DSP_FD define WRAP 0x2000 wrap bit define INTR 0x1000 interrupt on completion define for function opcodes define FIR_2 0x0102 FIR2 filter define MOD 0x0008...

Page 947: ...ch function including overhead for context switching handling the FD and initialization As seen in Table 36 30 the CPM loading from DSP applications depends on which functions are called and their parameters The frequency with which the functions are called also affects CPM loading Table 36 30 DSP Function Execution Times Function Execution Time FIR1 53 20 i 1 1 25 i k 1 FIR2 47 17 i 1 3 i k 1 FIR...

Page 948: ...36 34 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...

Page 949: ...n systems control Chapter 38 ÒIEEE 1149 1 TestAccess Port Ó describes the dedicated user accessible test access port TAP which is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architectu...

Page 950: ...mple MSR LE refers to the little endian mode enable bit in the machine state register x In certain contexts such as in a signal encoding or a bit Þeld indicates a donÕt care n Indicates an undeÞned numerical value Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document Note that the meanings for some acronyms such as SDR1 and DSISR are historical and the words ...

Page 951: ... MPC860 is programmed to operate in serialized mode with all fetch cycles shown on the external bus Although instruction ßow tracking is simpler performance is much lower than in regular mode Section 37 5 1 3 ÒInstruction Support Control Register ICTRL Ó describes programming of the core to operate in this mode The MPC860 implements a prefetch queue combined with parallel out of order and pipeline...

Page 952: ...gram trace cycle is deÞned The program trace cycle attribute is attached to all fetch cycles resulting from indirect ßow changes When program trace recording is required the user can ensure these cycles are visible on the external bus The core can be forced to show all fetch cycles marked with the program trace cycle attribute either by setting TECR VSYNC of the development port or by programming ...

Page 953: ...trol Bits Show Cycles Generated X 000 All fetch cycles X X01 All change of ßow direct and indirect X X10ÑEnable STS functionality of OP2 MODCK1 STS by writing 10 or 11 to SIUMCR DBGC The external bus address should be sampled only when STS is asserted All indirect change of ßow 0 X11 No show cycles are performed 1 X11 All indirect change of ßow Table 37 2 Status Pin Groupings Pins Description VF 0...

Page 954: ...tions Flushed VF Next Cycle Holds 000 None Instruction type information 001 One instruction was ßushed from the instruction queue Instruction type information 010 Two instructions were ßushed from the instruction queue Instruction type information 011 Three instructions were ßushed from the instruction queue Instruction type information 100 Four instructions were ßushed from the instruction queue ...

Page 955: ...ch target Therefore when one of these special instructions is detected in the core the address of the next instruction is externally visible The reconstructing software can now correctly evaluate the effect of these instructions 37 1 5 Reconstructing Program Trace When program trace is needed external hardware must sample the status pins VF and VFLS of every clock and mark the address of all cycle...

Page 956: ...vent that marks the start of the trace window using the registers deÞned in Section 37 2 ÒWatchpoints and Breakpoints Support Ó 3 Enable debug mode entry for the breakpoint programmed in the DER see Table 37 25 4 Return to the regular code run refer to Section 37 3 1 7 ÒExiting Debug ModeÓ 5 The hardware generates a breakpoint when the event in question is detected and the machine enters debug mod...

Page 957: ...tween when a program trace cycle is reported as performed and the time that this cycle can be detected on the external bus When the user exitsVSYNC state through the serial interface of the development port the core delays the report of VSYNC occurring on the VF pins until all addresses marked with the program trace cycle attribute are externally visible Therefore the external hardware should stop...

Page 958: ...side of the MPC860 such as an external development system Peripherals on the external bus use the serial interface of the development port to assert the external breakpoint In the core as in other RISC processors software saves and restores machine state as part of exception handling As software saves restores the machine state MSR RI is cleared Exceptions that occur are handled by the core when M...

Page 959: ...rd and word operating modes and four byte mask bits for each comparator It can be used for integer data A match is detected only on the valid part of the data bus according to the cycleÕs size and the two address lsbs No internal breakpoint watchpoint support for unaligned words and half words L data comparators can be programmed to treat integers as signed or unsigned Combined comparator pairs to...

Page 960: ... load store bus cycles Instruction and load store breakpoints and watchpoints are handled on retirement and then reported Breakpoints and watchpoints on recovered instructions due to exceptions or missed predictions are not reported and do not change the machineÕs timing Instructions with instruction breakpoints are not executed The machine branches to the breakpoint exception routine before it ex...

Page 961: ...akpoint is asserted Instruction watchpoints and load store match events on address data enter the load store AND OR logic where load store watchpoints and breakpoints are generated Load store watchpoints when asserted can generate the load store breakpoint or decrement a counter When a counter on one load store watchpoint expires the load store breakpoint is asserted Watchpoints progress in the ma...

Page 962: ...ut signalsÑequal and less than These signals generate one of four events from each comparatorÑequal not equal greater than or less than See Section 37 2 4 2 ÒByte and Half Word Working Modes Ó Table 37 6 Instruction Watchpoints Programming Options Name Description Programming Options IW0 First instruction watchpoint Comparator A Comparators A B IW1 Second instruction watchpoint Comparator B Compar...

Page 963: ...re type programmed Therefore from the two 32 bit comparators eight match indications are generatedÑ Gmatch 0Ð3 and Hmatch 0Ð3 According to the lower bits of the address and the size of the cycle only match indications detected on bytes with valid information are validated The rest are negated If the executed cycle has a smaller size than the compare size a byte access when the compare size is word...

Page 964: ...truction breakpoint in that it is not executed before the machine branches to the breakpoint exception routine As a side effect of this behavior the value of the counter inside the breakpoint exception routine equals one and not zero as one might expect When programmed to count load store watchpoints the last instruction that decrements the counter to zero is treated like any other 1 denotes a log...

Page 965: ...In such cases only one watchpoint of a given type is reported for the instruction Similarly only one watchpoint of the same type can be counted for a single instruction Watchpoint events are reported when the instruction that caused the event retires because more than one instruction can retire in a single clock ensuing events may be reported in the same clock Moreover an event detected on more th...

Page 966: ...s than 0x9C409C40 Programming option One L address comparator 0x00000000 and program for greater than One L address comparator 0x0000000C and program for less than One L data comparator 0x4E204E20 and program for greater than One L data comparator 0x9C409C40 and program for less than Both byte masks 0x0 Both L data comparators program to half word mode Result The event will be correctly detected a...

Page 967: ...al pins regardless of the value of MSR RI In nonmaskable mode when the core is programmed to recognize internal breakpoints all parts of the code can be debugged However if an internal breakpoint is recognized when MSR RI 0 SRR0 and SRR1 are busy the machine enters a nonrestartable state See Section 7 1 5 ÒRecoverability after an Exception Ó The core defaults to maskable mode after reset The core ...

Page 968: ...d mode 1000 These boundary cases do not require special support because they are considered always true They can be programmed using the ignore option of the load store watchpoint programming See Section 37 5 1 5 ÒLoad Store Support AND OR Control Register LCTRL2 Ó 37 2 5 Load Store Breakpoint Example CMPE and CMPF are used for load store addresses while CMPG and CMPH are used for load store data ...

Page 969: ...n the core is in debug mode It is also possible to debug the core using monitor debugger software described in Section 37 4 ÒSoftware Monitor Debugger Support Ó In debug mode the core fetches all instructions from the development port data can be read from the development port and written to the development port This allows memory and registers to be read and modiÞed by a development tool emulator...

Page 970: ...trap enable bits for programming the instruction breakpoint dynamically Load store trap enable bits for programming the load store breakpoint dynamically Nonmaskable breakpoint is used to assert the nonmaskable external breakpoint Maskable breakpoint is used to assert the maskable external breakpoint VSYNC control code is used to assert and negate VSYNC operation In debug mode the development port...

Page 971: ...an be entered immediately out of reset allowing the user to debug a system without using ROM The debug enable register DER can be used to selectively enable events that cause the machine to enter debug mode The interrupt cause register ICR indicates why debug mode is entered After entry into debug mode program execution continues from the where debug mode was entered All instructions are fetched f...

Page 972: ...tchpoint breakpoint hardware remains operational and can be used for debugging by a software monitor program Figure 37 7 is a timing diagram for the enabling debug mode Figure 37 7 Debug Mode Reset Configuration Timing Diagram Note that because SRESET negation time depends on an external pull up resistor any reference to SRESET negation time in this chapter refers to the time the MPC860 releases S...

Page 973: ...he user can enable events that can initiate debug mode and determine which events require regular interrupt handling The following events can cause the core to enter debug mode Each event results in debug mode entry if debug mode is enabled and the corresponding enable bit is set in the DER The reset values of the enable bits allow use of the debug mode features without programming the DER in most...

Page 974: ...tion is asserted causing any properly programmed peripheral to stop The development port should read the value of the ICR to get the cause of the debug mode entry Reading the ICR clears all of its bits 37 3 1 3 Debug Mode Indication The fact that the core is in debug mode is broadcast to the external world using the value 0b11 on the VFLS pins Debug mode indication will also be given on the FRZ pi...

Page 975: ...ts in debug mode regardless of the value of MSR RI On entering debug mode MSR EE is cleared forcing hardware to ignore external and decrementer interrupts Note that debug software must not set MSR EE in debug mode because the external interrupt event is a level signal Because the core only reports and does not handle exceptions in debug mode core hardware does not clear MSR EE This event if enable...

Page 976: ... to be gated with the serial transmissions 37 3 2 1 2 Development Serial Data In DSDI External logic presents data to be transferred into the development port shift register at the development serial data in pin DSDI When driven asynchronously with the system clock data presented to DSDI must be stable at setup time before the rising edge of DSCK and at hold time after the rising edge of DSCK When...

Page 977: ...ment port shift register These instructions are serially loaded into the shift register from DSDI using DSCK or CLKOUT as the shift clock Similarly data is transferred to the core Data is shifted into the shift register and read by the processor by executing mfspr DPDR Data is also parallel loaded into the development port shift register from the core by executing mtspr DPDR It is then serially sh...

Page 978: ...us communications The development port supports two ways to clock serial transmissions 37 3 2 3 1 Asynchronous Clocked ModeÑUsing DSCK The Þrst clock mode is called asynchronous clocked since the input clock DSCK is asynchronous with CLKOUT To ensure that data on DSDI is sampled correctly transitions on DSDI must meet all setup and hold times with respect to the rising edge of DSCK This clock mode...

Page 979: ...ection of clocked or self clocked mode is made at reset The state of the DSDI input is latched eight clocks after negation of SRESET If it is latched low asynchronous clocked mode is enabled If it is latched high then synchronous self clocked mode is enabled The timing diagram in Figure 37 11 shows the clock mode selection after reset CLKOUT Debug port drives the ready bit onto DSDO when the core ...

Page 980: ...the development port is signaled by a start bit A mode bit in the transmission deÞnes it as either a trap enable mode transmission or a debug mode transmission If the mode bit is set the transmission will be 10 bits long and only seven data bits will be shifted into the shift register These seven bits will be latched into the TECR A control bit determines whether the data is latched into the trap ...

Page 981: ...nable mode there is no data from the core out of the development port Data out of the development port in the trap enable mode is shown in Table 37 12 Table 37 10 Trap Enable Data Shifted into Development Port Shift Register Star t Mode Control 1st 2nd 3rd 4th 1st 2nd VSYNC Function Instruction Data Watchpoint Trap Enables 1 1 0 0 Disabled 1 Enabled Transfer data to trap enable control register Ta...

Page 982: ... bit is not set Instead the port waits for the core to read the next instruction before asserting ready This allows duplex operation of the serial port and lets the port control all transmissions from the external development tool After detecting this ready status the external development tool begins transmitting to the development port with a start bit logic high on DSDI 37 3 2 5 1 Serial Data In...

Page 983: ... out 37 3 2 5 2 Serial Data Out of Development Port The encoding of data shifted out of the development port shift register in debug mode is the same as for trap enable mode as shown in Table 37 12 The valid data encoding is used when data has been transferred from the core to the development port shift register as the result of an instruction to move the contents of a GPR to the DPDR The valid da...

Page 984: ...g the execution of the previous instruction in debug mode Interrupts may occur as the result of instruction execution such as unimplemented opcode or arithmetic error because of a memory access fault or from an unmasked external interrupt When an interrupt occurs the development port ignores the command instruction or data shifted in while the interrupt encoding was shifting out The next transmiss...

Page 985: ...nal 37 4 1 Freeze Indication The internal freeze signal connects to all relevant internal modules which can be programmed to stop all operations in response to the assertion of the freeze signal To enable a software monitor debugger to broadcast the fact that debug software has executed it is possible to assert and negate the internal freeze signal when debug mode is disabled The assertion of the ...

Page 986: ... 10011 CMPD Fetch sync on write 150 00100 10110 COUNTA Fetch sync on write 151 00100 10111 COUNTB Fetch sync on write 152 00100 11000 CMPE Write Fetch sync Read Sync relative to load store operations 153 00100 11001 CMPF Write Fetch sync Read Sync relative to load store operations 154 00100 11010 CMPG Write Fetch sync Read Sync relative to load store operations 155 00100 11011 CMPH Write Fetch syn...

Page 987: ...n Debug Mode Result Read register 0 0 X Read is performed When reading ICR it is also cleared 0 1 0 Read is performed When reading ICR it is not cleared 0 1 1 Read is performed When reading ICR it is also cleared 1 X X Read is not performed program interrupt is generated When reading ICR it is not cleared Write register 0 0 X Write is performed Write to ICR or DPDR is ignored the register is not m...

Page 988: ...kpoint Bit 0 1 2 3 4 5 6 7 8 9 É 32 Field CMPV Reset UndeÞned R W R W SPR 152 CMPE 153 CMPF Figure 37 15 Comparator EÐF Value Registers CMPEÐCMPF Table 37 17 CMPEÐCMPF Field Descriptions Bits Name Description 0Ð31 CMPV Address bits to be compared Bit 0 1 2 3 4 5 6 7 8 9 É 32 Field CMPV Reset UndeÞned R W R W SPR 154 CMPG 155 CMPH Figure 37 16 Comparator GÐH Value Registers CMPGÐCMPH Table 37 18 CM...

Page 989: ...IFM ISCT_SER Reset 0000_0000_0000_0000 R W R W SPR 158 Figure 37 18 Instruction Support Control Register ICTRL Table 37 20 ICTRL Field Descriptions Bits Name Description 0Ð2 CTA Compare type of comparator AÐD 0xx Not active reset value 100 Equal 101 Less than 110 Greater than 111 Not equal 3Ð5 CTB 6Ð8 CTC 9Ð11 CTD 12Ð13 IW0 Instruction Þrst watchpoint programming 0x Not active reset value 10 Match...

Page 990: ... show cycle is performed for all changes in program ßow 010 Core is fully serialized show cycle is performed for all indirect changes in program ßow 011 Core is fully serialized no show cycles is performed for fetched instructions 100 Illegal 101 Core is not serialized normal mode show cycle is performed for all changes in the program ßow If the fetch of the target of a direct branch is aborted by...

Page 991: ...onÕt care reset value 10 Match on read 11 Match on write 14Ð1 5 CRWF 16Ð1 7 CSG Compare size comparator G and H 00 Reserved 01 Word 10 Half word 11 Byte 18Ð1 9 CSH 20 SUSG Signed unsigned operating mode for comparator G and H 0 Unsigned 1 Signed 21 SUSH 22Ð2 5 CGBMS K Byte mask for comparator G and H 0000 All bytes are not masked 0001 Last byte of the word is masked É 1111 All bytes are masked 26Ð...

Page 992: ... store watchpoint care donÕt care load store address events 0 DonÕt care 1 Care 7Ð8 LW0LD First load store watchpoint load store data events selection 00 Match from comparator G 01 Match from comparator H 10 Match from comparators G H 11 Match from comparators G H 9 LW0LDDC First load store watchpoint care donÕt care load store data events 0 DonÕt care 1 Care 10 LW1EN Second load store watchpoint ...

Page 993: ... H 11 Match from comparator G H 19 LW1LDDC Second load store watchpoint care donÕt care load store data events 0 DonÕt care 1 Care 20 BRKNOMS K Internal breakpoints nonmask bit controls both instruction and load store breakpoints 0 Masked mode breakpoints are recognized only when MSR RI 1 reset value 1 Nonmasked mode breakpoints are always recognized 21Ð2 7 Ñ Reserved 28 DLW0EN Development port tr...

Page 994: ... 25 26 27 28 29 30 31 Field Ñ CNTC Reset 0000_0000_0000_0000 R W R W SPR 150 COUNTA 151 COUNTB Figure 37 21 Breakpoint Counter Value and Control Registers COUNTA COUNTB Table 37 23 COUNTA COUNTB Field Descriptions Bits Name Description 0Ð15 CNTV Counter preset value 16Ð29 Ñ Reserved 30Ð31 CNTC Counter source select 00 Not active reset value 01 Instruction Þrst COUNTA second COUNTB watchpoint 10 Lo...

Page 995: ...auses debug mode entry if debug mode is enabled and the corresponding enable bit is set 10 DECI Decrementer interrupt bit Set when the decrementer interrupt is asserted Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set 11Ð1 2 Ñ Reserved 13 SYSI System call interrupt bit Set when the system call interrupt is asserted Causes debug mode entry if debug mode is en...

Page 996: ...corresponding enable bit is set 31 DPI Development port interrupt bit Set by the development port as a result of a debug station nonmaskable request or when entering debug mode immediately out of reset Causes debug mode entry if debug mode is enabled and the corresponding enable bit is set Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field Ñ RSTE CHSTPE MCIE Ñ EXTIE ALIE PRIE FPUVIE DECIE Ñ SYSIE TRE...

Page 997: ...2 Ñ Reserved 13 SYSIE System call interrupt enable bit 14 TRE Trace interrupt enable bit 0 Debug mode entry is disabled 1 Debug mode entry is enabled reset value 15Ð16 Ñ Reserved 17 SEIE Software emulation interrupt enable bit 0 Debug mode entry is disabled reset value 1 Debug mode entry is enabled 18 ITLBMS E Implementation speciÞc ITLB miss enable bit 19 DTLBMS E Implementation speciÞc DTLB miss...

Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...

Page 999: ...ctrical continuity Bypass the MPC860 for a given circuit board test by effectively reducing the boundary scan register to a single cell Sample the MPC860 system signals during operation and transparently shift out the result in the boundary scan register Disable the output drive to signals during circuit board testing 38 1 Overview The MPC860 TAP implementation includes a TAP controller a 4 bit in...

Page 1000: ...ence of logical values on the TMS signal It is a synchronous state machine that controls the operation of the JTAG logic The value shown adjacent to each bubble represents the value of the TMS signal sampled on the rising edge of TCK Figure 38 2 shows the MPC860 TAP controller state machine BOUNDARY SCAN REGISTER BYPASS M U X INSTRUCTION APPLY DECODE REGISTER 4ÑBIT INSTRUCTION REGISTER M U X TDO T...

Page 1001: ...860 This 475 bit boundary scan register can be connected between TDI and TDO when EXTEST or SAMPLE PRELOAD instructions are selected The boundary scan register is used for capturing data on the input signals forcing Þxed values on the output signals and selecting the direction and drive characteristics a logic value or high impedance of the bidirectional and three state signals TEST LOGIC RESET RU...

Page 1002: ...Figure 38 4 shows the logic conÞguration for an observe only input signal boundary scan cell Figure 38 4 Observe Only Input Signal Boundary Scan Cell Input Cell 1 1 MUX G1 1 1 MUX G1 C D C D FROM LAST CELL CLOCK DR UPDATE DR SHIFT DR 1 Ñ EXTEST CLAMP DATA FROM TO OUTPUT BUFFER 0 Ñ OTHERWISE LOGIC SYSTEM TO NEXT CELL 1 1 MUX G1 C D FROM LAST CELL CLOCK DR DATA TO SYSTEM LOGIC INPUT PIN SHIFT DR TO ...

Page 1003: ...onal signals include two scan cells for data input and output buffers and an I O control block It is important to know the boundary scan bit order and the signals that are associated with them The bit order of the boundary scan chain described in the MPC860 BSDL Þle starts with the TDO output and ends with the TDI input The shift register cell nearest TDO Þrst to be shifted in is deÞned as bit 1 a...

Page 1004: ... beginning internal state while performing external boundary scan operations Through the TAP the user is capable of scanning user deÞned values into the output buffers capturing values presented to input pins and controlling the output drive of three stateable output or bidirectional pins For more details on the function and use of EXTEST refer to the IEEE 1149 1 standard 38 4 2 SAMPLE PRELOAD The...

Page 1005: ... is set to a logic zero on the rising edge of TCK in the capture DR controller state Therefore the Þrst bit to be shifted out after selecting the bypass register is always a logic zero 38 4 4 CLAMP The CLAMP instruction selects the single bit bypass register as shown in Figure 38 7 above and the state of all signals driven from the system output pins is deÞned by the data currently contained in th...

Page 1006: ...to PORESET If power down mode the lowest power mode where VDDH is disabled is used connect TRST to PORESET through a diode anode to TRST cathode to PORESET The TMS TDI and TRST signals include on chip pull up resistors TCK however does not have an on chip pull up or pull down resistor it should be pulled down through a resistor To use the TAP to perform test operations select the TAP functions in ...

Page 1007: ...ar comes Þrst in memory For PowerPC little endian byte ordering also referred to as Ômunged little endianÕ the address of data is modiÞed so that the memory structure appears little endian to the executing processor when in fact the byte ordering is big endian The address modiÞcation is called ÔmungingÕ Note that the term ÔmungingÕ is not deÞned or used in the PowerPC architecture speciÞcation How...

Page 1008: ...ode to be used when an exception handler is invoked That is when an exception occurs the ILE bit as set for the interrupted process is copied into MSR LE to select the endian mode for the context established by the exception For both bits a value of 0 speciÞes BE mode or TLE mode depending on DC_CST LES and a value of 1 speciÞes PPC LE mode A 4 TLE Mode When the MPC860 operates in TLE mode the ext...

Page 1009: ...low order address bits of the effective address are exclusive ORed XOR with a two bit value that depends on the length of the operand 1 2 or 4 bytes as shown in Table A 2 This process is called 2 bit munging Õ Since all instructions are 4 byte words no address modiÞcations by the instruction cache are necessary Table A 2 TLE 2 bit Munging Data Width Bytes Address ModiÞcation 4 No change 2 XOR with...

Page 1010: ...te Swapping The unmunging and byte swapping places all external accesses by the PowerPC core into true little endian byte order Note that the bit ordering remains unchangedÑthat is bit 0 is always the msb and bit 31 is always the lsb The communication peripherals SCCs SMCs SPI I2C PIP or IDMA transfer data as bytes bytes are received one at a time and transmitted one at a time Byte transfers have ...

Page 1011: ... 32 32 31 31 32 Byte 0 3 0 ÔaÕ ÔaÕ ÔaÕ ÔaÕ Byte 1 2 1 ÔbÕ ÔbÕ ÔbÕ ÔbÕ Byte 2 1 2 ÔcÕ ÔcÕ ÔcÕ ÔcÕ Byte 3 0 3 ÔdÕ ÔdÕ ÔdÕ ÔdÕ Table A 4 Little Endian Program Data Path Between the Register and 16 Bit Memory Fetch Load Store Type Little Endian Addr U bus and Cache Addr External Bus Addr Data in the Register U bus and Cache format External Bus Format Little Endian Program Data M S B L S B 0 1 2 3 0 1 ...

Page 1012: ...een the Register and 8 Bit Memory Fetch Load Store Type Little Endian Addr U bus and Cache Addr External Bus Addr Data in the Register U bus and Cache Format External Bus Format Little Endian Program Data M S B L S B 0 1 2 3 0 1 2 3 3 2 1 0 Word 0 0 0 11 12 13 14 11 12 13 14 14 14 1 13 13 2 12 12 3 11 11 Half word 0 2 0 21 22 21 22 22 22 1 21 21 Half word 2 0 2 31 32 31 32 32 32 3 31 31 Byte 0 3 0...

Page 1013: ...physical address is passed to the cache or to external memory and the speciÞed width of data is transferred in big endian orderÑthat is MSB at the lowest address LSB at the highest address In PPC LE mode only the address is modiÞed not the byte order Munging makes it appear to the core that individual aligned scalars are stored in little endian order when in fact they are stored in big endian orde...

Page 1014: ...owest order address bits must be XORed with 0b111 This does not mean that I O operations in PPC LE systems must be performed using only one byte wide transfers Data transfers can be as wide as desired but the order of the bytes within double words must be as if they were fetched or stored one at a time That is for a true little endian I O device the system must provide a mechanism to munge and unm...

Page 1015: ... To switch the system to TLE mode DC_CST LES should be set using an mtspr instruction that resides on an even word boundary A 29 0 Further instructions should reside in the little endian format of the external system memory or in the big endian format of the internal memory if it exists The buffer descriptors for the peripherals contain the FCR BO parameters for the SDMA controller The BO paramete...

Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...

Page 1017: ...he appropriate chapter of the manual SYNCCLK is a programmable clock rate which is derived from the system frequency see Chapter 15 ÒClocks and Power Control Ó At its maximum rate it is equal to the system frequency The maximum serial clock rate is a limitation on the peak data rate This is the maximum rate at which the receiver or transmitter hardware can transfer data between its internal FIFO a...

Page 1018: ...a major consideration bus latency can be Extreme periods of bus latency could potentially cause a FIFO to overrun or underrun Where this is a more critical issue some speciÞc recommendations are made For example recommendations for system bus latency are made for an MPC860MH operating in QMC mode see the QMC Supplement to MC68360 and MPC860 User s Manuals B 3 CPM Bandwidth Average Rate Limitation ...

Page 1019: ...mode even if all QMC time slots are concatenated into one logical channel Maximum data rates are given for most channels as full duplex Channels operating in half duplex will require only half the CPM service and thus the maximum data rates supported for these channels doubles Managing DMA for the serial channels is a signiÞcant portion of the CPM processing Therefore because channels with larger ...

Page 1020: ...in Asynchronous HDLC IrDA mode 3 Mbps FD SMC in Transparent mode 1 5 Mbps FD SMC in UART mode 220 Kbps FD I2C 520 Kbps see note 1 SPI 16 bit mode 3 125 Mbps SPI 8 bit mode 500 Kbps PIP 8 bit width 625 Kbyte s PIP 16 bit width 1250 Kbyte s SCC in ProÞbus mode optional RAM microcode 2 4 Kbps FD SCC in SS 7 mode optional RAM microcode 6 Mbps FD SCC in SS 7 mode optional RAM microcode without scrambli...

Page 1021: ...er Assuming approximately linear performance versus frequency the general problem reduces to taking simple ratios For example since a 25 MHz MPC860 running Ethernet theoretically at 22 Mbps consumes approximately 100 of the CPM bandwidth what bandwidth does a practical 10 Mbps channel require The above equation shows the 10 Mbps channel requiring 45 of the CPM bandwidth of a 25 MHz MPC860 Table B ...

Page 1022: ...SCC2 QMC channels 0 11 SCC3 QMC channels 12 23 A 33 MHz MPC860MH with one half duplex Ethernet and 32 QMC channels i e 32 x 64 kbps QMC if and only if SCC1 is Ethernet QMC channels are spread over two SCCs e g SCC1 Ethernet SCC2 QMC channels 0 15 SCC3 QMC channels 16 31 A 40 MHz MPC860EN with four half duplex Ethernet channels More examples of CPM bandwidth calculations follow Example 1 MPC860 at ...

Page 1023: ...on applies Example 4 MPC860 at 25 MHz with a block of data transferred by IDMA at 512 Kbytes s to a 32 bit peripheral one asynchronous HDLC at 1Mbps one UART at 9 600 baud and one transparent channel at 2 Mbps NOTE In the case of IDMA this process calculates the peak CPM utilization not the sustained rate By nature IDMA transfers occur at random intervals and are not consistent bit rates when comp...

Page 1024: ...B 8 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...

Page 1025: ...code for mftb 371 rather than 339 2 Any write mtspr to this address causes an implementation dependent software emulation exception Table C 1 User Level PowerPC Registers Description Name Comments Access Level Serialize Access General purpose registers GPRs The thirty two 32 bit GPRs are used for source and destination operands User Ñ Condition register CR See Section 5 1 1 1 1 ÒCondition Register...

Page 1026: ...ss Decimal SPR 5Ð9 SPR 0Ð4 18 00000 10010 DSISR See the Programming Environments Manual and Section 5 1 2 1 ÒDAR DSISR and BAR Operation Ó Write Full sync Read Sync relative to load store operations 19 00000 10011 DAR See the Programming Environments Manual and Section 5 1 2 1 ÒDAR DSISR and BAR Operation Ó Write Full sync Read Sync relative to load store operations 22 00000 10110 DEC See Section ...

Page 1027: ...tore 569 10001 11001 DC_ADR Section 8 3 2 ÒData Cache Control RegistersÓ Write as a store 570 10001 11010 DC_DAT Section 8 3 2 ÒData Cache Control RegistersÓ Write as a store 784 11000 10000 MI_CTR Section 9 8 1 ÒIMMU Control Register MI_CTR Ó Write as a store 786 11000 10010 MI_AP Section 9 8 10 ÒMMU Access Protection Registers MI_AP MD_AP Ó Write as a store 787 11000 10011 MI_EPN Section 9 8 3 Ò...

Page 1028: ...8 7 ÒDMMU Real Page Number Register MD_RPN Ó Write as a store 799 11000 11111 M_TW M_SAVE Section 9 8 11 ÒMMU Tablewalk Special Register M_TW Ó Write as a store 824 11001 11000 MD_CAM Section 9 8 12 4 ÒDMMU CAM Entry Read Register MD_CAM Ó Write as a store 825 11001 11001 MD_RAM0 Section 9 8 12 5 ÒDMMU RAM Entry Read Register 0 MD_RAM0 Ó Write as a store 826 11001 11010 MD_RAM1 Section 9 8 13 ÒDMM...

Page 1029: ...etch sync Read Sync relative to load store operations 156 00100 11100 LCTRL1 Write Fetch sync Read Sync relative to load store operations 157 00100 11101 LCTRL2 Write Fetch sync Read Sync relative to load store operations 158 00100 11110 ICTRL Fetch sync on write 159 00100 11111 BAR Write Fetch sync Read Sync relative to load store operations See Section 5 1 2 1 ÒDAR DSISR and BAR Operation Ó 630 ...

Page 1030: ...C 6 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...

Page 1031: ...ncatenation of sequences from left to right are shown in lowercase For more information refer to Chapter 8 ÒInstruction Set Ó in The Programming Environments Manual D 1 Instructions Sorted by Mnemonic Table D 1 lists the instructions implemented in the MPC860 in alphabetical order by mnemonic Table D 1 Complete Instruction List Sorted by Mnemonic Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ...

Page 1032: ...qv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 dcbf 31 0 0 0 0 0 A B 86 0 dcbi 1 31 0 0 0 0 0 A B 470 0 dcbst 31 0 0 0 0 0 A B 54 0 dcbt 31 0 0 0 0 0 A B 278 0 dcbtst 31 0 0 0 0 0 A B 246 0 dcbz 31 0 0 0 0 0 A B 1014 0 divdx 4 31 D A B OE 489 Rc divdux 4 31 D A B OE 457 ...

Page 1033: ... 63 D 0 0 0 0 0 B 15 Rc fdivx6 63 D A B 0 0 0 0 0 18 Rc fdivsx6 59 D A B 0 0 0 0 0 18 Rc fmaddx6 63 D A B C 29 Rc fmaddsx6 59 D A B C 29 Rc fmrx6 63 D 0 0 0 0 0 B 72 Rc fmsubx6 63 D A B C 28 Rc fmsubsx6 59 D A B C 28 Rc fmulx6 63 D A 0 0 0 0 0 C 25 Rc fmulsx6 59 D A 0 0 0 0 0 C 25 Rc fnabsx6 63 D 0 0 0 0 0 B 136 Rc fnegx6 63 D 0 0 0 0 0 B 40 Rc fnmaddx 6 63 D A B C 31 Rc fnmaddsx6 59 D A B C 31 Rc...

Page 1034: ...A B 119 0 lbzx 31 D A B 87 0 ld 4 58 D A ds 0 ldarx 4 31 D A B 84 0 ldu 4 58 D A ds 1 ldux 4 31 D A B 53 0 ldx 4 31 D A B 21 0 lfd6 50 D A d lfdu6 51 D A d lfdux6 31 D A B 631 0 lfdx6 31 D A B 599 0 lfs6 48 D A d lfsu6 49 D A d lfsux6 31 D A B 567 0 lfsx6 31 D A B 535 0 lha 42 D A d lhau 43 D A d lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhbrx 31 D A B 790 0 lhz 40 D A d lhzu 41 D A d lhzux 31 D A ...

Page 1035: ...fsx6 63 D 0 0 0 0 0 0 0 0 0 0 583 Rc mfmsr 1 31 D 0 0 0 0 0 0 0 0 0 0 83 0 mfspr 2 31 D spr 339 0 mfsr 1 31 D 0 SR 0 0 0 0 0 595 0 mfsrin 1 31 D 0 0 0 0 0 B 659 0 mftb 31 D tbr 371 0 mtcrf 31 S 0 CRM 0 144 0 mtfsb0x6 63 crbD 0 0 0 0 0 0 0 0 0 0 70 Rc mtfsb1x 6 63 crbD 0 0 0 0 0 0 0 0 0 0 38 Rc mtfsfx6 63 0 FM 0 B 711 Rc mtfsfix6 63 crfD 0 0 0 0 0 0 0 IMM 0 134 Rc mtmsr 1 31 S 0 0 0 0 0 0 0 0 0 0 1...

Page 1036: ...h mb 2 sh Rc rldiclx 4 30 S A sh mb 0 sh Rc rldicrx 4 30 S A sh me 1 sh Rc rldimix 4 30 S A sh mb 3 sh Rc rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc sc 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 slbia 1 4 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 498 0 slbie 1 4 5 31 0 0 0 0 0 0 0 0 0 0 B 434 0 sldx 4 31 S A B 27 Rc slwx 31 S A B 24 Rc sradx 4 31 S A B 794 ...

Page 1037: ...727 0 stfiwx 5 31 S A B 983 0 stfs 52 S A d stfsu 53 S A d stfsux 31 S A B 695 0 stfsx 31 S A B 663 0 sth 44 S A d sthbrx 31 S A B 918 0 sthu 45 S A d sthux 31 S A B 439 0 sthx 31 S A B 407 0 stmw 3 47 S A d stswi 3 31 S A NB 725 0 stswx 3 31 S A B 661 0 stw 36 S A d stwbrx 31 S A B 662 0 stwcx 31 S A B 150 1 stwu 37 S A d stwux 31 S A B 183 0 stwx 31 S A B 151 0 subfx 31 D A B OE 40 Rc subfcx 31 ...

Page 1038: ... tlbie 1 5 31 0 0 0 0 0 0 0 0 0 0 B 306 0 tlbsync1 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 566 0 tw 31 TO A B 4 0 twi 03 TO A SIMM xorx 31 S A B 316 Rc xori 26 S A UIMM xoris 27 S A UIMM 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not s...

Page 1039: ... 0 0 0 1 0 bx 0 1 0 0 1 0 LI AA LK mcrf 0 1 0 0 1 1 crfD 0 0 crfS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bclrx 0 1 0 0 1 1 BO BI 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 LK crnor 0 1 0 0 1 1 crbD crbA crbB 0 0 0 0 1 0 0 0 0 1 0 rfi 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 crandc 0 1 0 0 1 1 crbD crbA crbB 0 0 1 0 0 0 0 0 0 1 0 isync 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 ...

Page 1040: ...0 0 0 Rc mulhdux 4 0 1 1 1 1 1 D A B 0 0 0 0 0 0 1 0 0 1 Rc addcx 0 1 1 1 1 1 D A B OE 0 0 0 0 0 1 0 1 0 Rc mulhwux 0 1 1 1 1 1 D A B 0 0 0 0 0 0 1 0 1 1 Rc mfcr 0 1 1 1 1 1 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 lwarx 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 0 0 ldx 4 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 0 1 0 lwzx 0 1 1 1 1 1 D A B 0 0 0 0 0 1 0 1 1 1 0 slwx 0 1 1 1 1 1 S A B 0 0 0 0 0 1 1 0 0 0 Rc...

Page 1041: ...0 0 0 mtmsr 0 1 1 1 1 1 S 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 stdx 4 0 1 1 1 1 1 S A B 0 0 1 0 0 1 0 1 0 1 0 stwcx 0 1 1 1 1 1 S A B 0 0 1 0 0 1 0 1 1 0 1 stwx 0 1 1 1 1 1 S A B 0 0 1 0 0 1 0 1 1 1 0 stdux 4 0 1 1 1 1 1 S A B 0 0 1 0 1 1 0 1 0 1 0 stwux 0 1 1 1 1 1 S A B 0 0 1 0 1 1 0 1 1 1 0 subfzex 0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 1 1 0 0 1 0 0 0 Rc addzex 0 1 1 1 1 1 D A 0 0 0 0 0 OE 0 1 1 ...

Page 1042: ...0 1 1 1 1 1 S A B 0 1 1 0 0 1 0 1 1 1 0 orcx 0 1 1 1 1 1 S A B 0 1 1 0 0 1 1 1 0 0 Rc sradix 4 0 1 1 1 1 1 S A sh 1 1 0 0 1 1 1 0 1 1 sh Rc slbie 1 4 5 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 B 0 1 1 0 1 1 0 0 1 0 0 ecowx 0 1 1 1 1 1 S A B 0 1 1 0 1 1 0 1 1 0 0 sthux 0 1 1 1 1 1 S A B 0 1 1 0 1 1 0 1 1 1 0 orx 0 1 1 1 1 1 S A B 0 1 1 0 1 1 1 1 0 0 Rc divdux 4 0 1 1 1 1 1 D A B OE 1 1 1 0 0 1 0 0 1 Rc divw...

Page 1043: ...1 0 1 1 1 0 stfsux 0 1 1 1 1 1 S A B 1 0 1 0 1 1 0 1 1 1 0 stswi 3 0 1 1 1 1 1 S A NB 1 0 1 1 0 1 0 1 0 1 0 stfdx6 0 1 1 1 1 1 S A B 1 0 1 1 0 1 0 1 1 1 0 stfdux6 0 1 1 1 1 1 S A B 1 0 1 1 1 1 0 1 1 1 0 lhbrx 0 1 1 1 1 1 D A B 1 1 0 0 0 1 0 1 1 0 0 srawx 0 1 1 1 1 1 S A B 1 1 0 0 0 1 1 0 0 0 Rc sradx 4 0 1 1 1 1 1 S A B 1 1 0 0 0 1 1 0 1 0 Rc srawix 0 1 1 1 1 1 S A SH 1 1 0 0 1 1 1 0 0 0 Rc eieio ...

Page 1044: ... 1 1 0 1 0 1 S A d stfd6 1 1 0 1 1 0 S A d stfdu6 1 1 0 1 1 1 S A d ld 4 1 1 1 0 1 0 D A ds 0 0 ldu 4 1 1 1 0 1 0 D A ds 0 1 lwa 4 1 1 1 0 1 0 D A ds 1 0 fdivsx6 1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 0 1 0 Rc fsubsx6 1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 1 0 0 Rc faddsx6 1 1 1 0 1 1 D A B 0 0 0 0 0 1 0 1 0 1 Rc fsqrtsx 5 6 1 1 1 0 1 1 D 0 0 0 0 0 B 0 0 0 0 0 1 0 1 1 0 Rc fresx 5 6 1 1 1 0 1 1 D 0 0 0 0 0 B 0 ...

Page 1045: ...1 1 1 D A B C 1 1 1 0 0 Rc fmaddx6 1 1 1 1 1 1 D A B C 1 1 1 0 1 Rc fnmsubx6 1 1 1 1 1 1 D A B C 1 1 1 1 0 Rc fnmaddx 6 1 1 1 1 1 1 D A B C 1 1 1 1 1 Rc fcmpo 6 1 1 1 1 1 1 crfD 0 0 A B 0 0 0 0 1 0 0 0 0 0 0 mtfsb1x 6 1 1 1 1 1 1 crbD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 Rc fnegx6 1 1 1 1 1 1 D 0 0 0 0 0 B 0 0 0 0 1 0 1 0 0 0 Rc mcrfs6 1 1 1 1 1 1 crfD 0 0 crfS 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0...

Page 1046: ... 0 B 1 1 0 1 0 0 1 1 1 0 Rc 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC860 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ...

Page 1047: ... A SIMM addic 13 D A SIMM addis 15 D A SIMM addmex 31 D A 0 0 0 0 0 OE 234 Rc addzex 31 D A 0 0 0 0 0 OE 202 Rc divdx 4 31 D A B OE 489 Rc divdux 4 31 D A B OE 457 Rc divwx 31 D A B OE 491 Rc divwux 31 D A B OE 459 Rc mulhdx 4 31 D A B 0 73 Rc mulhdux4 31 D A B 0 9 Rc mulhwx 31 D A B 0 75 Rc mulhwux 31 D A B 0 11 Rc mulld 4 31 D A B OE 233 Rc mulli 07 D A SIMM mullwx 31 D A B OE 235 Rc negx 31 D A...

Page 1048: ... UIMM andis 29 S A UIMM cntlzdx 4 31 S A 0 0 0 0 0 58 Rc cntlzwx 31 S A 0 0 0 0 0 26 Rc eqvx 31 S A B 284 Rc extsbx 31 S A 0 0 0 0 0 954 Rc extshx 31 S A 0 0 0 0 0 922 Rc extswx 4 31 S A 0 0 0 0 0 986 Rc nandx 31 S A B 476 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc ori 24 S A UIMM oris 25 S A UIMM xorx 31 S A B 316 Rc xori 26 S A UIMM xoris 27 S A UIMM Table D 6 Integer Rotat...

Page 1049: ... S A B 536 Rc Table D 8 Floating Point Arithmetic Instructions6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddx 63 D A B 0 0 0 0 0 21 Rc faddsx 59 D A B 0 0 0 0 0 21 Rc fdivx 63 D A B 0 0 0 0 0 18 Rc fdivsx 59 D A B 0 0 0 0 0 18 Rc fmulx 63 D A 0 0 0 0 0 C 25 Rc fmulsx 59 D A 0 0 0 0 0 C 25 Rc fresx 5 59 D 0 0 0 0 0 B 0 0 0 0 0 24 Rc frsqrtex 5 63 D 0 0 0 0...

Page 1050: ... 63 D 0 0 0 0 0 B 846 Rc fctidx 4 63 D 0 0 0 0 0 B 814 Rc fctidzx 4 63 D 0 0 0 0 0 B 815 Rc fctiwx 63 D 0 0 0 0 0 B 14 Rc fctiwzx 63 D 0 0 0 0 0 B 15 Rc frspx 63 D 0 0 0 0 0 B 12 Rc Table D 11 Floating Point Compare Instructions6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fcmpo 63 crfD 0 0 A B 32 0 fcmpu 63 crfD 0 0 A B 0 0 Table D 12 Floating Point Status a...

Page 1051: ...A d lbzu 35 D A d lbzux 31 D A B 119 0 lbzx 31 D A B 87 0 ld 4 58 D A ds 0 ldu 4 58 D A ds 1 ldux 4 31 D A B 53 0 ldx 4 31 D A B 21 0 lha 42 D A d lhau 43 D A d lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhz 40 D A d lhzu 41 D A d lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lwa 4 58 D A ds 2 lwaux 4 31 D A B 373 0 lwax 4 31 D A B 341 0 lwz 32 D A d lwzu 33 D A d lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 ...

Page 1052: ...4 S A d sthu 45 S A d sthux 31 S A B 439 0 sthx 31 S A B 407 0 stw 36 S A d stwu 37 S A d stwux 31 S A B 183 0 stwx 31 S A B 151 0 Table D 15 Integer Load and Store with Byte Reverse Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lhbrx 31 D A B 790 0 lwbrx 31 D A B 534 0 sthbrx 31 S A B 918 0 stwbrx 31 S A B 662 0 Table D 16 Integer Load and Store M...

Page 1053: ... 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eieio 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 854 0 isync 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 150 0 ldarx 4 31 D A B 84 0 lwarx 31 D A B 20 0 stdcx 4 31 S A B 214 1 stwcx 31 S A B 150 1 sync 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 598 0 Table D 19 Floating Point Load Instructions6 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ...

Page 1054: ...0 0 0 0 0 B 72 Rc fnabsx 63 D 0 0 0 0 0 B 136 Rc fnegx 63 D 0 0 0 0 0 B 40 Rc Table D 22 Branch Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bx 18 LI AA LK bcx 16 BO BI BD AA LK bcctrx 19 BO BI 0 0 0 0 0 528 LK bclrx 19 BO BI 0 0 0 0 0 16 LK Table D 23 Condition Register Logical Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ...

Page 1055: ...ame 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 td 4 31 TO A B 68 0 tdi 4 03 TO A SIMM tw 31 TO A B 4 0 twi 03 TO A SIMM Table D 26 Processor Control Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mcrxr 31 crfS 0 0 0 0 0 0 0 0 0 0 0 0 512 0 mfcr 31 D 0 0 0 0 0 0 0 0 0 0 19 0 mfmsr 1 31 D 0 0 0 0 0 0 0 0 0 0 83 0 mfs...

Page 1056: ...10 0 mtsrin 1 31 S 0 0 0 0 0 B 242 0 Table D 29 Lookaside Buffer Management Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 slbia 1 4 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 498 0 slbie 1 4 5 31 0 0 0 0 0 0 0 0 0 0 B 434 0 tlbia 1 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 370 0 tlbie 1 5 31 0 0 0 0 0 0 0 0 0 0 B 306 0 tlbsync1 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 1057: ...5 26 27 28 29 30 31 bx 18 LI AA LK OPCD BO BI BD AA LK SpeciÞc Instruction Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcx 16 BO BI BD AA LK OPCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 SpeciÞc Instruction Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sc 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ...

Page 1058: ... andi 28 S A UIMM andis 29 S A UIMM cmpi 11 crfD 0 L A SIMM cmpli 10 crfD 0 L A UIMM lbz 34 D A d lbzu 35 D A d lfd6 50 D A d lfdu 6 51 D A d lfs6 48 D A d lfsu6 49 D A d lha 42 D A d lhau 43 D A d lhz 40 D A d lhzu 41 D A d lmw 3 46 D A d lwz 32 D A d lwzu 33 D A d mulli 7 D A SIMM ori 24 S A UIMM oris 25 S A UIMM stb 38 S A d stbu 39 S A d stfd6 54 S A d stfdu6 55 S A d stfs6 52 S A d stfsu6 53 ...

Page 1059: ... 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ld 4 58 D A ds 0 ldu 4 58 D A ds 1 lwa 4 58 D A ds 2 std 4 62 S A ds 0 stdu 4 62 S A ds 1 OPCD D A B XO 0 OPCD D A NB XO 0 OPCD D 0 0 0 0 0 B XO 0 OPCD D 0 0 0 0 0 0 0 0 0 0 XO 0 OPCD D 0 SR 0 0 0 0 0 XO 0 OPCD S A B XO Rc OPCD S A B XO 1 OPCD S A B XO 0 OPCD S A NB XO 0 OPCD S A 0 0 0 0 0 XO Rc OPCD S 0 0 0 0 0 B XO 0 OP...

Page 1060: ...ndx 31 S A B 28 Rc andcx 31 S A B 60 Rc cmp 31 crfD 0 L A B 0 0 cmpl 31 crfD 0 L A B 32 0 cntlzdx 4 31 S A 0 0 0 0 0 58 Rc cntlzwx 31 S A 0 0 0 0 0 26 Rc dcbf 31 0 0 0 0 0 A B 86 0 dcbi 1 31 0 0 0 0 0 A B 470 0 dcbst 31 0 0 0 0 0 A B 54 0 dcbt 31 0 0 0 0 0 A B 278 0 dcbtst 31 0 0 0 0 0 A B 246 0 dcbz 31 0 0 0 0 0 A B 1014 0 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1061: ...bzux 31 D A B 119 0 lbzx 31 D A B 87 0 ldarx 4 31 D A B 84 0 ldux 4 31 D A B 53 0 ldx 4 31 D A B 21 0 lfdux6 31 D A B 631 0 lfdx6 31 D A B 599 0 lfsux6 31 D A B 567 0 lfsx6 31 D A B 535 0 lhaux 31 D A B 375 0 lhax 31 D A B 343 0 lhbrx 31 D A B 790 0 lhzux 31 D A B 311 0 lhzx 31 D A B 279 0 lswi 3 31 D A NB 597 0 lswx 3 31 D A B 533 0 lwarx 31 D A B 20 0 lwaux 4 31 D A B 373 0 lwax 4 31 D A B 341 0...

Page 1062: ...0 0 0 0 0 B 242 0 nandx 31 S A B 476 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc slbia 1 4 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 498 0 slbie 1 4 5 31 0 0 0 0 0 0 0 0 0 0 B 434 0 sldx 4 31 S A B 27 Rc slwx 31 S A B 24 Rc sradx 4 31 S A B 794 Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srdx 4 31 S A B 539 Rc srwx 31 S A B 536 Rc stbux 31 S A B 247 0 stbx 31 S A B 215 0 stdcx 4...

Page 1063: ... 0 0 0 0 0 0 0 0 B 1010 0 tlbsync1 5 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 566 0 tw 31 TO A B 4 0 xorx 31 S A B 316 Rc OPCD BO BI 0 0 0 0 0 XO LK OPCD crbD crbA crbB XO 0 OPCD crfD 0 0 crfS 0 0 0 0 0 0 0 XO 0 OPCD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XO 0 SpeciÞc Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bcctrx 19 BO BI 0 0 0 0 0 528 LK bclrx 19 BO BI 0 0 ...

Page 1064: ...28 29 30 31 mfspr 2 31 D spr 339 0 mftb 31 D tbr 371 0 mtcrf 31 S 0 CRM 0 144 0 mtspr 2 31 D spr 467 0 OPCD 0 FM 0 B XO Rc SpeciÞc Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mtfsfx6 63 0 FM 0 B 711 Rc OPCD S A sh XO sh Rc SpeciÞc Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sradix 4 31 S A sh 41...

Page 1065: ... OE 235 Rc negx 31 D A 0 0 0 0 0 OE 104 Rc subfx 31 D A B OE 40 Rc subfcx 31 D A B OE 8 Rc subfex 31 D A B OE 136 Rc subfmex 31 D A 0 0 0 0 0 OE 232 Rc subfzex 31 D A 0 0 0 0 0 OE 200 Rc OPCD D A B 0 0 0 0 0 XO Rc OPCD D A B C XO Rc OPCD D A 0 0 0 0 0 C XO Rc OPCD D 0 0 0 0 0 B 0 0 0 0 0 XO Rc SpeciÞc Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 f...

Page 1066: ...0 0 22 Rc fsqrtsx 5 6 59 D 0 0 0 0 0 B 0 0 0 0 0 22 Rc fsubx6 63 D A B 0 0 0 0 0 20 Rc fsubsx6 59 D A B 0 0 0 0 0 20 Rc OPCD S A SH MB ME Rc OPCD S A B MB ME Rc SpeciÞc Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc OPCD S A sh mb XO sh Rc OPCD S A sh me XO sh Rc SpeciÞc ...

Page 1067: ... 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rldclx 4 30 S A B mb 8 Rc rldcrx 4 30 S A B me 9 Rc 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC860 ...

Page 1068: ...able D 46 Instruction Set Legend UISA VEA OEA Supervisor Level 64 Bit Optional Form addx Ö XO addcx Ö XO addex Ö XO addi Ö D addic Ö D addic Ö D addis Ö D addmex Ö XO addzex Ö XO andx Ö X andcx Ö X andi Ö D andis Ö D bx Ö I bcx Ö B bcctrx Ö XL bclrx Ö XL cmp Ö X cmpi Ö D cmpl Ö X cmpli Ö D cntlzdx 4 Ö Ö X cntlzwx Ö X crand Ö XL crandc Ö XL creqv Ö XL crnand Ö XL crnor Ö XL Reserved bits Key Instru...

Page 1069: ...4 Ö Ö XO divdux 4 Ö Ö XO divwx Ö XO divwux Ö XO eciwx Ö Ö X ecowx Ö Ö X eieio Ö X eqvx Ö X extsbx Ö X extshx Ö X extswx 4 Ö Ö X fabsx6 Ö X faddx6 Ö A faddsx6 Ö A fcfidx 4 6 Ö Ö X fcmpo6 Ö X fcmpu6 Ö X fctidx 4 6 Ö Ö X fctidzx 4 6 Ö Ö X fctiwx6 Ö X fctiwzx6 Ö X fdivx6 Ö A fdivsx6 Ö A fmaddx6 Ö A fmaddsx6 Ö A fmrx6 Ö X UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1070: ... A fnmsubsx6 Ö A fresx 5 6 Ö Ö A frspx6 Ö X frsqrtex 5 6 Ö Ö A fselx 5 6 Ö Ö A fsqrtx 5 6 Ö Ö A fsqrtsx 5 6 Ö Ö A fsubx6 Ö A fsubsx6 Ö A icbi Ö X isync Ö XL lbz Ö D lbzu Ö D lbzux Ö X lbzx Ö X ld 4 Ö Ö DS ldarx 4 Ö Ö X ldu 4 Ö Ö DS ldux 4 Ö Ö X ldx 4 Ö Ö X lfd6 Ö D lfdu 6 Ö D lfdux6 Ö X lfdx6 Ö X lfs6 Ö D lfsu6 Ö D UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1071: ... Ö D lhzux Ö X lhzx Ö X lmw 3 Ö D lswi 3 Ö X lswx 3 Ö X lwa 4 Ö Ö DS lwarx Ö X lwaux 4 Ö Ö X lwax 4 Ö Ö X lwbrx Ö X lwz Ö D lwzu Ö D lwzux Ö X lwzx Ö X mcrf Ö XL mcrfs6 Ö X mcrxr Ö X mfcr Ö X mffsx6 Ö X mfmsr 1 Ö Ö X mfspr 2 Ö Ö Ö XFX mfsr 1 Ö Ö X mfsrin 1 Ö Ö X mftb Ö XFX mtcrf Ö XFX mtfsb0x6 Ö X UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1072: ...mulhwx Ö XO mulhwux Ö XO mulldx 4 Ö Ö XO mulli Ö D mullwx Ö XO nandx Ö X negx Ö XO norx Ö X orx Ö X orcx Ö X ori Ö D oris Ö D rfi 1 Ö Ö XL rldclx 4 Ö Ö MDS rldcrx 4 Ö Ö MDS rldicx 4 Ö Ö MD rldiclx 4 Ö Ö MD rldicrx 4 Ö Ö MD rldimix 4 Ö Ö MD rlwimix Ö M rlwinmx Ö M rlwnmx Ö M sc Ö Ö SC slbia 1 4 5 Ö Ö Ö Ö X slbie 1 4 5 Ö Ö Ö Ö X sldx 4 Ö Ö X UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1073: ...Ö D stbu Ö D stbux Ö X stbx Ö X std 4 Ö Ö DS stdcx 4 Ö Ö X stdu 4 Ö Ö DS stdux 4 Ö Ö X stdx 4 Ö Ö X stfd6 Ö D stfdu6 Ö D stfdux6 Ö X stfdx6 Ö X stfiwx 5 6 Ö Ö X stfs6 Ö D stfsu6 Ö D stfsux6 Ö X stfsx6 Ö X sth Ö D sthbrx Ö X sthu Ö D sthux Ö X sthx Ö X stmw 3 Ö D stswi 3 Ö X stswx 3 Ö X stw Ö D stwbrx Ö X UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1074: ...Ö Ö D tlbia 1 5 Ö Ö Ö X tlbie 1 5 Ö Ö Ö X tlbsync 1 5 Ö Ö X tw Ö X twi Ö D xorx Ö X xori Ö D xoris Ö D 1 Supervisor level instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 64 bit instruction 5 Optional in the PowerPC architecture 6 Floating point instructions are not supported by the MPC860 UISA VEA OEA Supervisor Level 64 Bit Optional Form ...

Page 1075: ...ronous exception Exceptions that are caused by events external to the processorÕs execution In this document the term Ôasynchronous exceptionÕ is used interchangeably with the word interrupt Atomic access A bus access that attempts to be part of a read write operation to the same address uninterrupted by any other access to that address the term refers to the fact that the transactions are indivis...

Page 1076: ...t bus a four beat burst can transfer four 64 bit double words Bus parking A feature that optimizes the use of the bus by allowing a device to retain bus mastership without having to rearbitrate Cache High speed memory component containing recently accessed data and or instructions subset of main memory Cache coherency An attribute in which an accurate and common view of memory is provided to all d...

Page 1077: ...a word or double word in a cache block to be transferred Þrst Denormalized number A nonzero ßoating point number whose exponent has a reserved value usually the format s minimum and whose explicit or implicit leading signiÞcand bit is zero Direct mapped cache A cache in which each main memory address can appear in only one location within the cache operates more quickly when the memory request is ...

Page 1078: ...to context synchronization but doesn t force the contents of the instruction buffers to be deleted and refetched Exponent In the binary representation of a ßoating point number the exponent is the component that normally signiÞes the integer power to which the value two is raised in determining the value of the represented number See also Biased exponent Fetch Retrieving instructions from either t...

Page 1079: ...cessorÕs design that is not required by the PowerPC architecture but for which the PowerPC architecture may provide concessions to ensure that processors that implement the feature do so consistently Imprecise exception A type of synchronous exception that is allowed not to adhere to the precise exception model see Precise exception The PowerPC architecture allows only ßoating point exceptions to ...

Page 1080: ...m memory for example on chip cache secondary cache and system memory Memory management unit MMU The functional unit that is capable of translating an effective logical address to a physical address providing protection mechanisms and deÞning caching methods Microarchitecture The hardware details of a microprocessorÕs design Such details are not deÞned by the PowerPC architecture Mnemonic The abbre...

Page 1081: ... model for example speculative operations An operation is said to be performed out of order if at the time that it is performed it is not known to be required by the sequential execution model See In order Out of order execution A technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream Overßow An error condition that occu...

Page 1082: ...on domain A protection domain is a segment a virtual page a BAT area or a range of unmapped effective addresses It is deÞned only when the appropriate relocate bit in the MSR IR or DR is 1 Quad word A group of 16 contiguous locations starting at an address divisible by 16 rA The rA instruction Þeld is used to specify a GPR to be used as a source or destination rB The rB instruction Þeld is used to...

Page 1083: ...written to the bit was 0 and returns an undeÞned value 0 or 1 otherwise RISC reduced instruction set computing An architecture characterized by Þxed length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses Scalability The capability of an architecture to generate implementations speciÞc for a wide range of purposes and ...

Page 1084: ... instructions concurrently from a conventional linear instruction stream Supervisor mode The privileged operation state of a processor In supervisor mode software typically the operating system can access all control registers and can access the supervisor memory space among other privileged operations Synchronization A process to ensure that operations occur strictly in order See Context synchron...

Page 1085: ...ity from a user level perspective Implementations that conform to the PowerPC VEA also adhere to the UISA but may not necessarily adhere to the OEA Virtual address An intermediate address used in the translation of an effective address to a physical address Virtual memory The address space created using the memory management facilities of the processor Program access to virtual memory is possible ...

Page 1086: ...Glossary 12 MPC860 PowerQUICC UserÕs Manual MOTOROLA ...

Page 1087: ...d store example 37 18 operation details 37 15 Breakpoint address BAR register 37 38 Breakpoint counter value and control COUNTA COUNTB registers 37 43 BRn base registers 16 8 BS_An byte select signals 3 7 13 9 BSYNC BISYNC SYNC register 27 7 Buffer chaining 20 12 BURST burst transfer signal 3 3 13 5 14 4 14 30 Burst bus operations 14 14 Burst transfer bus operation 14 13 Bus arbitration 14 25 Bus ...

Page 1088: ...itor 8 30 disable commands 8 9 enable commands 8 9 IC_CST commands 8 9 instruction fetching 8 23 instruction sequencer 8 2 8 20 invalidate all command 8 11 load lock cache block commands 8 10 memory coherency 8 4 operations 8 20 organization 8 2 read command 8 9 reading data 8 8 reading tags 8 9 registers 8 6 snooping 8 4 8 24 stream hits 8 22 unlock all command 8 11 unlock cache block command 8 1...

Page 1089: ...al interface overview 21 1 timers 18 4 Comparator value CMPAÐCMPH registers 37 37 Compare instructions D 18 Completion queue timing full 10 4 compliant with the Book 1 specification for the PowerPC architecture The PowerPC core is a fully static design that consist 1 6 Context synchronization 6 6 Conventions notational conventions lxix ix xiv xxx xxxvi terminology lxxiii xxi copyback buffer 8 15 C...

Page 1090: ...E mode A 2 Exceptions alignment exception 7 7 asynchronous exceptions 7 3 breakpoint detection 37 8 bus exception control cycles 14 37 debug exceptions 7 15 decrementer exception 7 10 DSI exception 7 6 DTLB error 7 14 9 32 DTLB miss 7 13 9 32 exception handling 7 1 16 43 exception latency 7 18 exception priority 7 4 external interrupt 7 6 external reset exception 20 22 floating point assist 7 12 i...

Page 1091: ...12 4 settings at power on 15 7 HRESET hard reset signal 3 8 13 11 I I2ADD I2 C address register 32 7 I2BRG I2 C baud rate generator register 32 7 I2C controller buffer descriptors 32 11 clocking 32 2 commands 32 11 master read slave write 32 4 master write slave read 32 3 overview xxviii 32 1 parameter RAM 32 9 registers 32 6 signals functions 32 2 slave read master write 32 3 slave write master r...

Page 1092: ...oad store address generation 6 11 load instructions 6 12 multiple instructions 6 14 store instructions 6 13 string instructions 6 14 lwarx 8 28 memory control D 26 memory control OEA 6 23 memory control VEA 6 21 memory synchronization D 23 memory synchronization UISA 6 17 memory synchronization VEA 6 20 mfspr 8 6 8 11 mtspr 8 6 8 11 optional instructions D 38 processor control D 25 processor contr...

Page 1093: ... register 16 16 Memory controller basic architecture 16 4 block diagram single UPM 16 3 external master support 16 51 features summary 16 1 memory system interface 16 58 overview 16 1 page mode extended data out interface 16 70 registers 16 8 memory map PIP 2 9 2 9 SCC1 2 6 SCC4 2 8 Memory map reference 2 1 Memory synchronization instructions D 23 Memory system interface 16 58 MI_CAM IMMU CAM entr...

Page 1094: ...lel interface port block diagram 33 2 buffer descriptors 33 11 BUSY signal Centronics interface 33 17 Centronics interface implementation 33 19 Centronics receive errors 33 22 Centronics receiver 33 22 Centronics transmit errors 33 21 Centronics transmitter 33 20 control character table 33 6 core control vs CP control 33 2 CP commands 33 14 features 33 1 handshaking I O modes 33 15 interlocked han...

Page 1095: ...37 5 debug mode 37 5 description 37 2 indirect branch instructions 37 5 queue flush information 37 4 reconstruction 37 5 sequential instructions 37 5 signals 37 3 special cases 37 4 window trace 37 6 Programming the SIU 11 4 Promiscuous mode see Transparent mode PSCR PCMCIA interface status changed register 17 9 PSMR protocol specific mode register 22 10 AppleTalk mode 25 4 transparent mode 29 8 P...

Page 1096: ...FCR 20 11 IDMA buffer descriptors 20 9 IMMR 11 4 instruction register 38 6 key registers 11 11 LCTRL1 37 40 LCTRL2 37 41 M_CASID 9 23 M_TW 9 24 M_TWB 9 23 MD_CAM 9 28 MD_CTR 9 17 MD_RAM 9 29 9 30 MD_RPN 9 22 MD_TWC 9 19 memory controller BRn 16 8 MAR 16 17 MCR 16 15 MDR 16 16 MPTPR 16 17 MSTAT 16 13 MxMR 16 13 ORn 16 10 memory controller register model 16 8 MI_CAM 9 25 MI_CTR 9 16 MI_RAM 9 27 MI_R...

Page 1097: ...0 3 SDMR 20 5 SDSR 20 4 serial interface BRGCn 21 40 SICMR 21 24 SICR 21 23 SIGMR 21 16 SIMODE 21 17 SIRP 21 26 SISTR 21 25 settings after alignment exception 7 8 debug exception 7 15 decrementer exception 7 10 DTLB error exception 7 14 DTLB miss exception 7 13 external interrupt 7 7 ITLB error exception 7 14 ITLB miss exception 7 13 program exception 7 9 software emulation exception 7 12 system c...

Page 1098: ...RT event register 23 19 SCCM SCC mask asynchronous HDLC 26 9 SCCM SCC mask register transparent mode 29 12 SCCM SCC mask register BISYNC 27 15 SCCM SCC mask register Ethernet 28 25 SCCM SCC mask register HDLC 24 12 SCCM SCC UART mask register 23 19 SCCR system clock and reset control register 15 27 SCCs AppleTalk mode connecting to AppleTalk 25 3 operating LocalTalk frame 25 1 overview 25 1 progra...

Page 1099: ...R SDMA configuration register 20 3 SDMA channels and U bus arbitration 20 2 SDMR SDMA mask register 20 5 SDSR SDMA status register 20 4 Segment registers manipulation instructions D 26 Serial communication controllers SCCs UART mode features 23 2 overview 23 1 Serial communications controllers SCCs features 22 2 overview 22 1 Serial communications performance bus utilization B 2 clocking B 1 IDMA ...

Page 1100: ...SI mode SIMODE register 21 17 SI RAM pointer SIRP register 21 26 SI status register SISTR 21 25 SIEL SIU interrupt edge level register 11 18 Signals ALE_x 3 8 13 11 An 3 3 13 5 14 3 14 30 AS 3 11 13 14 ATn 14 4 14 30 BADDRn 3 10 13 14 BB 3 6 13 8 14 6 14 27 BDIP 3 4 13 5 14 4 14 33 BG 3 6 13 8 14 6 14 26 BI 3 4 13 6 14 5 14 33 BR 3 6 13 8 14 6 14 26 BS_A 3 7 13 9 BURST 3 3 13 5 14 4 14 30 bus cont...

Page 1101: ...reset sequence 12 5 SRESET soft reset signal 3 8 13 11 Status mask SMASK register 33 4 Storage reservation 14 34 String instruction timing 10 8 String instructions D 23 STS special transfer start signal 14 4 SWSR software service register 11 22 SWT see Software watchdog timer Synchronization description 6 6 memory synchronization instructions D 23 clock SYNCCLK signal 15 14 SYPCR system protection...

Page 1102: ...C in transparent mode 30 20 SMC transparent specific parameter RAM 30 21 Trap enable control TECR register 37 27 Trap enable programming 37 15 True little endian TLE mode A 2 TS transfer start signal 3 4 13 5 14 4 14 29 TSIZ0 3 3 TSIZ1 3 3 TSIZn transfer size signals 3 3 13 5 14 4 14 30 U UART mode SMC UART specific parameter ARM 30 10 SMCs 30 9 U bus arbitration and SDMA channels 20 2 UPM program...

Page 1103: ...IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controller Serial Peripheral Interface I C Controller Parallel Interface Port Parallel I O Port CPM Interrupt Controller Digital Signal Processing System Development and Debugging IEEE 1149 1 Tes...

Page 1104: ...IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controller Serial Peripheral Interface I C Controller Parallel Interface Port Parallel I O Port CPM Interrupt Controller Digital Signal Processing System Development and Debugging IEEE 1149 1 Tes...

Page 1105: ... Manual exists in two versions See the Preface for a description of the following two versions PowerPC Microprocessor Family The Programming Environments Rev 1 Order MPCFPE AD PowerPC Microprocessor Family The Programming Environments for 32 Bit Microprocessors Rev 1 Order MPCFPE32B AD Call the Motorola LDC at 1 800 441 2447 website http ldc nmd com or contact your local sales ofÞce to obtain copi...

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