Motorola MPC860 PowerQUICC, User Manual, Page: 665 / 1106

MOTOROLA Chapter 23. SCC UART Mode 23-5
Part V. The Communications Processor Module
23.5 Data-Handling Methods: Character- or
Message-Based
An SCC UART controller uses the same BD table and buffer structures as the other
protocols and supports both multibuffer, message-based and single-buffer, character-based
operation.
For character-based transfers, each character is sent with stop bits and parity and received
into separate 1-byte buffers. A maskable interrupt is generated when each buffer is received.
In a message-based environment, transfers can be made on entire messages rather than on
individual characters. To simplify programming and save processor overhead, a message is
transferred as a linked list of buffers without core intervention. For example, before
handling input data, a terminal driver may wait for an end-of-line character or an idle
timeout rather than be interrupted when each character is received. Conversely, ASCII Þles
can be sent as messages ending with an end-of-line character.
When receiving messages, up to eight control characters can be conÞgured to mark the end
of a message or generate a maskable interrupt without being stored in the buffer. This option
1
From SCC base. SCC base = IMMR + 0x3C00 (SCC1) or 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x3F00 (SCC4)
0x50 CHARACTER1 Hword Control character 1Ð8. These characters deÞne the Rx control characters on
which interrupts can be generated.
0x52 CHARACTER2 Hword
0x54 CHARACTER3 Hword
0x56 CHARACTER4 Hword
0x58 CHARACTER5 Hword
0x5A CHARACTER6 Hword
0x5C CHARACTER7 Hword
0x5E CHARACTER8 Hword
0x60 RCCM Hword Receive control character mask. Used to mask comparison of
CHARACTER1Ð8 so classes of control characters can be deÞned. A one
enables the comparison, and a zero masks it.
0x62 RCCR Hword Receive control character register. Used to hold the last rejected control
character (not written to the Rx buffer). Generates a maskable interrupt. If the
core does not process the interrupt and read RCCR before a new control
character arrives, the previous control character is overwritten.
0x64 RLBC Hword Receive last break character. Used in synchronous UART when PSMR[RZS] =
1; holds the last break character pattern. By counting zeros in RLBC, the core
can measure break length to a one-bit resolution. Read RLBC by counting the
zeros written from bit 0 to where the Þrst one was written. RLBC =
0b001xxxxxxxxxxxxx indicates two zeros; 0b1xxxxxxxxxxxxxxx indicates no
zeros.
Note that RLBC can be used in combination with BRKLN above to measure the
break length down to a bit resolution: (BRKLN + number of zeros in RLBC).
Table 23-1. UART-Specific SCC Parameter RAM Memory Map (Continued)