Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 32. I2C Controller 32-3
Part V. The Communications Processor Module
for the bus during transmission and aborts if it loses arbitration. When the I
2
C controller is
a slave, the SCL clock input shifts data in and out through SDA. The SCL frequency can
range from DC to BRGCLK/48.
32.3 I
2
C Controller Transfers
To initiate a transfer, the master I 2 C controller sends a message specifying a read or write
request to an I 2 C slave. The Þrst byte of the message consists of a R/W request (bit 0) and
the slave port address (bits 1Ð7). To write to a slave, the master sends a write request (R/W
= 0) along with either the target slaveÕs address or a general call address (broadcast),
followed by the data to be written. To read from a slave, the master sends a read request
(R/W = 1) and the target slaveÕs address. When the target slave acknowledges the read
request, the transfer direction is reversed, and the master receives the slaveÕs transmit
buffers. If the receiver (master or slave) does not acknowledge each byte transfer in the
ninth bit frame, the transmitter signals a transmission error event (I2ER[TXE]). An I
2 C
transfer timing diagram is shown in Figure 32-3.
Figure 32-3. I
2
C Transfer Timing
Select master or slave mode for the controller using the I
2
C command register
(I2COM[M/S]). Set the masterÕs start bit, I2COM[STR], to begin a transfer; setting a
slaveÕs I2COM[STR] activates the slave to wait for a transfer request from a master.
If a master or slave transmitterÕs current TxBD[L] is set, transmission stops once the buffer
is sent; that is, I2COM[STR] must be set again to reactivate transfers. If TxBD[L] is zero,
once the current buffer is sent, the controller begins processing the next TxBD without
waiting for I2COM[STR] to be set again.
The following sections further detail the transfer process.
32.3.1 I
2
C Master Write (Slave Read)
If the MPC860 is the master, prepare the transmit buffers and BDs before initiating a write.
Initialize the Þrst transmit data byte with the write request (R/W = 0) and slave address (bits
1Ð7).
If the MPC860 is the slave target of the write, prepare receive buffers and BDs to await the
masterÕs request. Figure 32-4 shows the timing for a master write.
SCL
SDA DATA BYTE
START CONDITION STOP CONDITION
A
C
K
7 8 9 4 5 6 1 2 3