
MOTOROLA
Glossary of Terms and Abbreviations
Glossary--5
Illegal instructions. A class of instructions that are not implemented for a
particular PowerPC processor. These include instructions not deÞned
by the PowerPC architecture. In addition, for 32-bit
implementations, instructions that are deÞned only for 64-bit
implementations are considered to be illegal instructions. For 64-bit
implementations instructions that are deÞned only for 32-bit
implementations are considered to be illegal instructions.
Implementation. A particular processor that conforms to the PowerPC
architecture, but may differ from other architecture-compliant
implementations for example in design, feature set, and
implementation of optional features. The PowerPC architecture has
many different implementations.
Implementation-dependent. An aspect of a feature in a processorÕs design
that is deÞned by a processorÕs design speciÞcations rather than by
the PowerPC architecture.
Implementation-speciÞc. An aspect of a feature in a processorÕs design that
is not required by the PowerPC architecture, but for which the
PowerPC architecture may provide concessions to ensure that
processors that implement the feature do so consistently.
Imprecise exception. A type of synchronous exception that is allowed not to
adhere to the precise exception model (
see
Precise exception). The
PowerPC architecture allows only ßoating-point exceptions to be
handled imprecisely.
Internal bus. The bus connecting the core and system interface unit (SIU).
Instruction latency. The total number of clock cycles necessary to execute
an instruction and make ready the results of that instruction.
Interrupt. An asynchronous exception. On PowerPC processors, interrupts
are a special case of exceptions.
See also
asynchronous exception.
Latency. The time an operation requires. For example, execution latency is
the number of processor clocks an instruction takes to execute.
Memory latency is the number of bus clocks needed to perform a
memory operation.
Least-signiÞcant bit (lsb). The bit of least value in an address, register, data
element, or instruction encoding.
Least-signiÞcant byte (LSB). The byte of least value in an address, register,
data element, or instruction encoding.
L
Summary of Contents for MPC860 PowerQUICC
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Page 36: ...xxxvi MPC860 PowerQUICC UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...
Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
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Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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Page 632: ...21 44 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part V The Communications Processor Module ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
Page 1024: ...B 8 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
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