Motorola MPC860 PowerQUICC, User Manual

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10-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
10.2 Instruction Timing List
Table 10-1 summarizes instruction execution timings in terms of latency and blockage of
the appropriate execution unit. A serializing instruction blocks all execution units.
Table 10-1. Instruction Execution Timing
Instructions Latency Blockage Unit Serializing
Branch: b , ba , bl , bla , bc , bca , bcl , bcla , bclr , bclrl ,
bcctr , bcctl
Taken 2 2 BPU No
Not taken 1 1
System call: sc , rÞ Ser 2 Ñ Yes
CR logical: crand , crxor , cror , crnand , crnor , crandc ,
creqv , crorc , mcrf
1 1 BPU No
Integer trap: twi , tw Taken
ser 3 Ser 3 IU After
Not taken 1 1 No
Move to: mtspr , mtcrf , mtmsr , mcrxr except mtspr to
LR and CTR and to SPRs external to the core.
Ser 1 All Yes
Move to LR, CTR: mtspr 1 1 BPU No
Move to SPRs external to core: mtspr , mttb , mttbu . See
Section 10.2.3, ÒAccessing Off-Core SPRs.Ó
Ser 1
1
Ser 1 LSU Yes
Move from SPRs external to core: mfspr , mftb , mftbu Load latency 1 LSU No
Move from SPRs internal to core: mfspr
2
1 Ñ See list
3
Move from: mfcr , mfmsr Ser 1 Ñ See list
4
Integer arithmetic: addi , add , addis , subf , addic , subÞc ,
addic. , addc , adde , subfc , subfe , addme , addze ,
subfme , subfze , neg
1 IU No
Integer divide: divw , divwu Min 2
Max 11
5
Min 2
Max 11
6
IU No
Integer multiply: mul , mullw , mulhw , mulhwu 2 1-2
7
IU No
Integer compare: cmpi , cmp , cmpli , cmpl 1 IU No
Integer logical: andi. , andis. , ori , oris , xori , xoris , and ,
or , xor , nand , nor , eqv , andc , orc , extsb , extsh , cntlzw
1 IU No
Integer rotate and shift: rlwinm , rlwnm , rlwimi , slw , srw ,
srawi , sraw
1 IU No
Integer load: lbz , lbzu , lbzx , lbzux , lhz , lhzu , lhzx ,
lhzux , lha , lhau , lhax , lhaux , lwz , lwzu , lwzx , lwzux ,
lhbrx , lwbrx.
2
8
1 LSU No
Integer store: stb , stbu , stbx , stbux , sth , sthu , sthx ,
sthux , stw , stwu , stwbrx , stwx , stwux , sthbrx
1
1
1 LSU No
Integer load/store multiple: lmw , smw Ser 1 + no. of registers LSU Yes
Synchronize: sync Ser 1 LSU Yes