Motorola MPC860 PowerQUICC, User Manual

Page: 358 / 1106

14-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
O= Output from the MPC860
I = Input to the MPC860
14.4 Bus Operations
This section provides a functional description of the system bus, the signals that control it,
and the bus cycles provided for data transfers. It also describes error conditions, bus
arbitration, and the reset operation. The MPC860 generates a system clock output
(CLKOUT), which directly sets the bus interface operation frequency. Internally, the
MPC860 uses a phase-lock loop (PLL) circuit to generate a master clock for all CPU
circuitry (including the bus interface), which is phase-locked to CLKOUT.
MPC860 bus interface signals are speciÞed with respect to the rising edge of the external
CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to
that edge. Because the same clock edge is used for driving or sampling bus signals, clock
skew may occur between various modules in a system due to routing or the use of multiple
clock lines. The system must handle any clock skew problems that could occur as a result
of layout, lead length, and physical routing.
14.4.1 Basic Transfer Protocol
The basic transfer protocol deÞnes the sequence of actions required for a complete
MPC860 bus transaction. Figure 14-3 shows a simpliÞcation of the basic transfer protocol.
Arbitration
BR
Bus Request 1 Low I Asserting BR when the internal arbiter is enabled indicates that an external
master is requesting the bus.
O The MPC860 drives BR when the internal arbiter is disabled.
BG
Bus Grant 1 Low O When the internal arbiter is enabled, the MPC860 asserts BG to indicate that an
external master may assume bus mastership and begin a bus transaction. The
device requesting bus mastership should qualify BG to ensure it is the bus owner:
QualiÞed BG = BG & ~ BB
I When the internal arbiter is disabled, BG is sampled and properly qualiÞed by the
MPC860 when an external bus transaction is to be executed by the chip.
BB
Bus Busy 1 Low O When the internal arbiter is enabled, the MPC860 asserts BB to indicate it is bus
master. When the internal arbiter is disabled, the MPC860 asserts BB after the
external arbiter granted mastership to the chip and it is ready to start the transfer.
I When the internal arbiter is enabled, the MPC860 samples this signal to get
indication of when the external master ended its bus tenure (BB negated).
When the internal arbiter is disabled, the BB is sampled, to properly qualify the
BG line, when an external bus transaction is to be executed by the chip.
Arbitration Address transfer Data transfer Termination
Figure 14-3. Basic Transfer Protocol
Table 14-1. MPC860 Signal Overview (Continued)
Signal Pins Active I/O Description