Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 6. MPC860 Instruction Set 6-21
Part II. PowerPC Microprocessor Module
However, eieio could be useful in the rare event that a region where speculative accesses
are not allowed lies in the middle of a non-guarded page.
6.2.5.2.2 isync Behavior
The isync instruction is context synchronizing, which guarantees that all of effects of
previous instructions are in place and any instructions in the instruction queue are ßushed
(which means all instructions that were in the instruction queue need to be refetched). In
the MPC860, fetching an isync instruction causes fetch to stall, so that no refetching is
required. On the MPC860, writes to SPRs and MSR that effect context are automatically
context synchronizing, so an isync is not required before these instructions. However, isync
should be inserted after these instructions to ensure that instructions are fetched in the
appropriate context. Furthermore, load/store instructions that update the MMU page tables
in external memory should both be preceded and followed by an isync, to ensure that
instructions before and after such instructions are fetched and completed in the appropriate
context.
6.2.5.3 Memory Control InstructionsÑVEA
Memory control instructions include the following types:
¥ Cache management instructions
¥ Translation lookaside buffer (TLB) management instructions
This section describes the user-level cache management instructions deÞned by the VEA.
See Section 6.2.6.3, ÒMemory Control InstructionsÑOEA,Ó for information about
supervisor-level cache and translation lookaside buffer management instructions.
The instructions listed in Table 6-19 provide user-level programs the ability to manage
on-chip caches.
As with other memory-related instructions, the effect of the cache management instructions
on memory are weakly ordered. If the programmer needs to ensure that cache or other
instructions have been performed with respect to all other processors and system
mechanisms, a sync instruction must be placed in the program following those instructions.
Note that when data address translation is disabled (MSR[DR] = 0), the Data Cache Block
Set to Zero (dcbz) instruction allocates a cache block in the cache and may not verify that
the physical address is valid. If a cache block is created for an invalid physical address, a
machine check condition may result when an attempt is made to write that cache block back
to memory. The cache block could be written back as a result of the execution of an
instruction that causes a cache miss and the invalid addressed cache block is the target for
replacement or a Data Cache Block Store (dcbst) instruction.