Motorola MPC860 PowerQUICC, User Manual

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18-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
18.2.2.1 Timer Clock Source
The clock input to the prescaler can be selected from three sources:
¥ The general system clock
¥ The general system clock divided by 16
¥ An external source on the corresponding TINx pin
The general system clock (GCLK2) is generated in the clock synthesizer. To save power,
the general system clock can be divided before it leaves the clock synthesizer (slow-go
mode). Regardless of the resulting general system clock frequency, either that frequency or
that frequency divided by 16 can be chosen as the input to the prescaler of each timer. Also,
an external clock source can be supplied on the TINx signal. If two 16-bit timers are
cascaded internally into a 32-bit timer, one timer uses the clock generated by the output of
another timer.
The clock input source is selected by TMRx[ICLK]. The prescaler is programmed in
TMRx[PS] and divides the clock input by values between 1 and 256; the prescaler output
is used as an input to the 16-bit counter. The best resolution of the timer is one clock cycle
(40 ns at 25 MHz). The maximum period is 268,435,456 cycles, which is 10.7 seconds at
25 MHz.
18.2.2.2 Timer Reference Count
TMRx[FRR] (the free-run/restart bit) can be conÞgured so that when a reference is reached
the count either continues or begins again. When the reference value is reached, the
corresponding TERx event bit is set and an interrupt is issued if TMRx[ORI] = 1. Also when
the reference value is reached, timers can output a signal on their timer output pins
(TOUT[1Ð4]). The output signal can be programmed to be an active-low pulse or a toggle
of the current output as selected by TMRx[OM] (the output mode bit).
18.2.2.3 Timer Capture
Each timerÕs 16-bit capture register, TCRx, is used to latch the value of the counter when a
deÞned transition of TINx is sensed by the corresponding input capture edge detector. The
type of transition triggering the capture is selected by TMRx[CE]. When a capture or
reference event occurs, the corresponding TERx event bit is set and a maskable interrupt
request is issued to the CPIC.
18.2.2.4 Timer Gating
Timers can be gated or restarted by one of two external gate signalsÑTGATE1 for timer 1
and/or 2, TGATE2 for timer 3 and/or 4. Normal gate mode enables the count on a falling
edge of TGATEx and disables the count on the rising edge of TGATEx. This allows the
timer to count conditionally, depending on the state of TGATEx.