Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 31. Serial Peripheral Interface 31-11
Part V. The Communications Processor Module
Table 31-4 describes the SPCOM Þelds.
31.5 SPI Parameter RAM
The SPI parameter RAM area begins at the SPI base address. It is similar to the SCC
general-purpose parameter RAM. Some values must be user-initialized before the SPI is
enabled; the CPM initializes the others. Once initialized, parameter RAM values do not
usually need to be accessed. They should be changed only when the SPI is inactive.
Table 31-5 shows the memory map of the SPI parameter RAM.
Table 31-4. SPCOM Field Descriptions
Bits Name Description
0 STR Start transmit. For an SPI master, setting STR causes the SPI to start transferring data to and from the
Tx/Rx buffers if they are prepared. For a slave, setting STR when the SPI is idle causes it to load the Tx
data register from the SPI Tx buffer and start sending with the next SPICLK after SPISEL is asserted.
STR is cleared automatically after one system clock cycle.
1Ð7 Ñ Reserved and should be cleared.
Table 31-5. SPI Parameter RAM Memory Map
Offset
1
Name Width Description
0x00 RBASE Hword Rx/Tx BD table base address. Indicate where the BD tables begin in the dual-port RAM.
Setting Rx/TxBD[W] in the last BD in each BD table determines how many BDs are
allocated for the Tx and Rx sections of the SPI. Initialize RBASE/TBASE before enabling
the SPI. Furthermore, do not conÞgure BD tables of the SPI to overlap any other active
controllerÕs parameter RAM.
RBASE and TBASE should be divisible by eight.
0x02 TBASE Hword
0x04 RFCR Byte Rx/Tx function code. Contains the value to appear on AT[1-3] when the associated
SDMA channel accesses memory. Also controls byte ordering for the transfers. See
Section 31.5.1, ÒReceive/Transmit Function Code Registers (RFCR/TFCR).Ó
0x05 TFCR Byte
0x06 MRBLR Hword Maximum receive buffer length. The SPI has one MRBLR entry to deÞne the maximum
number of bytes the MPC860 writes to a Rx buffer before moving to the next buffer. The
MPC860 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but never
exceeds the MRBLR value. User-supplied buffers should be no smaller than MRBLR.
Tx buffers are unaffected by MRBLR and can have varying lengths; the number of bytes
to be sent is programmed in TxBD[Data Length].
MRBLR is not intended to be changed while the SPI is operating. However it can be
changed in a single bus cycle with one 16-bit move (not two 8-bit bus cycles
back-to-back). The change takes effect when the CPM moves control to the next RxBD.
To guarantee the exact RxBD on which the change occurs, change MRBLR only while
the SPI receiver is disabled. MRBLR should be greater than zero; it should be an even
number if the character length of the data exceeds 8 bits.
0x08 RSTATE Word Rx internal state. Reserved for CPM use.
0x0C Ñ Word The Rx internal data pointer
2
is updated by the SDMA channels to show the next
address in the buffer to be accessed.
0x10 RBPTR Hword RxBD pointer. Points to the current Rx BD being processed or to the next BD to be
serviced when idle. After a reset or when the end of the BD table is reached, the CPM
initializes RBPTR to the RBASE value. Most applications should not modify RBPTR, but
it can be updated when the receiver is disabled or when no Rx buffer is in use.