Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 21. Serial Interface 21-41
Part V. The Communications Processor Module
21.4.2 Autobaud Operation on a UART
During the autobaud process, a UART deduces the baud rate of its received character stream
by examining the received pattern and its timing. A built-in autobaud control function
automatically measures the length of a start bit and modiÞes the baud rate accordingly.
If the autobaud bit BRGCn[ATB] is set, the autobaud control function starts searching for
a low level on the corresponding RXDn input, which it assumes marks the beginning of a
start bit, and begins counting the start bit length. During this time, the BRG output clock
toggles for 16 BRG clock cycles at the BRG source clock rate and then stops with BRGOn
in the low state.
When RXDn goes high again, the autobaud control block rewrites BRGCn[CD, DIV16] to
the divide ratio found, which at high baud rates may not be exactly the Þnal rate desired (for
example, 56,600 could be the result, rather than 57,600). An interrupt can be enabled in the
UART SCC event register to report that the autobaud controller rewrote BRGCn. The
interrupt handler can then adjust BRGCn[CD, DIV16] for accuracy before the Þrst
character is fully received, ensuring that the UART recognizes all characters.
After a full character is received, the software can verify that the character matches a
predeÞned value (such as ÔaÕ or ÔAÕ). Software should then check for other characters (such
as ÔtÕ or ÔTÕ) and program the preferred parity mode in the UARTÕs protocol-speciÞc mode
register (PSMR).
15 EN Enable BRG count. Used to dynamically stop the BRG from countingÑuseful for low-power modes.
0 Stop all clocks to the BRG.
1 Enable clocks to the BRG.
16Ð17 EXTC External clock source. Selects the BRG input clock.
00 BRGCLK (internal clock generated by the clock synthesizer in the SIU).
01 CLK2
10 CLK6
11 Reserved.
18 ATB Autobaud. Selects autobaud operation of the BRG on the corresponding RXD. ATB must remain zero
until the SCC receives the three Rx clocks. Then the user must set ATB to obtain the correct baud rate.
After the baud rate is obtained and locked, it is indicated by setting AB in the UART event register.
0 Normal operation of the BRG.
1 When RXD goes low, the BRG determines the length of the start bit and synchronizes the BRG to
the actual baud rate.
19Ð30 CD Clock divider. CD presets an internal 12-bit counter that is decremented at the DIV16 output rate.
When the counter reaches zero, it is reloaded with CD. CD = 0xFFF produces the minimum clock rate
for BGRO (divide by 4,096); CD = 0x000 produces the maximum rate (divide by 1). When dividing by
an odd number, the counter ensures a 50% duty-cycle by asserting the terminal count once on clock
low and next on clock high. The terminal count signals counter expiration and toggles the clock.
31 DIV16 Divide-by-16. Selects a divide-by-1 or divide-by-16 prescaler before reaching the clock divider.
Table 21-13. BRGCn Field Descriptions (Continued)
Bits Name Description