MOTOROLA
Appendix C. Register Quick Reference Guide
C-1
Appendix C
Register Quick Reference Guide
C0
C0
This section provides a brief guide to the core registers.
C.1 PowerPC RegistersÑUser Registers
The MPC860 implements the user-level registers defined by the PowerPC architecture
except those required for supporting ßoating-point operations (the ßoating-point register
Þle (FPRs) and the ßoating-point status and control register (FPSCR)). User-level,
PowerPC registers are listed in Table C-1 and Table C-2. Table C-2 lists user-level
special-purpose registers (SPRs).
Table C-2 lists SPRs deÞned by the PowerPC architecture implemented on the MPC860.
1
Extended opcode for mftb, 371 rather than 339.
2
Any write (
mtspr
) to this address causes an implementation-dependent software emulation exception.
Table C-1. User-Level PowerPC Registers
Description
Name
Comments
Access Level
Serialize Access
General-purpose
registers
GPRs
The thirty-two 32-bit (GPRs) are used for source
and destination operands.
User
Ñ
Condition register
CR
See Section 5.1.1.1.1, ÒCondition Register
(CR).Ó
User
Only
mtcrf
Table C-2. User-Level PowerPC SPRs
SPR Number
Name
Comments
Serialize Access
Decimal SPR [5Ð9] SPR [0Ð4]
1
00000
00001
XER
Write: Full sync
Read: Sync relative to load/store operations
8
00000
01000
LR
See the
Programming
Environments Manual
No
9
00000
01001
CTR
See the
Programming
Environments Manual
No
268
01000
01100
TBL read
1
Section 11.9, ÒThe
PowerPC Timebase.Ó
Write (as a store)
269
01000
01101
TBU read
2
Summary of Contents for MPC860 PowerQUICC
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Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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