Motorola MPC860 PowerQUICC, User Manual

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37-36 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part VI. Debug and Test
37.5 Development Support Programming Model
The MPC860 implements a set of SPRs, shown in Table 37-14, that support debugging and
reside in the control registers space. They can be accessed using mtspr and mfspr.
The development support/debug registers are protected as described in Table 37-15. Note
the special behavior of the ICR and DPDR.
Table 37-14. MPC860-Specific Development Support and Debug SPRs
SPR Number
Name Serialization Performed in Response to Access
Decimal SPR [5Ð9] SPR [0Ð4]
Development Support Registers
144 00100 10000 CMPA Fetch sync on write
145 00100 10001 CMPB Fetch sync on write
146 00100 10010 CMPC Fetch sync on write
147 00100 10011 CMPD Fetch sync on write
150 00100 10110 COUNTA Fetch sync on write
151 00100 10111 COUNTB Fetch sync on write
152 00100 11000 CMPE Write: Fetch sync
Read: Sync relative to load/store operations
153 00100 11001 CMPF Write: Fetch sync
Read: Sync relative to load/store operations
154 00100 11010 CMPG Write: Fetch sync
Read: Sync relative to load/store operations
155 00100 11011 CMPH Write: Fetch sync
Read: Sync relative to load/store operations
156 00100 11100 LCTRL1 Write: Fetch sync
Read: Sync relative to load/store operations
157 00100 11101 LCTRL2 Write: Fetch sync
Read: Sync relative to load/store operations
158 00100 11110 ICTRL Fetch sync on write
159 00100 11111 BAR Write: Fetch sync
Read: Sync relative to load/store operations. See
Section 5.1.2.1, ÒDAR, DSISR, and BAR Operation.Ó
Debug Registers
148 00100 10100 ICR Fetch sync on write
149 00100 10101 DER Fetch sync on write
630 10011 10110 DPDR Read and Write