Motorola MPC860 PowerQUICC, User Manual

Page: 338 / 1106

13-12 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
ALE_B
DSCK/AT1 See
Section
13.5
J1 Bidirectional
Three-state
Address Latch Enable BÑThis output is asserted when the
MPC860 initiates an access to a region under the control of
the PCMCIA socket B interface.
Development Serial ClockÑThis input is the clock for the
debug port interface.
Address Type 1ÑThe MPC860 drives this bidirectional
three-state line when it initiates a transaction on the external
bus. When the transaction is initiated by the core, it indicates if
the transfer is for user or supervisor state. This signal is not
used for transactions initiated by external masters.
IP_B[0Ð1]
IWP[0Ð1]
VFLS[0Ð1] See
Section
13.5
H2, J3 Bidirectional Input Port B 0Ð1ÑThe MPC860 senses these inputs; their
values and changes are reported in the PIPR and PSCR of the
PCMCIA interface.
Instruction Watchpoint 0-1ÑThese outputs report the
detection of an instruction watchpoint in the program ßow
executed by the core.
Visible History Buffer Flushes StatusÑThe MPC860 outputs
VFLS[0Ð1] when program instruction ßow tracking is required.
They report the number of instructions ßushed from the history
buffer in the core.
IP_B2
IOIS16_B
AT2 Hi-Z J2 Bidirectional
Three-state
Input Port B 2ÑThe MPC860 senses this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
I/O Device B is 16 Bits Port SizeÑThe MPC860 monitors this
input when a PCMCIA interface transaction is initiated to an
I/O region in socket B in the PCMCIA space.
Address Type 2ÑThe MPC860 drives this bidirectional
three-state signal when it initiates a transaction on the external
bus. If the core initiates the transaction, it indicates if the
transfer is instruction or data. This signal is not used for
transactions initiated by external masters.
IP_B3
IWP2
VF2 See
Section
13.5
G1 Bidirectional Input Port B 3ÑThe MPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Instruction Watchpoint 2ÑThis output reports the detection of
an instruction watchpoint in the program ßow executed by the
core.
Visible Instruction Queue Flush StatusÑThe MPC860 outputs
VF2 with VF0/VF1 when instruction ßow tracking is required.
VF
n reports the number of instructions ßushed from the
instruction queue in the core.
IP_B4
LWP0
VF0 Hi-Z G2 Bidirectional Input Port B 4ÑThe MPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 0ÑThis output reports the detection of
a data watchpoint in the program ßow executed by the core.
Visible Instruction Queue Flushes StatusÑThe MPC860
outputs VF0 with VF1/VF2 when instruction ßow tracking is
required. VF
n reports the number of instructions ßushed from
the instruction queue in the core.
Table 13-1. Signal Descriptions (Continued)
Name Reset Number Type Description