Motorola MPC860 PowerQUICC, User Manual

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30-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
R is cleared. In both cases, an interrupt is issued according to the I bit in the BD. By
appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a
speciÞc buffer, or each block is sent. The SMC then proceeds to the next BD. If no
additional buffers have been presented to the SMC for transmission and the L bit was
cleared, an underrun is detected and the SMC begins sending idles.
If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer
on its next access. For instance, if a single TxBD is initialized with the CM and W bits set,
the buffer is sent continuously until R is cleared in the BD.
30.4.4 SMC Transparent Channel Reception Process
When the core enables the SMC receiver in transparent mode, it waits for synchronization
before receiving data. Once synchronization is achieved, the receiver transfers the incoming
data into memory according to the Þrst RxBD in the table. Synchronization can be achieved
in two ways. First, when the receiver is connected to a TDM channel, it can be synchronized
to a time slot. Once the frame sync is received, the receiver waits for the Þrst bit of its time
slot to occur before reception begins. Data is received only during the time slots deÞned by
the TSA. Secondly, when working with its own set of pins, the receiver starts reception
when SMSYN
x
is asserted.
When the buffer full, the SMC clears the E bit in the BD and generates an interrupt if the I
bit in the BD is set. If incoming data exceeds the buffer length, the SMC fetches the next
BD; if it is empty, the SMC continues transferring data to this BDÕs buffer. If the CM bit is
set in the RxBD, the E bit is not cleared, so the CP can automatically overwrite the buffer
on its next access.
30.4.5 Using SMSYN for Synchronization
The SMSYN signal offers a way to externally synchronize the SMC channel. This method
differs somewhat from the synchronization options available in the SCCs and should be
studied carefully. See Figure 30-11 for an example.
Once SMCMR[REN] is set, the Þrst rising edge of SMCLK that Þnds SMSYN low causes
the SMC receiver to achieve synchronization. Data starts being received or latched on the
same rising edge of SMCLK that latched SMSYN. This is the Þrst bit of data received. The
receiver does not lose synchronization again, regardless of the state of SMSYN, until REN
is cleared.
Once SMCMR[TEN] is set, the Þrst rising edge of SMCLK that Þnds SMSYN low
synchronizes the SMC transmitter which begins sending ones asynchronously from the
falling edge of SMSYN. After one character of ones is sent, if the transmit FIFO is loaded
(the TxBD is ready with data), data starts being send on the next falling edge of SMCLK
after one character of ones is sent. If the transmit FIFO is loaded later, data starts being sent
after some multiple number of all-ones characters is sent.