Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 34. Parallel I/O Ports 34-3
Part V. The Communications Processor Module
Port A signals selected for general-purpose I/O can be accessed through the port A data
register (PADAT). Data written to PADAT is stored in an output latch. For port A outputs,
the latch data is gated onto the signal. When PADAT is read, the signal itself is read. For
inputs, data written to PADAT is also stored in the output latch but cannot reach the port
signal, so when PADAT is read, the signalÕs state is read. If an input to a peripheral is not
supplied from a signal, the default value listed in Table is supplied.
34.2.1 Port A Registers
Port A has four memory-mapped control registers, described in the following sections.
34.2.1.1 Port A Open-Drain Register (PAODR)
The port A open-drain register (PAODR), shown in Figure 34-1, determines which port
signals with serial channel output capability are conÞgured in a normal or wired-OR
conÞguration. Setting the PAODR bits conÞgure the signals for open-drain operation.
1
Clearing the corresponding PADIR bit makes the signal an input; setting PADIR makes it an output.
2
Available for MPC860 Rev. B and later only when PA9 or PA8 is not used as RXD4 or TXD4 functions.
3
Available for MPC860 Rev. B and later.
4
Multi-function peripheral input signals, such as CLK1/TIN1/L1RCLKA, can perform multiple functions
simultaneously. (That is, a clock supplied at PA7 can be used for both CLK1 and TIN1.)
1
Available for MPC860 Rev. B and later.
PA6 PORT A6 CLK2 TOUT1 CLK2 = GND
PA5 PORT A5 CLK3/TIN2/L1TCLKA
4
BRGO2 CLK3/TIN2/L1TCLKA = BRGO2
PA4 PORT A4 CLK4 TOUT2 CLK4 = CLK8
PA3 PORT A3 CLK5/TIN3
4
BRGO3 CLK5/TIN3 = BRGO3
PA2 PORT A2 CLK6/L1RCLKB
4
TOUT3 CLK6/L1RCLKB = GND
PA1 PORT A1 CLK7/TIN4
4
BRGO4 CLK7/TIN4 = BRGO4
PA0 PORT A0 CLK8/L1TCLKB
4
TOUT4 CLK8/L1TCLKB = GND
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ OD8
1
OD9 OD10
1
OD11 OD12 Ñ OD14 Ñ
Reset 0
R/W R/W
Addr 0x954
Figure 34-1. Port A Open-Drain Register (PAODR)
Table 34-1. Port A Pin Assignment (Continued)
Signal
Pin Function
PAPAR[DDn] = 0
(General I/O)
1
PAPAR[DDn] = 1
Input to On-Chip Peripherals
(Default)
PADIR[DRn] = 0 PADIR[DRn] = 1