Motorola MPC860 PowerQUICC, User Manual

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13-20 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
1
Pulled Low if RSTCONF pulled down
2
High until SPLL locked, then oscillating
3
Available for MPC860 Rev. B and later only when PA9 or PA8 is not used as RXD4 or TXD4 functions.
4
Available for MPC860 Rev. B and later.
5
Pulled up on rev 0 to rev A.3
6
Hi-Z on rev 0 to rev A.3
PD[5]
REJECT2 Hi-Z U15 Bidirectional General-Purpose I/O Port D Bit 5ÑBit 5 of the
general-purpose I/O port D.
REJECT2ÑThis input to SCC2 allows a CAM to reject the
current Ethernet frame after it determines the frame address
did not match.
PD[4]
REJECT3 Hi-Z U16 Bidirectional General-Purpose I/O Port D Bit 4ÑBit 4 of the
general-purpose I/O port D.
REJECT3ÑThis input to SCC3 allows a CAM to reject the
current Ethernet frame after it determines the frame address
did not match.
PD[3]
REJECT4 Hi-Z W16 Bidirectional General-purpose I/O Port D Bit 3ÑBit 3 of the
general-purpose I/O port D.
REJECT4ÑThis input to SCC4 allows a CAM to reject the
current Ethernet frame after it determines the frame address
did not match.
TCK
DSCK Hi-Z
5
H16 Input Provides clock to scan chain logic or for the development port
logic.
TMS Pulled
up G18 Input Controls the scan chain test mode operations.
TDI
DSDI Pulled
up
6
H17 Input Input serial data for either the scan chain logic or the
development port and determines the operating mode of the
development port at reset.
TDO
DSDO Low G17 Output Output serial data for either the scan chain logic or for the
development port.
TRST Pulled
up
G19 Input Reset for the scan chain logic.
SPARE[1Ð4] Hi-Z B7, H18,
V15, H4
No-connect Spare signalsÑNot used on current chip revisions. Leave
unconnected.
Power Supply See
Figure 13-2
Power VDDLÑPower supply of the internal logic.
VDDHÑPower supply of the I/O buffers and certain parts of
the clock control.
VDDSYNÑPower supply of the PLL circuitry.
KAPWRÑPower supply of the internal OSCM, RTC, PIT, DEC,
and TB.
VSSÑGround for circuits, except for the PLL circuitry.
VSSSYN, VSSSYN1ÑGround for the PLL circuitry.
Table 13-1. Signal Descriptions (Continued)
Name Reset Number Type Description