Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 18. Communications Processor Module and CPM Timers 18-9
Part V. The Communications Processor Module
18.2.3.2 Timer Mode Registers (TMR1ÐTMR4)
The timer mode registers (TMR1ÐTMR4), shown in Figure 18-6, are identical. Before
modifying TMRx, reset the timer by clearing TGCR[RSTx].
Table 18-2 describes the TMR Þelds.
8 CAS2 Cascade timers.
0 Normal operation.
1 Timers 1 and 2 are cascaded to form a 32-bit timer.
12 GM1 Gate mode for TGATE1. Valid only if TMR1[GE] or TMR2[GE] is set.
0 Restart gate mode. A falling TGATE1 enables and restarts the count and a rising edge of TGATE1
disables the count.
1 Normal gate mode. This mode is the same as 0, except the falling edge of TGATE1 does not restart
the count value in the TCN.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field PS CE OM ORI FRR ICLK GE
Reset 0
R/W R/W
Addr 0x990 (TMR1), 0x992 (TMR2), 0x9A0 (TMR3), 0x9A2 (TMR4)
Figure 18-6. Timer Mode Registers (TMR1ÐTMR4)
Table 18-2. TMR1ÐTMR4 Field Descriptions
Bits Name Description
0Ð7 PS Prescaler value. The prescaler is programmed to divide the clock input by a value between 1 and
256. A 0x00 value divides the clock by 1; 0xFF divides it by 256.
8Ð9 CE Capture edge and enable Interrupt.
00 Disable interrupt on capture event; capture function is disabled.
01 Capture on rising TINx edge only and enable interrupt on capture event.
10 Capture on falling TINx edge only and enable interrupt on capture event.
11 Capture on any TINx edge and enable interrupt on capture event.
10 OM Output mode.
0 Active-low pulse on TOUTx for one timer input clock cycle as deÞned by ICLK. Thus, TOUTx may
be low for one general system clock period, one general system clock/16 period, or one TINx clock
cycle period. Changes to TOUTx occur on the falling edge of the system clock.
1 Toggle TOUTx. Changes to TOUTx occur on the falling edge of the system clock.
11 ORI Output reference interrupt enable.
0 Disable interrupt for reference that is reached. Does not affect an interrupt on the capture function.
1 Enable interrupt when the reference value is reached.
12 FRR Free run/restart.
0 Free run. The timer count continues to increment after the reference value is reached.
1 Restart. The timer count is reset immediately after the reference value is reached.
Table 18-1. TGCR Field Descriptions (Continued)
Bits Name Description