Motorola MPC860 PowerQUICC, User Manual

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32-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
Figure 32-4. I
2
C Master Write Timing
A master write performed by the MPC860 occurs as follows:
1. Set the masterÕs I2COM[STR]. The transfer starts when the SDMA channel loads
the transmit FIFO with data and the I
2
C bus is not busy.
2. The I 2 C master generates a start conditionÑa high-to-low transition on SDA while
SCL is highÑand the transfer clock SCL pulses for each bit shifted out on SDA. If
the master transmitter detects a multiple-master collision (by sensing a Ô0Õ on SDA
while sending a Ô1Õ), transmission stops and the channel reverts to slave mode. A
maskable interrupt is sent to the masterÕs core so software can try to retransmit later.
3. The slave acknowledges each byte and writes to its current receive buffer until a new
start or stop condition is detected.
4. After sending each byte, the master monitors the acknowledge indication. If the
slave receiver fails to acknowledge a byte, transmission stops and the master
generates a stop conditionÑa low-to-high transition on SDA while SCL is high.
32.3.2 I 2 C Loopback Testing
When in master mode, an I 2 C controller supports loopback operation for master write
requests. The master I 2 C controller simply issues a write request directed to its own address
(programmed in I2ADD). The masterÕs receiver monitors the transmission and reads the
transmitted data into its receive buffer. Loopback operation requires no special register
programming.
32.3.3 I 2 C Master Read (Slave Write)
Before initiating a master read with the MPC860, prepare a transmit buffer of size
n
+1
bytes, where
n
is the number of bytes to be read from the slave. The Þrst transmit byte
should be initialized to the slave address with R/W = 1. The next
n
transmit bytes are used
strictly for timing and can be left uninitialized. ConÞgure suitable receive buffers and BDs
to receive the slaveÕs transmission.
If the MPC860 is the slave target of the read, prepare the I 2 C transmit buffers and BDs and
activate it by setting I2COM[STR]. Figure 32-5 shows the timing for a master read.
SDA DEVICE ADDRESS
W
DATA BYTE
S
T
A
R
T
S
T
O
P
A
C
K A
C
K
NOTE: DATA AND ACK ARE REPEATED N TIMES.