Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 4. The PowerPC Core 4-15
Part II. PowerPC Microprocessor Module
Table 4-3 summarizes MPC860 features with respect to the UISA deÞnition.
Table 4-3. UISA-Level Features
Functionality Description
Reserved Þelds Reserved Þelds in instructions are described under the speciÞc instruction deÞnition in Chapter 6,
ÒMPC860 Instruction Set.Ó Unless otherwise stated, instruction Þelds marked I, II, and III are
discarded during decoding. Thus, this type of instruction yields results of the deÞned instructions
with the appropriate Þeld = 0. In most cases, reserved Þelds in registers are ignored on write and
return zeros for them on read for any control register implemented by the core. Exceptions are
XER[16Ð23] and the reserved bits of MSR, which are set by the source value on write and return
the value last set for it on read.
Classes of
Instructions Required instructions (except ßoating-point load, store, and compute instructions) are
implemented in hardware. Optional instructions are executed by implementation-dependent code;
any attempt to execute one of these commands causes the core to take the software emulation
exception (offset 0x01000). Illegal and reserved instruction class instructions are supported by
implementation-dependent code and, thus the core hardware generates a software emulation
exception.
Exceptions Invocation of the system software for any exception caused by an instruction in the core is precise,
regardless of the type and setting.
Fetching
instructions The core fetches a number of instructions into its IQ from which they are dispatched to the
execution units. If a program modiÞes instructions, it should call a system library program to
ensure that the instruction fetching mechanism can detect changes before execution.
Branch
instructions The core implements all UISA instructions deÞned for the branch processor in hardware. For
details about the performance of various instructions, see Table 4-1.
Invalid branch
instruction forms Bits marked with z in the BO encoding deÞnition default to z = 0 and are discarded by the core
decoding. Thus, these instructions yield results of deÞned instructions for which z = 0. If the
decrement and test CTR option is speciÞed for the
bcctr or bcctrl instructions, the target address
of the branch is the new value of the CTR. Condition is evaluated correctly, including the value of
the counter after decrement.
Branch prediction The core uses the y bit to predict path for prefetch. Prediction is only done for not-ready branch
conditions. No prediction is done for branches to the link or count register if the target address is
not ready (see Table 4-1).
Integer processor The core implements the following integer instructions:
¥ Arithmetic instructions
¥ Compare instructions
¥ Trap instructions
¥ Logical instructions
¥ Rotate and shift instructions
Move to/from
SPR instructions Move to/from invalid SPRs in which SPR[0] = 1 invokes the privileged instruction error exception
handler if the processor is in user mode.
Integer arithmetic
instructions Attempting to use divw to perform either 0x80000000
¸
-1 or <anything>
¸
0 sets the contents of
r D to 0x80000000 and if Rc =1, the contents CR0 are LT = 1, GT = 0, and EQ = 0. SO is set to the
correct value.
In the
cmpi , cmp , cmpli , and cmpl instructions, the L bit is applicable for 64-bit implementations.
For the MPC860, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the
behavior when L = 1 is identical to the valid form instruction with L = 0.
Integer
load/store with
update
instructions For load with update and store with update instructions where r A = 0, the EA is written into r 0. For
load with update instructions where r A = r D, r A is boundedly undeÞned.