Motorola MPC860 PowerQUICC, User Manual

Page: 151 / 1106

MOTOROLA Chapter 6. MPC860 Instruction Set 6-1
Chapter 6
MPC860 Instruction Set
60
60
This chapter describes the PowerPC instructions implemented by the MPC860. These
instructions are organized by the level of architecture in which they are implementedÑ
UISA, VEA, and OEA. These levels are described in Section 4.1.1, ÒLevels of the PowerPC
Architecture.Ó
6.1 Operand Conventions
This section describes the operand conventions as they are represented in two levels of the
PowerPC architecture. It also provides detailed descriptions of conventions used for storing
values in registers and memory, accessing the MPC860Õs registers, and representation of
data in these registers.
6.1.1 Data Organization in Memory and Data Transfers
Bytes in memory are numbered consecutively starting with 0. Each number is the address
of the corresponding byte.
Memory operands may be bytes, half words, words, or double words, or, for the load/store
multiple and move assist instructions, a sequence of bytes or words. The address of a
memory operand is the address of its Þrst byte (that is, of its lowest-numbered byte).
6.1.2 Aligned and Misaligned Accesses
The operand of a single-register memory access instruction has a natural alignment
boundary equal to the operand length. In other words, the natural address of an operand is
an integral multiple of the operand length. A memory operand is said to be aligned if it is
aligned at its natural boundary; otherwise it is misaligned.
Operands for single-register memory access instructions have the characteristics shown in
Table 6-1. (Although not permitted as memory operands, quad words are shown because
quad-word alignment is desirable for certain memory operands.)