Motorola MPC860 PowerQUICC, User Manual

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9-4 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
The MMU supports a multiple virtual address space model. Each translation is associated
with an ASID, which must equal the address space ID (CASID) for a translation to be valid.
Figure 9-1 shows the ßow for a read access or instruction fetch.
Figure 9-1. Read/Instruction Fetch Flow Diagram
Figure 9-2 shows the ßow for a load/store access, assuming translation is enabled. Because
data transfers have less locality than instruction fetches, the DMMU does not implement a
fast TLB mechanism. The DTLB is accessed for each transfer simultaneously with the data
cache tag read, hence there is no time penalty.
Data/Instruction Fetch
Same page
(Fast TLB Hit)
?
TLB
Hit
?
TLB reload (read page
description from external
memory to TLB)
Use current page description
Yes
No
Yes
No
32-bit EA is generated
Compare address
with TLB
Entries
Is page
valid
?
Yes
No
TLB error exception
Access permitted
by page protection
?
Yes
No
Use page description from TLB
(1 clock penalty)
(20Ð23 clock penalty
@ one wait-state
external memory)