Motorola MPC860 PowerQUICC, User Manual

Page: 231 / 1106

MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-5
Part II. PowerPC Microprocessor Module
Figure 9-2. Flow of Load/Store Access
9.3.3 TLB Operation
Each TLB contains pointers to pages in physical memory where data is indexed by the EPN.
TLBs entries can have different page sizes. The entry page size determines which EA bits
are compared and how many of its lsbs pass untranslated as physical address bits.
For a 4-Kbyte page, four subpage validity ßags are supported, allowing any combination of
1-Kbyte subpages to be mapped. For any other page size, all of these ßags should have the
same value. Programming non-4-Kbyte pages with different valid bits is a programming
error. Subpage validity ßags can be manipulated to implement 1Ð4 Kbyte pages or any other
combination of 1-Kbyte subpages. However, all subpages of an effective page frame must
map to the same physical page. During translation, the EA, the privilege level (MSR[PR]),
and CASID are provided to the TLB, as shown in Figure 9-3. In the TLB, the EA and
CASID are compared with each entryÕs EPN and ASID. The CASID is compared only
when the matching entry is programmed as unshared. See Table 9-11 and Table 9-12.
Data/Instruction Fetch
TLB
Hit
?
TLB reload (read page
description from external
memory to TLB)
Yes
No
32-bit EA is generated
Compare address
with TLB
entries
Is page
valid
?
Yes
No
TLB error exception
Access permitted
by page protection
?
Yes
No
Use page description from TLB
(0 clock penalty)
(20Ð23 clock penalty
@ one wait-state
external memory)