Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 4. The PowerPC Core 4-7
Part II. PowerPC Microprocessor Module
4.3.2 Basic Instruction Pipeline
Figure 4-3 shows instruction pipeline timing, showing how by distributing the processes
required to fetch, execute, and retire an instruction into stages, multiple instructions can be
processed during a single clock cycle.
Figure 4-3. Basic Instruction Pipeline Timing
4.3.3 Instruction Unit
The instruction unit implements the basic instruction pipeline, fetches instructions from the
memory system, dispatches them to available execution units, and maintains a state history
to ensure a precise exception model and that operations Þnish in order. The instruction unit
implements all branch processor instructions, including ßow control and CR instructions.
Table 10-1 describes instruction latencies.
4.3.3.1 Branch Operations
Because branch instructions can change program ßow and because most branches cannot
be resolved at the same time they are fetched, program branching can keep a processor from
operating at maximum instruction throughput.
If a branch is mispredicted, additional time is required to ßush the incorrect branch
instructions and begin fetching from the correct target stream, which can create bubbles in
the pipeline. To reduce the latency caused by misprediction, PowerPC branch instructions
allow the programmer to indicate whether a branch is likely to be taken. This is called static
branch prediction.
lwz sub mulli addi addic
Fetch
Decode
Read + Execute
Writeback
L Address Drive
L Data
Load Write Back
lwz sub
Bubble
addic
lwz sub
sub
addic
ld
ld
ld
Gclk1
addic