Motorola MPC860 PowerQUICC, User Manual, Page: 422 / 1106

15-28 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
6 TBS Timebase Source. Determines the clock source that drives the timebase and decrementer.
0 = Timebase frequency source is the OSCCLK divided by 4 or 16.
1 = Timebase frequency source is GCLK2 divided by 16.
7 RTDIV Real-Time Clock Divide. Determines if the clock, the crystal oscillator or main clock oscillator, to the
real-time clock and periodic interrupt timer is divided by 4 or 512. At power-on reset this bit is
cleared if the MODCK1 and MODCK2 signals are low.
0 = The clock is divided by 4.
1 = The clock is divided by 512.
8 RTSEL Real-Time Clock Select. Selects the crystal oscillator or main clock oscillator as the input source to
PITRTCLK. At power-on reset, it reßects the value of MODCK1.
0 = OSCM (crystal oscillator) is selected.
1 = EXTCLK is selected.
9 CRQEN CPM Request Enable. Cleared by power-on or hard reset. In low-power modes, speciÞes if the
general system clock returns to high frequency while the CP is active.
0 The system remains in low frequency even if the communication processor module is active.
1 The system switches to high frequency when the communication processor module is active.
10 PRQEN Power Management Request Enable. In low-power modes, speciÞes whether the general system
clock returns to a high frequency when a pending interrupt from the interrupt controller or
MSR[POW] is clear (normal mode). Cleared by power-on or hard reset.
0 =The system remains in low frequency even if there is a pending interrupt from the interrupt
controller or MSR[POW] = 0 (normal mode).
1 =The system switches to high frequency when there is a pending interrupt from the Interrupt
controller or MSR[POW] = 0.
11Ð12 Ñ Reserved, should be cleared.
13Ð14 EBDF External Bus Division Factor. This Þeld deÞnes the frequency division factor between GCLKx and
GCLKx_50. CLKOUT is similar to GCLK2_50. The GCLKx_50 is used by the bus interface and
memory controller to interface with an external system. This Þeld is initialized during hard reset
using the hard reset conÞguration word in Section 12.3.1.1, ÒHard Reset ConÞguration Word.Ó
00 = CLKOUT is GCLK2 divided by 1.
01 = CLKOUT is GCLK2 divided by 2.
1x = Reserved.
15Ð16 Ñ Reserved, should be cleared.
17Ð18 DFSYNC Division Factor for the SYNCCLK. This Þeld sets the VCOOUT frequency division factor for the
SYNCCLK signal. Changing the value of this Þeld does not result in a loss-of-lock condition. This
Þeld is cleared by a power-on or hard reset.
00 = Divide by 1 (normal operation).
01 = Divide by 4.
10 = Divide by 16.
11 = Divide by 64.
19Ð20 DFBRG Division Factor of the BRGCLK. This Þeld sets the VCOOUT frequency division factor for the
BRGCLK signal. Changing the value of this Þeld does not result in a loss-of-lock condition. This
Þeld is cleared by a power-on or hard reset.
00 = Divide by 1 (normal operation).
01 = Divide by 4.
10 = Divide by 16.
11 = Divide by 64.
Table 15-8. SCCR Field Descriptions (Continued)
Bits Name Description