Motorola MPC860 PowerQUICC, User Manual, Page: 882 / 1106

33-22 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
33.9.2 PIP as a Centronics Receiver
If the current BD in the RxBD table is empty and a character is received from the
Centronics interface, the PIP receiver Þrst compares the character against the user-deÞned
control character table. If no match is found, the character is written to the buffer. If a match
is found, the control character is either written to the Rx buffer or rejected, depending on
the reject bit in the control character table. If rejected, the character is written to the received
control character register (RCCR) in the PIP Rx parameter RAM and a maskable interrupt
is generated when the BD Þnishes processing. Note that a single received data frame can
span several buffers.
For each transfer, the PIP controller generates ACK and BUSY handshake signals on the
Centronics interface. The ACK pulse width and the timing of BUSY with respect to ACK
are determined by the timing parameter register PTPR.
Figure 33-22 shows the PIP conÞgured as a Centronics receiver. The SELECT, PERROR,
and FAULT signals shown are not automatically generated; they are controlled by software
and driven on general-purpose outputs.
Figure 33-22. PIP as a Centronics Receiver
33.9.2.1 Centronics Rx Errors and the PIPE
The Centronics receiving error is described in Table 33-14.
The relevant PIPE event bits for Centronics receiving are CCR, BSY, RCH, and RXB; see
Section 33.4.2, ÒPIP Event Register (PIPE).Ó For core-controlled receiving, only the
character-based RCH interrupt applies.
Table 33-14. Centronics Rx Error
Error Description
BD Busy The current BD to be processed is not empty. PIPE[BSY] is ßagged. The channel resumes receiving after
user software prepares the BD.
PB31
PB30 SELECT
BUSY
ACK
STB
PB28 FAULT
PB29 PERROR
Host
MPC860
(Centronics Device)
Data[0:7] PB[16:23]
PB14
PB15
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