Motorola MPC860 PowerQUICC, User Manual, Page: 607 / 1106

MOTOROLA Chapter 21. Serial Interface 21-19
Part V. The Communications Processor Module
6Ð7,
22Ð23 RFSD x Receive frame sync delay for TDMa/b. Indicates the delay between the Rx sync and the Þrst bit of
the Rx frame. Even if CRT
x is set, RFSD x does not control the Tx frame delay.
00 No bit delay. The Þrst bit of the frame is received on the same clock as sync. Use for GCI.
01 1-bit delay. Use for IDL.
10 2-bit delay.
11 3-bit delay.
See the examples in Figure 21-14 and Figure 21-15.
8, 24 DSC x Double speed clock for TDMa/bÑfor TDM interfaces, such as GCI, that deÞne the input clock to
be twice as fast as the data rate.
0 Channel clock (L1RCLK
x and/or L1TCLK x ) is equal to the data clock. Use for IDL and most
other TDM formats.
1 Channel clock rate is twice the data rate. Use for GCI.
9, 25 CRT x Common receive and transmit pins for TDMa/b.
0 Separate pins. The receive section of the TDM uses L1RCLK
x and L1RSYNC x for framing; the
transmit section uses L1TCLK x and L1TSYNC x for framing.
1 Common pins. Both the transmit and receive section use L1RCLK x as the clock pin of the
channel and L1RSYNC x as the sync pin. Use for IDL and GCI. Useful when the transmit and
receive section of a given TDM share clock and sync signals. L1TCLK x and L1TSYNC x can be
used for general-purpose I/O.
10, 26 STZ x Set L1TXD x to zero for TDMa/b.
0 Normal operation.
1 L1TXD
x is cleared until serial clocks are availableÑuseful for GCI activation; see
Section 21.2.6.1, ÒGCI Activation/Deactivation.Ó
11, 27 CE x Clock edge for TDMa/b.
When DSC
x = 0:
0 Data is sent on the rising clock edge and received on the falling edge (use for IDL and GCI).
1 Data is sent on the falling edge of the clock and received on the rising edge.
When DSC
x = 1:
0 Data is sent on the rising clock edge and received on the rising edge.
1 Data is sent on the falling edge of the clock and received on the falling edge.
12, 28 FE x Frame sync edge for TDMa/b. Indicates when L1RSYNC x and L1TSYNC x pulses are sampled
with the falling/rising edge of the channel clock.
0 Falling edge. Use for IDL and GCI.
1 Rising edge.
13, 29 GM x Grant mode for TDMa/b.
0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is supported
internally. The grant is signalled by one bit of the Rx frame and is marked by setting
SIRAM[CSEL] to 111 to assert an internal strobe. See
Section 21.2.6.2.2, ÒSCIT Mode.Ó
1 IDL mode. A grant mechanism is supported if the corresponding SICR[GR n ] are set. The grant
is a sample of the L1GR x signal while L1TSYNC x is asserted. This grant mechanism implies
the IDL access controls transmission on the D channel. See Section 21.2.5.2, ÒProgramming
the IDL Interface.Ó
Note that for the MPC860 Rev. B and later, if GMa = 1, then the RTS4 signal on ports B and C
functions as L1RQa. (The RTS4 function is still available on port D.)
Note that for the MPC860 Rev. B and later, if GMb = 1, then the RTS3 signal on ports B and C
functions as L1RQB. (The RTS3 function is still available on port D.)
Table 21-5. SIMODE Field Descriptions (Continued)
Bits Name Description