Motorola MPC860 PowerQUICC, User Manual

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21-34 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
channel 2 to logic high. The MPC860 then aborts its transmission and resends the frame
when this bit is driven to logic low again. This procedure is automatically handled for the
Þrst two buffers of a frame.
21.2.6.1 GCI Activation/Deactivation
In the deactivated state, the clock pulse is disabled and the data line is at a logic one. The
layer-1 device activates the MPC860 by enabling the clock pulses and sending an indication
on the C/I channel 0. To report the arrival of a valid indication in the SMCÕs RxBD, the
CPM sends a maskable interrupt to the core.
When the core activates the line, the data output of L1TXDx should be programmed to zero
by setting SIMODE[STZx]. Code 0 (command timing TIM) is sent on C/I channel 0 to the
layer-1 device until STZx is cleared. The physical layer device resumes the clock pulses and
gives an indication on C/I channel 0. The core should then clear STZx to enable data output.
21.2.6.2 Programming the GCI Interface
The two GCI interface modes, normal and SCIT, are described in the following sections.
21.2.6.2.1 Normal Mode
For normal mode operation, Þrst program the channelsÕ SIMODE[DSCx, FEx, CEx,
RFSDx] for GCI/SCIT mode, deÞning the sync pulse to GCI sync for framing and the data
clock as one-half the input clock rate. Also, if the receive and transmit sections are used to
interface with the same GCI bus, set SIMODE[CRTx] to internally connect the Rx clock
and sync signals to the SI RAM transmit section. Then deÞne the GCI frame routing and
strobe select using the SI RAM.
When the receive and transmit sections use the same clock and sync signals, the sections
should use the same conÞguration. Also, L1TXDx in the I/O register should be conÞgured
as an open-drain output. To support the monitor and C/I channels in GCI, those channels
should be routed to an SMC. To support the D channel when there is no possibility of
collision, clear SICR[GRx] for the SCC that supports the D channel.
21.2.6.2.2 SCIT Mode
To interface with the GCI/SCIT bus, conÞgure SIMODE for basic GCI/SCIT operation.
Then program the SI RAM to support a 96-bit frame length and the frame sync to be the
GCI sync pulse. Generally, the SCIT bus supports the D channel access collision
mechanism. For this purpose, set SIMODE[CRTx] so the receive and transmit sections use
the same clock and sync signals and program SICR[GRx] to transfer the D channel grant
to the supporting SCC. The received bit (grant) should be marked by programming the
CSEL (channel select) bits of the SI RAM to 0b111 for an internal assertion of a strobe.
This bit is sampled by the SI and transferred to the D-channel SCC as the grant. The grant
is generally bit 4 of the C/I in channel 2 of the GCI bus, but any bit slot can be selected in
the SI RAM.