MOTOROLA
Chapter 22. Serial Communications Controllers
22-13
Part V. The Communications Processor Module
Figure 22-7. SCC BD and Buffer Memory Structure
In all protocols, BDs can point to buffers in the internal dual-port RAM. However, because
internal RAM is used for descriptors, buffers are usually put in external RAM, especially if
they are large. Usually, the internal U bus transfers data to the buffer.
The CP processes TxBDs in a straightforward manner. Once the transmit side of an SCC is
enabled, it starts with the Þrst BD in that SCC TxBD table. Once the CP detects that the R
bit is set in the TxBD, it starts processing the buffer. The CP detects that the BD is ready
when it polls the R bit or when the user writes to the TODR. After data from the BD is put
in the Tx FIFO, if necessary the CP waits for the next descriptorÕs R bit to be set before
proceeding. Thus, the CP does no look-ahead descriptor processing and does not skip BDs
that are not ready. When the CP sees a BDÕs W bit (wrap) set, it returns to the start of the
BD table after this last BD of the table is processed. The CP clears R (not ready) after using
a TxBD, which keeps it from being retransmitted before it is conÞrmed by the core.
However, some protocols support a continuous mode (CM), for which R is not cleared
(always ready).
The CP uses RxBDs similarly. When data arrives, the CP performs required processing on
the data and moves resultant data to the buffer pointed to by the Þrst BD; it continues until
the buffer is full or an event, such as an error or end-of-frame detection, occurs. The buffer
is then closed; subsequent data uses the next BD. If E = 0, the current buffer is not empty
and it reports a busy error. The CP does not move from the current BD until E is set by the
Status and Control
Buffer Length
Buffer Pointer
SCC
x
TxBD
Table Pointer
SCC
x
RxBD
Table Pointer
SCC
x
RxBD
Table
SCC
x
TxBD
Table
Dual-Port RAM
Status and Control
Buffer Length
Buffer Pointer
Tx Buffer
External Memory
Rx Buffer Descriptors
Tx Buffer Descriptors
Rx Buffer
Summary of Contents for MPC860 PowerQUICC
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Page 78: ...I iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part I Overview ...
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Page 226: ...8 32 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part II PowerPC Microprocessor Module ...
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Page 274: ...III iv MPC860 PowerQUICC UserÕs Manual MOTOROLA Part III Configuration ...
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Page 325: ...MOTOROLA Part IV Hardware Interface IV v Part IV Hardware Interface ...
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Page 998: ...37 48 MPC860 PowerQUICC UserÕs Manual MOTOROLA Part VI Debug and Test ...
Page 1016: ...A 10 MPC860 PowerQUICC UserÕs Manual MOTOROLA Appendixes ...
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