Motorola MPC860 PowerQUICC, User Manual, Page: 1083 / 1106

MOTOROLA Glossary of Terms and Abbreviations Glossary--9
Register indirect addressing. A form of addressing that speciÞes one GPR
that contains the address for the load or store.
Register indirect with immediate index addressing. A form of addressing
that speciÞes an immediate value to be added to the contents of a
speciÞed GPR to form the target address for the load or store.
Register indirect with index addressing. A form of addressing that speciÞes
that the contents of two GPRs be added together to yield the target
address for the load or store.
Reservation. The processor establishes a reservation on a cache block of
memory space when it executes an lwarx instruction to read a
memory semaphore into a GPR.
Reserved Þeld. In a register, a reserved Þeld is one that is not assigned a
function. A reserved Þeld may be a single bit. The handling of
reserved bits is implementation-dependent. Software is permitted to
write any value to such a bit. A subsequent reading of the bit returns
0 if the value last written to the bit was 0 and returns an undeÞned
value (0 or 1) otherwise.
RISC (reduced instruction set computing). An architecture characterized
by Þxed-length instructions with nonoverlapping functionality and
by a separate set of load and store instructions that perform memory
accesses.
Scalability. The capability of an architecture to generate implementations
speciÞc for a wide range of purposes, and in particular
implementations of signiÞcantly greater performance and/or
functionality than at present, while maintaining compatibility with
current implementations.
Scan chain. The peripheral buffers of a device, linked in JTAG test mode, that
are addressed in a shift-register fashion.
Set (v). To write a nonzero value to a bit or bit Þeld; the opposite of clear. The
term ÔsetÕ may also be used to generally describe the updating of a
bit or bit Þeld.
Set (n). A subdivision of a cache. Cacheable data can be stored in a given
location in any one of the sets, typically corresponding to its
lower-order address bits. Because several memory locations can map
to the same location, cached data is typically placed in the set whose
cache block corresponding to that address was used least recently.
See Set-associative.
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