Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 30. Serial Management Controllers 30-7
Part V. The Communications Processor Module
To extract data from a partially full Rx buffer, issue a
CLOSE RXBD
command.
Certain parameter RAM values must be initialized before the SMC is enabled. Other values
are initialized or written by the CP. Once values are initialized, software typically does not
need to update them because activity centers mostly around Tx and Rx BDs rather than
parameter RAM. However, note the following:
¥ Parameter RAM can be read at any time.
¥ Values that pertain to the SMC transmitter can be written only if SMCMR[TEN] is
zero or between the
STOP TRANSMIT
and
RESTART TRANSMIT
commands.
¥ Values for the SMC receiver can be written only when SMCMR[REN] is zero, or, if
the receiver is previously enabled, after an
ENTER HUNT MODE
command is issued
but before the
CLOSE RXBD
command is issued and REN is set.
30.2.3.1 SMC Function Code Registers (RFCR/TFCR)
Each SMC channel has two function code registersÑone for receiving (RFCRn) and one
for transmitting (TFCRn). The function code entry contains the value to appear on the
function code pins AT[1Ð3] when the associated SDMA channel accesses memory. The
FCRs also control byte-ordering. See Figure 30-4.
Table 30-3 describes RFCR Þelds.
30.2.4 Disabling SMCs On-the-Fly
An SMC can be disabled and reenabled later by ensuring that buffers are closed properly
and new data is transferred to or from a new buffer. Such a sequence is required if the
parameters to be changed are not dynamic. If the register or bit description states that
Bit 0 1 2 3 4 5 6 7
Field Ñ BO AT[1Ð3]
R/W R/W
Address SMC base + 0x04 (RFCR)/SMC base + 0x05 (TFCR)
Figure 30-4. SMC Function Code Registers (RFCR/TFCR)
Table 30-3. RFCR/TFCR Field Descriptions
Bit Name Description
0Ð2 Ñ Reserved, should be cleared.
3Ð4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy, it
takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the beginning of
the next BD. See Appendix A, ÒByte Ordering.Ó
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
5Ð7 AT[1Ð3] Address type 1Ð3. Contains the user-deÞned function code value used during the SDMA channel
memory access. AT[0] is always driven high to identify this channel access as a DMA-type access.