Motorola MPC860 PowerQUICC, User Manual

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8-14 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
Table 8-7 describes the bits of the DC_ADR register.
The DC_DAT register, shown in Figure 8-8, has an SPR encoding of 570.
Table 8-8 describes the bits of the DC_DAT register.
8.3.2.1 Reading Data Cache Tags and Copyback Buffer
The MPC860 supports reading the tags, the state bits and the lock bits stored in the data
cache as well as the last copyback address, and data words in the copyback buffer. The data
cache read command, issued by reading DC_DAT, uses the DC_ADR register to qualify
what is to be read. Table 8-4 describes the Þelds of the DC_ADR register during a data
cache read command.
Table 8-7. Data Cache Address RegisterÑDC_ADR
Bits Name Description
0Ð31 ADR Data cache command address. When programming the DC_CST load & lock cache block, unlock
cache block, and ßush cache block commands, DC_ADR contains the physical address of the
desired cache block element in external memory. When reading the data, tags, and status
contained within the data cache, DC_ADR is used to qualify what is to be read according to
Table 8-7. See Section 8.3.2.1, ÒReading Data Cache Tags and Copyback Buffer,Ó for more
information.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD DAT
RESET Ñ
R/W R/W
SPR 570
Figure 8-8. Data Cache Data Port Register (DC_DAT)
Table 8-8. Data Cache Data Port RegisterÑDC_DAT
Bits Name Description
0Ð31 DAT Data cache command data. The data received when reading information from the data cache. See
Section 8.3.2.1, ÒReading Data Cache Tags and Copyback Buffer,Ó for more information.
Table 8-9. DC_ADR Fields for Cache Read Commands
0Ð17 18 19 20 21Ð27 28Ð31
Reserved 0 Tags 0 Way 0
1 Way 1 Reserved Set select
(0Ð127)
Reserved
1 Copyback
buffer
Reserved Copyback buffer
address/
data-word select
Reserved