Motorola MPC860 PowerQUICC, User Manual

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6-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
The sync instruction delays execution of subsequent instructions until previous instructions
have completed to the point that they can no longer cause an exception and until all previous
memory accesses are performed globally; the sync operation is not broadcast onto the
MPC860 bus interface. Additionally, all load and store cache/bus activities initiated by prior
instructions are completed. Touch load operations (dcbt and dcbtst) are required to
complete at least through address translation, but not required to complete on the bus.
The functions performed by the sync instruction normally take a signiÞcant amount of time
to complete; as a result, frequent use of this instruction may adversely affect performance.
In addition, the number of cycles required to complete a sync instruction depends on
system parameters and on the processor's state when the instruction is issued.
The proper paired use of the l wa rx and stwcx. instructions allows programmers to emulate
common semaphore operations such as Òtest and set,Ó Òcompare and swap,Ó Òexchange
memory,Ó and Òfetch and add.Ó Examples of these semaphore operations can be found in
Appendix E, ÒSynchronization Programming Examples,Ó in The Programming
Environments Manual. The lwarx instruction must be paired with an stwcx. instruction
with the same effective address used for both instructions of the pair. Note that the
reservation granularity is 16 bytes.
The lwarx and stwcx. instructions are implemented according to the PowerPC architecture
requirements. The concept behind the use of the lwarx and stwcx. instructions is that a
processor may load a semaphore from memory, compute a result based on the value of the
semaphore, and conditionally store it back to the same location (only if that location has
not been modiÞed since it was Þrst read), and determine if the store was successful. The
conditional store is performed based upon the existence of a reservation established by the
preceding lwarx instruction. If the reservation exists when the store is executed, the store
is performed and a bit is set in the CR. If the reservation does not exist when the store is
executed, the target memory location is not modiÞed and a bit is cleared in the CR.
If the store was successful, the sequence of instructions from the read of the semaphore to
the store that updated the semaphore appear to have been executed atomically (that is, no
other processor or mechanism modiÞed the semaphore location between the read and the
update), thus providing the equivalent of a real atomic operation. However, in reality, other
processors may have read from the location during this operation. In the MPC860, the
reservations are made on behalf of aligned 16-byte sections of the memory address space.
Table 6-16. Memory Synchronization InstructionsÑUISA
Name Mnemonic Syntax
Load Word and Reserve Indexed lwarx r D ,r A ,r B
Store Word Conditional Indexed stwcx. r S ,r A ,r B
Synchronize sync Ñ