Motorola MPC860 PowerQUICC, User Manual

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3-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part I. Overview
GPL_A[2Ð3]
GPL_B[2Ð3]
CS[2Ð3] Output General-Purpose Line 2 and 3 on UPMAÑThese outputs reßect the value speciÞed
in the UPMA when an external transfer to a slave is controlled by UPMA.
General-Purpose Line 2 and 3 on UPMBÑThese outputs reßect the value speciÞed
in the UPMB when an external transfer to a slave is controlled by UPMB.
Chip Select 2 and 3ÑThese outputs enable peripheral or memory devices at
programmed addresses if they are appropriately deÞned. The double drive capability
for CS2 and CS3 is independently deÞned for each signal in the SIUMCR.
UPWAITA
GPL_A4 Bidirectional User Programmable Machine Wait AÑThis input is sampled as deÞned by the user
when an access to an external slave is controlled by the UPMA.
General-Purpose Line 4 on UPMAÑThis output reßects the value speciÞed in the
UPMA when an external transfer to a slave is controlled by UPMA.
UPWAITB
GPL_B4 Bidirectional User Programmable Machine Wait BÑThis input is sampled as deÞned by the user
when an access to an external slave is controlled by the UPMB.
General-Purpose Line 4 on UPMBÑThis output reßects the value speciÞed in the
UPMB when an external transfer to a slave is controlled by UPMB.
GPL_A5 Output General-Purpose Line 5 on UPMAÑThis output reßects the value speciÞed in the
UPMA when an external transfer to a slave is controlled by UPMA. This signal can
also be controlled by the UPMB.
PORESET Input Power on ResetÑWhen asserted, this input causes the MPC860 to enter the
power-on reset state.
RSTCONF Input Reset ConÞgurationÑThe MPC860 samples this input while HRESET is asserted. If
RSTCONF is asserted, the conÞguration mode is sampled in the form of the hard
reset conÞguration word driven on the data bus. When RSTCONF is negated, the
MPC860 uses the default conÞguration mode. Note that the initial base address of
internal registers is determined in this sequence.
HRESET Open-drain Hard ResetÑAsserting this open drain signal puts the MPC860 in hard reset state.
SRESET Open-drain Soft ResetÑAsserting this open drain line puts the MPC860 in soft reset state.
XTAL Analog
Output
This output is one of the connections to an external crystal for the internal oscillator
circuitry.
EXTAL Analog Input
(3.3V only)
This line is one of the connections to an external crystal for the internal oscillator
circuitry.
XFC Analog Input External Filter CapacitanceÑThis input is the connection pin for an external
capacitor Þlter for the PLL circuitry.
CLKOUT Output Clock OutÑThis output is the clock system frequency.
EXTCLK Input
(3.3V only)
External ClockÑThis input is the external input clock from an external source.
TEXP Output Timer ExpiredÑThis output reßects the status of PLPRCR[TEXPS].
ALE_A Output Address Latch Enable AÑThis output is asserted when MPC860 initiates an access
to a region under the control of the PCMCIA interface to socket A.
CE1_A Output Card Enable 1 Slot AÑThis output enables even byte transfers when accesses to
PCMCIA Slot A are handled under the control of the PCMCIA interface.
CE2_A Output Card Enable 2 Slot AÑThis output enables odd byte transfers when accesses to
PCMCIA Slot A are handled under the control of the PCMCIA interface.
Table 3-1. Signal Descriptions (Continued)
Name Type Description