Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 16. Memory Controller 16-5
Part IV. Hardware Interface
speciÞc memory bank in the base register. The type of parity is deÞned in the system
interface unit module conÞguration register (SIUMCR), which is explained in
Section 11.4.2, ÒSIU Module ConÞguration Register (SIUMCR).Ó
¥ Each memory bank can be selected for read-only or read/write operation.
¥ For system protection, access to a memory bank can be restricted to accesses with
certain address type codes (AT[0Ð2]). For additional ßexibility, address-type
comparisons provide a mask option.
The memory controller functionality minimizes the need for glue logic in MPC860-based
systems. In Figure 16-3, CS0 is used with the 16-bit boot EPROM with BR0[MS]
defaulting to select the GPCM. CS1 is used as the RAS signal for 32-bit DRAM with
BR1[MS] conÞgured to select UPMA. The BS_A signals are used as CAS signals on the
DRAM.
Figure 16-3. Simple System Configuration
The UPMs provide a ßexible interface to many types of memory devices. Each UPM can
control the address multiplexing necessary to access DRAM devices, the timing of the BS
signals, and the timing of the GPL signals. Each memory bank can be assigned to either
UPM.
Each UPM is a programmable RAM-based machine. The UPM toggles the memory
controller external signals as programmed in RAM when an internal or external master
initiates an external single-beat or burst read/write access. The UPM also controls address
multiplexing, address increment, and transfer acknowledge assertion for each memory
access. The UPM speciÞes a set of signal patterns for a user-speciÞed number of clock
cycles. The UPM RAM pattern run by the memory controller is selected according to the
type of external access transacted. At every clock cycle, the logical value of the external
Address
CE
OE
WE
Data
EPROM
RAS
CAS[0Ð3]
W
Data
Parity[0Ð3]
DRAM
CS1
R/W
Data
WE[0Ð1]
GPL1/OE
CS0
Address
Address
DP[0Ð3]
BS_A[0Ð3] UPMA
GPCM
MPC860