Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 8. Instruction and Data Caches 8-23
Part II. PowerPC Microprocessor Module
the cache can service a hit while a cache miss Þll is waiting to complete. If no bus errors
are encountered during the 4-word cache block fetch, the burst buffer is marked valid and
written to the cache array, provided the cache array is not busy servicing a hit.
If a bus error is encountered while fetching the requested instruction (the critical word),
then a machine check exception is generated. If a bus error occurs while fetching
subsequent words in the cache block, then the burst buffer is marked invalid and the cache
block is not written to the cache array.
8.5.3 Instruction Fetching on a Predicted Path
The core implements branch prediction to allow branches to issue as early as possible. This
mechanism allows instruction prefetching to continue while an unresolved branch is being
computed and the condition is being evaluated. Instructions fetched after unresolved
branches are said to be fetched on a predicted path. These instructions may be discarded
later if it turns out that the machine has followed the wrong path. To minimize power
consumption, the MPC860 instruction cache does not initiate a miss sequence in most cases
when the instruction is inside a predicted path. The MPC860 instruction cache evaluates
fetch requests to see if they are inside a predicted path. If a hit is detected, the requested
instruction is delivered to the core. However, if it is a cache miss, the miss sequence is not
initiated in most cases until the core Þnishes the branch evaluation.
8.5.4 Fetching Instructions from Caching-Inhibited Regions
The caching-inhibited/caching-allowed attributes of a memory region are programmed in
the memory management unit (MMU). To improve performance when fetching instructions
from caching-inhibited regions, the MPC860 loads the burst buffer with a full 4-word
block. Instructions that are stored in the burst buffer and originate from a cache-inhibited
region, can be sent to the instruction sequencer, at most, once before being refetched.
If an instruction fetch from a caching-inhibited region results in a cache hit, the instruction
is delivered to the instruction sequencer in the core from the cache and not from memory.
However, it is considered a programming error if an instruction fetch from a
caching-inhibited region results in a cache hit. Software must ensure that instructions from
a caching-inhibited region have not been previously loaded into the cache, or, if so, those
blocks have been ßushed from the cache. See Section 8.5.5, ÒUpdating Code And Memory
Region Attributes,Ó for more information.
It is also considered a programming error to perform load & lock cache block operations
from zero wait state devices that are located on the internal bus. The MPC860 considers
these devices as caching-inhibited memory regions. If a load & lock cache block operation
is performed from such a device, the instruction is not guaranteed to be fetched from the
instruction cache; in most cases, the instruction is fetched from the device, regardless of
whether it is in the instruction cache.