Motorola MPC860 PowerQUICC, User Manual

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MOTOROLA Chapter 33. Parallel Interface Port 33-19
Part V. The Communications Processor Module
Figure 33-18. PIP Receiver TimingÑMode 3
33.8 Transparent Transfers
The timing of transparent transfers, shown in Figure 33-19, is controlled by the timing of
the strobe signal STBI (PB14). Transparent transfers must be controlled by the CP, which
requires BD and parameter RAM initialization. The CP moves data in and out of buffers
using the virtual SDMA channels dedicated to SMC2. The falling edge of STBI generates
the request to the CP causing it to send or receive data. Signal direction is controlled by the
port B data direction register (PBDIR[14]).
Figure 33-19. PIP Transparent Transfers
33.9 Implementing Centronics
The PIP can implement a Centronics-compatible interface for both sending and receiving.
The Centronics protocol is a parallel peripheral interface for communicating between a host
computer and a printer. To implement Centronics, the PIP uses an 8-bit data bus, two
handshake signals that control the data exchange, and signals that reßect the peripheral
device status.
STB
BUSY
(PB31)
ACK
TPAR1 TPAR2
BUSY
Cleared
by S/W
Latch Buffer
I/O PB14
Write from CP Read from CP
DIR = Output
Peripheral Bus