Motorola MPC860 PowerQUICC, User Manual

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29-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part V. The Communications Processor Module
Data length and buffer pointer Þelds are described in Section 22.2, ÒSCC Buffer
Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater
than zero. The CPM writes these Þelds after it Þnishes sending the buffer. The Rx buffer
pointer must be divisible by four, unless GSMR_H[RFW] is set to 8 bits wide, in which
case the pointer can be even or odd. The buffer can reside in internal or external memory.
29.11 SCC Transparent Transmit Buffer Descriptor
(TxBD)
Data is sent to the CPM for transmission on an SCC channel by arranging it in buffers
referenced by the TxBD table. The CPM uses BDs to conÞrm transmission or indicate error
conditions so the processor knows buffers have been serviced. Prepare status and control
bits before transmission; they are set by the CPM after the buffer is sent.
4 L Last in frame. Set by the transparent controller when this buffer is the last in a frame, which occurs
when CD is negated (if GSMR_H[CDP] = 0) or an error is received. If an error is received, one or more
of RxBD[OV, CD, DE] are set. The transparent controller writes the number of frame octets to the BDÕs
data length Þeld.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5 F First in frame. The transparent controller sets F when this buffer is the Þrst in the frame:
0 Not the Þrst buffer in a frame.
1 First buffer in a frame.
6 CM Continuous mode.
0 Normal operation.
1 The CPM does not clear RxBD[E] after this BD is closed, letting the buffer be overwritten when the
CPM next accesses this BD. However, RxBD[E] is cleared if an error occurs during reception,
regardless of how CM is set.
7 Ñ Reserved, should be cleared.
8 DE DPLL error. Set by the transparent controller when a DPLL error occurs as this buffer is received. In
decoding modes, where a transition is promised every bit, DE is set when a missing transition occurs.
If a DPLL error occurs, no other error checking is performed.
9Ð10 Ñ Reserved, should be cleared.
11 NO Rx non-octet. Set when a frame containing a number of bits not exactly divisible by eight is received.
12 Ñ Reserved, should be cleared.
13 CR CRC error indication bits. Indicates that this frame contains a CRC error. The received CRC bytes are
always written to the receive buffer. CRC checking cannot be disabled, but it can be ignored.
14 OV Overrun. Indicates that a receiver overrun occurred during buffer reception.
15 CD Carrier detect lost. Indicates when CD is negated during buffer reception.
Table 29-7. SCC Transparent RxBD Status and Control Field Descriptions
(Continued)
Bits Name Description