Motorola MPC860 PowerQUICC, User Manual, Page: 510 / 1106

17-6 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part IV. Hardware Interface
17.3.1 Memory-Only Cards
Table 17-5 lists worst-case conditions of host programming memory cards and assumes
WAIT is not used. If it is, the minimum strobe time is at least 35 ns + 1 system clock.
17.3.2 I/O Cards
Table 17-6 lists worst-case conditions of host programming I/O cards.
17.3.3 Interrupts
The PCMCIA interface input pins register (PIPR) reports any changes on inputs from the
PCMCIA card to the host (BVD, CD, RDY, VS). The contents of the PCMCIA interface
status changed register (PSCR) are logically ANDed with the PCMCIA interface enable
register (PER) to generate a PCMCIA interface interrupt. The interrupt level is user
programmable and the PCMCIA interface can generate an additional interrupt for
RDY/IRQ that can trigger on level (low or high) or edge (fall or rise) of the input signal.
1
Because the minimum hold time is one clock, the real access time is, access time + one clock.
2
Worst-case setup time (STP). The worst-case setup time is address to strobe.
3
Length (LNG) is the minimum strobe time.
4
Worst-case hold time (HLD). The worst-case hold time is data disable from OE.
1
Setup time worst-case is for a write. In these cases, setup=data_set_up_befor1 clock.
Table 17-5. Host Programming for Memory Cards
Memory Access
Time
1
600 ns 200 ns 150 ns 100 ns
STP
2
LNG
3
HLD
4
STP LNG HLD STP LNG HLD STP LNG HLD
Clock Cycle 100 300 150 30 120 90 20 80 75 15 60 50
20 ns (50 MHz) 6 24 8 2 8 5 2 6 4 1 4 3
30 ns (33.3 MHz) 4 16 5 2 5 3 1 4 3 1 3 2
40 ns (25 MHz) 3 12 4 1 4 3 1 3 2 1 2 2
62 ns (16 MHz) 2 8 3 1 2 2 1 2 2 1 1 1
83 ns (12 MHz) 2 6 2 1 2 2 1 1 1 1 1 1
Table 17-6. Host Programming For I/O Cards
Frequency
STP
1
LNG HLD
60 165 30
20 ns (50 MHz) 4 8 2
30 ns (33.3 MHz) 3 6 1
40 ns (25 MHz) 3 4 1
62 ns (16 MHz) 2 3 1
83 ns (12 MHz) 2 2 1