Motorola MPC860 PowerQUICC, User Manual

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8-8 MPC860 PowerQUICC UserÕs Manual MOTOROLA
Part II. PowerPC Microprocessor Module
The IC_ADR register, shown in Figure 8-4, has an SPR encoding of 561.
Table 8-2 describes the bits of the IC_ADR register.
The IC_DAT register, shown in Figure 8-5, has an SPR encoding of 562.
Table 8-3 describes the bits of the IC_DAT register.
8.3.1.1 Reading Data and Tags within the Instruction Cache
The MPC860 supports reading the data, tags, and the state and lock bits stored in the
instruction cache. The instruction cache read command, issued by reading the IC_DAT
register, uses the IC_ADR register to qualify what is to be read. Table 8-4 describes the
Þelds of the IC_ADR register during an instruction cache read command.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD ADR
RESET Ñ
R/W R/W
SPR 561
Figure 8-4. Instruction Cache Address Register (IC_ADR)
Table 8-2. Instruction Cache Address RegisterÑIC_ADR
Bits Name Description
0Ð31 ADR Instruction cache command address. When programming the IC_CST[CMD] load & lock cache block
and unlock cache block commands, IC_ADR contains the physical address in external memory of
the desired cache block element. When reading the data, tags, and status contained within the
instruction cache, IC_ADR is used to qualify what is to be read according to Table 8-4. See
Section 8.3.1.1, ÒReading Data and Tags within the Instruction Cache,Ó for more information.
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD DAT
RESET Ñ
R/W R/W
SPR 562
Figure 8-5. Instruction Cache Data Port Register (IC_DAT)
Table 8-3. Instruction Cache Data Port RegisterÑIC_DAT
Bits Name Description
0Ð31 DAT Instruction cache command data. The data received when reading information from the
instruction cache. See Section 8.3.1.1, ÒReading Data and Tags within the Instruction Cache,Ó
for more information.